1; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
2
3; This tests that indirectbr instructions are lowered to switches. Currently we
4; just re-use the IndirectBrExpand Pass; it has its own IR-level test.
5; So this test just ensures that the pass gets run and we can lower indirectbr
6
7target triple = "wasm32"
8
9@test1.targets = constant [4 x i8*] [i8* blockaddress(@test1, %bb0),
10                                     i8* blockaddress(@test1, %bb1),
11                                     i8* blockaddress(@test1, %bb2),
12                                     i8* blockaddress(@test1, %bb3)]
13
14; Just check the barest skeleton of the structure
15; CHECK-LABEL: test1:
16; CHECK: block
17; CHECK: block
18; CHECK: block
19; CHECK: block
20; CHECK: i32.load
21; CHECK: i32.load
22; CHECK: i32.const
23; CHECK: i32.add $push[[DEST:.+]]=
24; CHECK: br_table $pop[[DEST]]
25; CHECK: end_block
26; CHECK: end_block
27; CHECK: end_block
28; CHECK: end_block
29; CHECK: loop
30; CHECK: block
31; CHECK: block
32; CHECK: block
33; CHECK: block
34; CHECK: br_table ${{[^,]+}}, 0, 1, 2, 2
35; CHECK: end_block
36; CHECK: end_block
37; CHECK: end_block
38; CHECK: block
39; CHECK: block
40; CHECK: block
41; CHECK: br_table ${{[^,]+}}, 1, 2, 0
42; CHECK: end_block
43; CHECK: end_block
44; CHECK: end_block
45; CHECK: end_loop
46; CHECK: test1.targets:
47; CHECK-NEXT: .int32
48; CHECK-NEXT: .int32
49; CHECK-NEXT: .int32
50; CHECK-NEXT: .int32
51
52define void @test1(i32* readonly %p, i32* %sink) #0 {
53
54entry:
55  %i0 = load i32, i32* %p
56  %target.i0 = getelementptr [4 x i8*], [4 x i8*]* @test1.targets, i32 0, i32 %i0
57  %target0 = load i8*, i8** %target.i0
58  ; Only a subset of blocks are viable successors here.
59  indirectbr i8* %target0, [label %bb0, label %bb1]
60
61
62bb0:
63  store volatile i32 0, i32* %sink
64  br label %latch
65
66bb1:
67  store volatile i32 1, i32* %sink
68  br label %latch
69
70bb2:
71  store volatile i32 2, i32* %sink
72  br label %latch
73
74bb3:
75  store volatile i32 3, i32* %sink
76  br label %latch
77
78latch:
79  %i.next = load i32, i32* %p
80  %target.i.next = getelementptr [4 x i8*], [4 x i8*]* @test1.targets, i32 0, i32 %i.next
81  %target.next = load i8*, i8** %target.i.next
82  ; A different subset of blocks are viable successors here.
83  indirectbr i8* %target.next, [label %bb1, label %bb2]
84}
85