1; Test vector insertion of register variables.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
4
5; Test v16i8 insertion into the first element.
6define <16 x i8> @f1(<16 x i8> %val, i8 %element) {
7; CHECK-LABEL: f1:
8; CHECK: vlvgb %v24, %r2, 0
9; CHECK: br %r14
10  %ret = insertelement <16 x i8> %val, i8 %element, i32 0
11  ret <16 x i8> %ret
12}
13
14; Test v16i8 insertion into the last element.
15define <16 x i8> @f2(<16 x i8> %val, i8 %element) {
16; CHECK-LABEL: f2:
17; CHECK: vlvgb %v24, %r2, 15
18; CHECK: br %r14
19  %ret = insertelement <16 x i8> %val, i8 %element, i32 15
20  ret <16 x i8> %ret
21}
22
23; Test v16i8 insertion into a variable element.
24define <16 x i8> @f3(<16 x i8> %val, i8 %element, i32 %index) {
25; CHECK-LABEL: f3:
26; CHECK: vlvgb %v24, %r2, 0(%r3)
27; CHECK: br %r14
28  %ret = insertelement <16 x i8> %val, i8 %element, i32 %index
29  ret <16 x i8> %ret
30}
31
32; Test v8i16 insertion into the first element.
33define <8 x i16> @f4(<8 x i16> %val, i16 %element) {
34; CHECK-LABEL: f4:
35; CHECK: vlvgh %v24, %r2, 0
36; CHECK: br %r14
37  %ret = insertelement <8 x i16> %val, i16 %element, i32 0
38  ret <8 x i16> %ret
39}
40
41; Test v8i16 insertion into the last element.
42define <8 x i16> @f5(<8 x i16> %val, i16 %element) {
43; CHECK-LABEL: f5:
44; CHECK: vlvgh %v24, %r2, 7
45; CHECK: br %r14
46  %ret = insertelement <8 x i16> %val, i16 %element, i32 7
47  ret <8 x i16> %ret
48}
49
50; Test v8i16 insertion into a variable element.
51define <8 x i16> @f6(<8 x i16> %val, i16 %element, i32 %index) {
52; CHECK-LABEL: f6:
53; CHECK: vlvgh %v24, %r2, 0(%r3)
54; CHECK: br %r14
55  %ret = insertelement <8 x i16> %val, i16 %element, i32 %index
56  ret <8 x i16> %ret
57}
58
59; Test v4i32 insertion into the first element.
60define <4 x i32> @f7(<4 x i32> %val, i32 %element) {
61; CHECK-LABEL: f7:
62; CHECK: vlvgf %v24, %r2, 0
63; CHECK: br %r14
64  %ret = insertelement <4 x i32> %val, i32 %element, i32 0
65  ret <4 x i32> %ret
66}
67
68; Test v4i32 insertion into the last element.
69define <4 x i32> @f8(<4 x i32> %val, i32 %element) {
70; CHECK-LABEL: f8:
71; CHECK: vlvgf %v24, %r2, 3
72; CHECK: br %r14
73  %ret = insertelement <4 x i32> %val, i32 %element, i32 3
74  ret <4 x i32> %ret
75}
76
77; Test v4i32 insertion into a variable element.
78define <4 x i32> @f9(<4 x i32> %val, i32 %element, i32 %index) {
79; CHECK-LABEL: f9:
80; CHECK: vlvgf %v24, %r2, 0(%r3)
81; CHECK: br %r14
82  %ret = insertelement <4 x i32> %val, i32 %element, i32 %index
83  ret <4 x i32> %ret
84}
85
86; Test v2i64 insertion into the first element.
87define <2 x i64> @f10(<2 x i64> %val, i64 %element) {
88; CHECK-LABEL: f10:
89; CHECK: vlvgg %v24, %r2, 0
90; CHECK: br %r14
91  %ret = insertelement <2 x i64> %val, i64 %element, i32 0
92  ret <2 x i64> %ret
93}
94
95; Test v2i64 insertion into the last element.
96define <2 x i64> @f11(<2 x i64> %val, i64 %element) {
97; CHECK-LABEL: f11:
98; CHECK: vlvgg %v24, %r2, 1
99; CHECK: br %r14
100  %ret = insertelement <2 x i64> %val, i64 %element, i32 1
101  ret <2 x i64> %ret
102}
103
104; Test v2i64 insertion into a variable element.
105define <2 x i64> @f12(<2 x i64> %val, i64 %element, i32 %index) {
106; CHECK-LABEL: f12:
107; CHECK: vlvgg %v24, %r2, 0(%r3)
108; CHECK: br %r14
109  %ret = insertelement <2 x i64> %val, i64 %element, i32 %index
110  ret <2 x i64> %ret
111}
112
113; Test v2f64 insertion into the first element.
114define <2 x double> @f16(<2 x double> %val, double %element) {
115; CHECK-LABEL: f16:
116; CHECK: vpdi %v24, %v0, %v24, 1
117; CHECK: br %r14
118  %ret = insertelement <2 x double> %val, double %element, i32 0
119  ret <2 x double> %ret
120}
121
122; Test v2f64 insertion into the last element.
123define <2 x double> @f17(<2 x double> %val, double %element) {
124; CHECK-LABEL: f17:
125; CHECK: vpdi %v24, %v24, %v0, 0
126; CHECK: br %r14
127  %ret = insertelement <2 x double> %val, double %element, i32 1
128  ret <2 x double> %ret
129}
130
131; Test v2f64 insertion into a variable element.
132define <2 x double> @f18(<2 x double> %val, double %element, i32 %index) {
133; CHECK-LABEL: f18:
134; CHECK: lgdr [[REG:%r[0-5]]], %f0
135; CHECK: vlvgg %v24, [[REG]], 0(%r2)
136; CHECK: br %r14
137  %ret = insertelement <2 x double> %val, double %element, i32 %index
138  ret <2 x double> %ret
139}
140
141; Test v16i8 insertion into a variable element plus one.
142define <16 x i8> @f19(<16 x i8> %val, i8 %element, i32 %index) {
143; CHECK-LABEL: f19:
144; CHECK: vlvgb %v24, %r2, 1(%r3)
145; CHECK: br %r14
146  %add = add i32 %index, 1
147  %ret = insertelement <16 x i8> %val, i8 %element, i32 %add
148  ret <16 x i8> %ret
149}
150