1; Test vector stores.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
4
5; Test v16i8 stores.
6define void @f1(<16 x i8> %val, <16 x i8> *%ptr) {
7; CHECK-LABEL: f1:
8; CHECK: vst %v24, 0(%r2)
9; CHECK: br %r14
10  store <16 x i8> %val, <16 x i8> *%ptr
11  ret void
12}
13
14; Test v8i16 stores.
15define void @f2(<8 x i16> %val, <8 x i16> *%ptr) {
16; CHECK-LABEL: f2:
17; CHECK: vst %v24, 0(%r2)
18; CHECK: br %r14
19  store <8 x i16> %val, <8 x i16> *%ptr
20  ret void
21}
22
23; Test v4i32 stores.
24define void @f3(<4 x i32> %val, <4 x i32> *%ptr) {
25; CHECK-LABEL: f3:
26; CHECK: vst %v24, 0(%r2)
27; CHECK: br %r14
28  store <4 x i32> %val, <4 x i32> *%ptr
29  ret void
30}
31
32; Test v2i64 stores.
33define void @f4(<2 x i64> %val, <2 x i64> *%ptr) {
34; CHECK-LABEL: f4:
35; CHECK: vst %v24, 0(%r2)
36; CHECK: br %r14
37  store <2 x i64> %val, <2 x i64> *%ptr
38  ret void
39}
40
41; Test v2f64 stores.
42define void @f6(<2 x double> %val, <2 x double> *%ptr) {
43; CHECK-LABEL: f6:
44; CHECK: vst %v24, 0(%r2)
45; CHECK: br %r14
46  store <2 x double> %val, <2 x double> *%ptr
47  ret void
48}
49
50; Test the highest aligned in-range offset.
51define void @f7(<16 x i8> %val, <16 x i8> *%base) {
52; CHECK-LABEL: f7:
53; CHECK: vst %v24, 4080(%r2)
54; CHECK: br %r14
55  %ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 255
56  store <16 x i8> %val, <16 x i8> *%ptr
57  ret void
58}
59
60; Test the highest unaligned in-range offset.
61define void @f8(<16 x i8> %val, i8 *%base) {
62; CHECK-LABEL: f8:
63; CHECK: vst %v24, 4095(%r2)
64; CHECK: br %r14
65  %addr = getelementptr i8, i8 *%base, i64 4095
66  %ptr = bitcast i8 *%addr to <16 x i8> *
67  store <16 x i8> %val, <16 x i8> *%ptr, align 1
68  ret void
69}
70
71; Test the next offset up, which requires separate address logic,
72define void @f9(<16 x i8> %val, <16 x i8> *%base) {
73; CHECK-LABEL: f9:
74; CHECK: aghi %r2, 4096
75; CHECK: vst %v24, 0(%r2)
76; CHECK: br %r14
77  %ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 256
78  store <16 x i8> %val, <16 x i8> *%ptr
79  ret void
80}
81
82; Test negative offsets, which also require separate address logic,
83define void @f10(<16 x i8> %val, <16 x i8> *%base) {
84; CHECK-LABEL: f10:
85; CHECK: aghi %r2, -16
86; CHECK: vst %v24, 0(%r2)
87; CHECK: br %r14
88  %ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 -1
89  store <16 x i8> %val, <16 x i8> *%ptr
90  ret void
91}
92
93; Check that indexes are allowed.
94define void @f11(<16 x i8> %val, i8 *%base, i64 %index) {
95; CHECK-LABEL: f11:
96; CHECK: vst %v24, 0(%r3,%r2)
97; CHECK: br %r14
98  %addr = getelementptr i8, i8 *%base, i64 %index
99  %ptr = bitcast i8 *%addr to <16 x i8> *
100  store <16 x i8> %val, <16 x i8> *%ptr, align 1
101  ret void
102}
103