1; Test vector register moves.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
4
5; Test v16i8 moves.
6define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
7; CHECK-LABEL: f1:
8; CHECK: vlr %v24, %v26
9; CHECK: br %r14
10  ret <16 x i8> %val2
11}
12
13; Test v8i16 moves.
14define <8 x i16> @f2(<8 x i16> %val1, <8 x i16> %val2) {
15; CHECK-LABEL: f2:
16; CHECK: vlr %v24, %v26
17; CHECK: br %r14
18  ret <8 x i16> %val2
19}
20
21; Test v4i32 moves.
22define <4 x i32> @f3(<4 x i32> %val1, <4 x i32> %val2) {
23; CHECK-LABEL: f3:
24; CHECK: vlr %v24, %v26
25; CHECK: br %r14
26  ret <4 x i32> %val2
27}
28
29; Test v2i64 moves.
30define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) {
31; CHECK-LABEL: f4:
32; CHECK: vlr %v24, %v26
33; CHECK: br %r14
34  ret <2 x i64> %val2
35}
36
37; Test v2f64 moves.
38define <2 x double> @f6(<2 x double> %val1, <2 x double> %val2) {
39; CHECK-LABEL: f6:
40; CHECK: vlr %v24, %v26
41; CHECK: br %r14
42  ret <2 x double> %val2
43}
44