1; RUN: llc < %s -mtriple=s390x-linux-gnu -verify-machineinstrs | FileCheck %s 2; RUN: llc < %s -mtriple=s390x-linux-gnu -O0 -verify-machineinstrs | FileCheck --check-prefix=CHECK-O0 %s 3 4@var = global i32 0 5 6; Test how llvm handles return type of {i16, i8}. The return value will be 7; passed in %r2 and %r3. 8; CHECK-LABEL: test: 9; CHECK: st %r2 10; CHECK: brasl %r14, gen 11; CHECK-DAG: lhr %r2, %r2 12; CHECK-DAG: lbr %[[REG1:r[0-9]+]], %r3 13; CHECK: ar %r2, %[[REG1]] 14; CHECK-O0-LABEL: test 15; CHECK-O0: st %r2 16; CHECK-O0: brasl %r14, gen 17; CHECK-O0-DAG: lhr %[[REG1:r[0-9]+]], %r2 18; CHECK-O0-DAG: lbr %[[REG2:r[0-9]+]], %r3 19; CHECK-O0: ar %[[REG1]], %[[REG2]] 20; CHECK-O0: lr %r2, %[[REG1]] 21define i16 @test(i32 %key) { 22entry: 23 %key.addr = alloca i32, align 4 24 store i32 %key, i32* %key.addr, align 4 25 %0 = load i32, i32* %key.addr, align 4 26 %call = call swiftcc { i16, i8 } @gen(i32 %0) 27 %v3 = extractvalue { i16, i8 } %call, 0 28 %v1 = sext i16 %v3 to i32 29 %v5 = extractvalue { i16, i8 } %call, 1 30 %v2 = sext i8 %v5 to i32 31 %add = add nsw i32 %v1, %v2 32 %conv = trunc i32 %add to i16 33 ret i16 %conv 34} 35 36declare swiftcc { i16, i8 } @gen(i32) 37 38; If we can't pass every return value in registers, we will pass everything 39; in memroy. The caller provides space for the return value and passes 40; the address in %r2. The first input argument will be in %r3. 41; CHECK-LABEL: test2: 42; CHECK: lr %[[REG1:r[0-9]+]], %r2 43; CHECK-DAG: la %r2, 160(%r15) 44; CHECK-DAG: lr %r3, %[[REG1]] 45; CHECK: brasl %r14, gen2 46; CHECK: l %r2, 160(%r15) 47; CHECK: a %r2, 164(%r15) 48; CHECK: a %r2, 168(%r15) 49; CHECK: a %r2, 172(%r15) 50; CHECK: a %r2, 176(%r15) 51; CHECK-O0-LABEL: test2: 52; CHECK-O0: st %r2, [[SPILL1:[0-9]+]](%r15) 53; CHECK-O0: l %r3, [[SPILL1]](%r15) 54; CHECK-O0: la %r2, 168(%r15) 55; CHECK-O0: brasl %r14, gen2 56; CHECK-O0-DAG: l %r{{.*}}, 184(%r15) 57; CHECK-O0-DAG: l %r{{.*}}, 180(%r15) 58; CHECK-O0-DAG: l %r{{.*}}, 176(%r15) 59; CHECK-O0-DAG: l %r{{.*}}, 172(%r15) 60; CHECK-O0-DAG: l %r{{.*}}, 168(%r15) 61; CHECK-O0: ar 62; CHECK-O0: ar 63; CHECK-O0: ar 64; CHECK-O0: ar 65; CHECK-O0: lr %r2 66define i32 @test2(i32 %key) #0 { 67entry: 68 %key.addr = alloca i32, align 4 69 store i32 %key, i32* %key.addr, align 4 70 %0 = load i32, i32* %key.addr, align 4 71 %call = call swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %0) 72 73 %v3 = extractvalue { i32, i32, i32, i32, i32 } %call, 0 74 %v5 = extractvalue { i32, i32, i32, i32, i32 } %call, 1 75 %v6 = extractvalue { i32, i32, i32, i32, i32 } %call, 2 76 %v7 = extractvalue { i32, i32, i32, i32, i32 } %call, 3 77 %v8 = extractvalue { i32, i32, i32, i32, i32 } %call, 4 78 79 %add = add nsw i32 %v3, %v5 80 %add1 = add nsw i32 %add, %v6 81 %add2 = add nsw i32 %add1, %v7 82 %add3 = add nsw i32 %add2, %v8 83 ret i32 %add3 84} 85 86; The address of the return value is passed in %r2. 87; On return, %r2 will contain the adddress that has been passed in by the caller in %r2. 88; CHECK-LABEL: gen2: 89; CHECK: st %r3, 16(%r2) 90; CHECK: st %r3, 12(%r2) 91; CHECK: st %r3, 8(%r2) 92; CHECK: st %r3, 4(%r2) 93; CHECK: st %r3, 0(%r2) 94; CHECK-O0-LABEL: gen2: 95; CHECK-O0-DAG: st %r3, 16(%r2) 96; CHECK-O0-DAG: st %r3, 12(%r2) 97; CHECK-O0-DAG: st %r3, 8(%r2) 98; CHECK-O0-DAG: st %r3, 4(%r2) 99; CHECK-O0-DAG: st %r3, 0(%r2) 100define swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %key) { 101 %Y = insertvalue { i32, i32, i32, i32, i32 } undef, i32 %key, 0 102 %Z = insertvalue { i32, i32, i32, i32, i32 } %Y, i32 %key, 1 103 %Z2 = insertvalue { i32, i32, i32, i32, i32 } %Z, i32 %key, 2 104 %Z3 = insertvalue { i32, i32, i32, i32, i32 } %Z2, i32 %key, 3 105 %Z4 = insertvalue { i32, i32, i32, i32, i32 } %Z3, i32 %key, 4 106 ret { i32, i32, i32, i32, i32 } %Z4 107} 108 109; The return value {i32, i32, i32, i32} will be returned via registers 110; %r2, %r3, %r4, %r5. 111; CHECK-LABEL: test3: 112; CHECK: brasl %r14, gen3 113; CHECK: ar %r2, %r3 114; CHECK: ar %r2, %r4 115; CHECK: ar %r2, %r5 116; CHECK-O0-LABEL: test3: 117; CHECK-O0: brasl %r14, gen3 118; CHECK-O0: ar %r2, %r3 119; CHECK-O0: ar %r2, %r4 120; CHECK-O0: ar %r2, %r5 121define i32 @test3(i32 %key) #0 { 122entry: 123 %key.addr = alloca i32, align 4 124 store i32 %key, i32* %key.addr, align 4 125 %0 = load i32, i32* %key.addr, align 4 126 %call = call swiftcc { i32, i32, i32, i32 } @gen3(i32 %0) 127 128 %v3 = extractvalue { i32, i32, i32, i32 } %call, 0 129 %v5 = extractvalue { i32, i32, i32, i32 } %call, 1 130 %v6 = extractvalue { i32, i32, i32, i32 } %call, 2 131 %v7 = extractvalue { i32, i32, i32, i32 } %call, 3 132 133 %add = add nsw i32 %v3, %v5 134 %add1 = add nsw i32 %add, %v6 135 %add2 = add nsw i32 %add1, %v7 136 ret i32 %add2 137} 138 139declare swiftcc { i32, i32, i32, i32 } @gen3(i32 %key) 140 141; The return value {float, float, float, float} will be returned via registers 142; %f0, %f2, %f4, %f6. 143; CHECK-LABEL: test4: 144; CHECK: brasl %r14, gen4 145; CHECK: aebr %f0, %f2 146; CHECK: aebr %f0, %f4 147; CHECK: aebr %f0, %f6 148; CHECK-O0-LABEL: test4: 149; CHECK-O0: brasl %r14, gen4 150; CHECK-O0: aebr %f0, %f2 151; CHECK-O0: aebr %f0, %f4 152; CHECK-O0: aebr %f0, %f6 153define float @test4(float %key) #0 { 154entry: 155 %key.addr = alloca float, align 4 156 store float %key, float* %key.addr, align 4 157 %0 = load float, float* %key.addr, align 4 158 %call = call swiftcc { float, float, float, float } @gen4(float %0) 159 160 %v3 = extractvalue { float, float, float, float } %call, 0 161 %v5 = extractvalue { float, float, float, float } %call, 1 162 %v6 = extractvalue { float, float, float, float } %call, 2 163 %v7 = extractvalue { float, float, float, float } %call, 3 164 165 %add = fadd float %v3, %v5 166 %add1 = fadd float %add, %v6 167 %add2 = fadd float %add1, %v7 168 ret float %add2 169} 170 171declare swiftcc { float, float, float, float } @gen4(float %key) 172 173; CHECK-LABEL: consume_i1_ret: 174; CHECK: brasl %r14, produce_i1_ret 175; CHECK: nilf %r2, 1 176; CHECK: nilf %r3, 1 177; CHECK: nilf %r4, 1 178; CHECK: nilf %r5, 1 179; CHECK-O0-LABEL: consume_i1_ret: 180; CHECK-O0: brasl %r14, produce_i1_ret 181; CHECK-O0: nilf %r2, 1 182; CHECK-O0: nilf %r3, 1 183; CHECK-O0: nilf %r4, 1 184; CHECK-O0: nilf %r5, 1 185define void @consume_i1_ret() { 186 %call = call swiftcc { i1, i1, i1, i1 } @produce_i1_ret() 187 %v3 = extractvalue { i1, i1, i1, i1 } %call, 0 188 %v5 = extractvalue { i1, i1, i1, i1 } %call, 1 189 %v6 = extractvalue { i1, i1, i1, i1 } %call, 2 190 %v7 = extractvalue { i1, i1, i1, i1 } %call, 3 191 %val = zext i1 %v3 to i32 192 store i32 %val, i32* @var 193 %val2 = zext i1 %v5 to i32 194 store i32 %val2, i32* @var 195 %val3 = zext i1 %v6 to i32 196 store i32 %val3, i32* @var 197 %val4 = zext i1 %v7 to i32 198 store i32 %val4, i32* @var 199 ret void 200} 201 202declare swiftcc { i1, i1, i1, i1 } @produce_i1_ret() 203