1; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s  | FileCheck %s
2
3; Store a <4 x i31> vector.
4define void @fun0(<4 x i31> %src, <4 x i31>* %p)
5; CHECK-LABEL: fun0:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    vlgvf %r1, %v24, 0
8; CHECK-NEXT:    vlgvf %r0, %v24, 1
9; CHECK-NEXT:    sllg %r1, %r1, 29
10; CHECK-NEXT:    rosbg %r1, %r0, 35, 63, 62
11; CHECK-NEXT:    nihh %r1, 4095
12; CHECK-NEXT:    stg %r1, 0(%r2)
13; CHECK-NEXT:    vlgvf %r1, %v24, 2
14; CHECK-NEXT:    risbgn %r0, %r0, 0, 129, 62
15; CHECK-NEXT:    rosbg %r0, %r1, 2, 32, 31
16; CHECK-NEXT:    vlgvf %r1, %v24, 3
17; CHECK-NEXT:    rosbg %r0, %r1, 33, 63, 0
18; CHECK-NEXT:    stg %r0, 8(%r2)
19; CHECK-NEXT:    br %r14
20{
21  store <4 x i31> %src, <4 x i31>* %p
22  ret void
23}
24
25; Store a <16 x i1> vector.
26define i16 @fun1(<16 x i1> %src)
27; CHECK-LABEL: fun1:
28; CHECK:       # %bb.0:
29; CHECK-NEXT:    aghi %r15, -168
30; CHECK-NEXT:    .cfi_def_cfa_offset 328
31; CHECK-NEXT:    vlgvb %r0, %v24, 0
32; CHECK-NEXT:    vlgvb %r1, %v24, 1
33; CHECK-NEXT:    risblg %r0, %r0, 16, 144, 15
34; CHECK-NEXT:    rosbg %r0, %r1, 49, 49, 14
35; CHECK-NEXT:    vlgvb %r1, %v24, 2
36; CHECK-NEXT:    rosbg %r0, %r1, 50, 50, 13
37; CHECK-NEXT:    vlgvb %r1, %v24, 3
38; CHECK-NEXT:    rosbg %r0, %r1, 51, 51, 12
39; CHECK-NEXT:    vlgvb %r1, %v24, 4
40; CHECK-NEXT:    rosbg %r0, %r1, 52, 52, 11
41; CHECK-NEXT:    vlgvb %r1, %v24, 5
42; CHECK-NEXT:    rosbg %r0, %r1, 53, 53, 10
43; CHECK-NEXT:    vlgvb %r1, %v24, 6
44; CHECK-NEXT:    rosbg %r0, %r1, 54, 54, 9
45; CHECK-NEXT:    vlgvb %r1, %v24, 7
46; CHECK-NEXT:    rosbg %r0, %r1, 55, 55, 8
47; CHECK-NEXT:    vlgvb %r1, %v24, 8
48; CHECK-NEXT:    rosbg %r0, %r1, 56, 56, 7
49; CHECK-NEXT:    vlgvb %r1, %v24, 9
50; CHECK-NEXT:    rosbg %r0, %r1, 57, 57, 6
51; CHECK-NEXT:    vlgvb %r1, %v24, 10
52; CHECK-NEXT:    rosbg %r0, %r1, 58, 58, 5
53; CHECK-NEXT:    vlgvb %r1, %v24, 11
54; CHECK-NEXT:    rosbg %r0, %r1, 59, 59, 4
55; CHECK-NEXT:    vlgvb %r1, %v24, 12
56; CHECK-NEXT:    rosbg %r0, %r1, 60, 60, 3
57; CHECK-NEXT:    vlgvb %r1, %v24, 13
58; CHECK-NEXT:    rosbg %r0, %r1, 61, 61, 2
59; CHECK-NEXT:    vlgvb %r1, %v24, 14
60; CHECK-NEXT:    rosbg %r0, %r1, 62, 62, 1
61; CHECK-NEXT:    vlgvb %r1, %v24, 15
62; CHECK-NEXT:    rosbg %r0, %r1, 63, 63, 0
63; CHECK-NEXT:    sth %r0, 160(%r15)
64; CHECK-NEXT:    lh %r2, 160(%r15)
65; CHECK-NEXT:    aghi %r15, 168
66; CHECK-NEXT:    br %r14
67{
68  %res = bitcast <16 x i1> %src to i16
69  ret i16 %res
70}
71
72; Truncate a <8 x i32> vector to <8 x i31> and store it (test splitting).
73define void @fun2(<8 x i32> %src, <8 x i31>* %p)
74; CHECK-LABEL: fun2:
75; CHECK:       # %bb.0:
76; CHECK-NEXT:    stmg %r14, %r15, 112(%r15)
77; CHECK-NEXT:    .cfi_offset %r14, -48
78; CHECK-NEXT:    .cfi_offset %r15, -40
79; CHECK-NEXT:    vlgvf %r3, %v26, 1
80; CHECK-NEXT:    vlgvf %r1, %v26, 2
81; CHECK-NEXT:    risbgn %r4, %r3, 0, 129, 62
82; CHECK-NEXT:    rosbg %r4, %r1, 2, 32, 31
83; CHECK-DAG:     vlgvf %r0, %v26, 3
84; CHECK-DAG:     rosbg %r4, %r0, 33, 63, 0
85; CHECK-DAG:     stc %r0, 30(%r2)
86; CHECK-DAG:     srl %r0, 8
87; CHECK-DAG:     vlgvf [[REG0:%r[0-9]+]], %v24, 1
88; CHECK-DAG:     vlgvf [[REG1:%r[0-9]+]], %v24, 0
89; CHECK-DAG:     sth %r0, 28(%r2)
90; CHECK-DAG:     vlgvf [[REG2:%r[0-9]+]], %v24, 2
91; CHECK-DAG:     risbgn [[REG3:%r[0-9]+]], [[REG0]], 0, 133, 58
92; CHECK-DAG:     rosbg [[REG3]], [[REG2]], 6, 36, 27
93; CHECK-DAG:     sllg [[REG4:%r[0-9]+]], [[REG1]], 25
94; CHECK-DAG:     rosbg [[REG4]], [[REG0]], 39, 63, 58
95; CHECK-DAG:     vlgvf [[REG5:%r[0-9]+]], %v24, 3
96; CHECK-DAG:     rosbg [[REG3]], [[REG5]], 37, 63, 60
97; CHECK-DAG:     sllg [[REG6:%r[0-9]+]], [[REG4]], 8
98; CHECK-DAG:     rosbg [[REG6]], [[REG3]], 56, 63, 8
99; CHECK-NEXT:    stg [[REG6]], 0(%r2)
100; CHECK-NEXT:    srlg [[REG7:%r[0-9]+]], %r4, 24
101; CHECK-NEXT:    st [[REG7]], 24(%r2)
102; CHECK-NEXT:    vlgvf [[REG8:%r[0-9]+]], %v26, 0
103; CHECK-NEXT:    risbgn [[REG10:%r[0-9]+]], [[REG5]], 0, 131, 60
104; CHECK-NEXT:    rosbg [[REG10]], [[REG8]], 4, 34, 29
105; CHECK-NEXT:    sllg [[REG9:%r[0-9]+]], [[REG3]], 8
106; CHECK-NEXT:    rosbg [[REG10]], %r3, 35, 63, 62
107; CHECK-NEXT:    rosbg [[REG9]], [[REG10]], 56, 63, 8
108; CHECK-NEXT:    stg [[REG9]], 8(%r2)
109; CHECK-NEXT:    sllg %r0, [[REG10]], 8
110; CHECK-NEXT:    rosbg %r0, %r4, 56, 63, 8
111; CHECK-NEXT:    stg %r0, 16(%r2)
112; CHECK-NEXT:    lmg %r14, %r15, 112(%r15)
113; CHECK-NEXT:    br %r14
114{
115  %tmp = trunc <8 x i32> %src to <8 x i31>
116  store <8 x i31> %tmp, <8 x i31>* %p
117  ret void
118}
119
120; Load and store a <3 x i31> vector (test widening).
121define void @fun3(<3 x i31>* %src, <3 x i31>* %p)
122; CHECK-LABEL: fun3:
123; CHECK:       # %bb.0:
124; CHECK-NEXT:    llgf %r1, 0(%r2)
125; CHECK-NEXT:    llgf %r0, 3(%r2)
126; CHECK-NEXT:    sllg %r4, %r1, 62
127; CHECK-NEXT:    rosbg %r4, %r0, 0, 32, 31
128; CHECK-NEXT:    llgf %r0, 6(%r2)
129; CHECK-NEXT:    ogr %r0, %r4
130; CHECK-NEXT:    st %r0, 8(%r3)
131; CHECK-NEXT:    srlg %r0, %r4, 32
132; CHECK-NEXT:    sllg %r1, %r1, 30
133; CHECK-NEXT:    lr %r1, %r0
134; CHECK-NEXT:    nihh %r1, 8191
135; CHECK-NEXT:    stg %r1, 0(%r3)
136; CHECK-NEXT:    br %r14
137{
138  %tmp = load <3 x i31>, <3 x i31>* %src
139  store <3 x i31> %tmp, <3 x i31>* %p
140  ret void
141}
142