1; Test compound shifts.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
4
5; Test a shift right followed by a sign extension.  This can use two shifts.
6define i64 @f1(i32 %a) {
7; CHECK-LABEL: f1:
8; CHECK: sllg [[REG:%r[0-5]]], %r2, 62
9; CHECK: srag %r2, [[REG]], 63
10; CHECK: br %r14
11  %shr = lshr i32 %a, 1
12  %trunc = trunc i32 %shr to i1
13  %ext = sext i1 %trunc to i64
14  ret i64 %ext
15}
16
17; ...and again with the highest shift count.
18define i64 @f2(i32 %a) {
19; CHECK-LABEL: f2:
20; CHECK: sllg [[REG:%r[0-5]]], %r2, 32
21; CHECK: srag %r2, [[REG]], 63
22; CHECK: br %r14
23  %shr = lshr i32 %a, 31
24  %trunc = trunc i32 %shr to i1
25  %ext = sext i1 %trunc to i64
26  ret i64 %ext
27}
28
29; Test a left shift that of an extended right shift in a case where folding
30; is possible.
31define i64 @f3(i32 %a) {
32; CHECK-LABEL: f3:
33; CHECK: risbg %r2, %r2, 27, 181, 9
34; CHECK: br %r14
35  %shr = lshr i32 %a, 1
36  %ext = zext i32 %shr to i64
37  %shl = shl i64 %ext, 10
38  %and = and i64 %shl, 137438952960
39  ret i64 %and
40}
41
42; ...and again with a larger right shift.
43define i64 @f4(i32 %a) {
44; CHECK-LABEL: f4:
45; CHECK: risbg %r2, %r2, 30, 158, 3
46; CHECK: br %r14
47  %shr = lshr i32 %a, 30
48  %ext = sext i32 %shr to i64
49  %shl = shl i64 %ext, 33
50  %and = and i64 %shl, 8589934592
51  ret i64 %and
52}
53
54; Repeat the previous test in a case where all bits outside the
55; bottom 3 matter.
56define i64 @f5(i32 %a) {
57; CHECK-LABEL: f5:
58; CHECK: risbg %r2, %r2, 29, 158, 3
59; CHECK: lhi %r2, 7
60; CHECK: br %r14
61  %shr = lshr i32 %a, 30
62  %ext = sext i32 %shr to i64
63  %shl = shl i64 %ext, 33
64  %or = or i64 %shl, 7
65  ret i64 %or
66}
67
68; Test that SRA gets replaced with SRL if the sign bit is the only one
69; that matters.
70define i64 @f6(i64 %a) {
71; CHECK-LABEL: f6:
72; CHECK: risbg %r2, %r2, 55, 183, 19
73; CHECK: br %r14
74  %shl = shl i64 %a, 10
75  %shr = ashr i64 %shl, 60
76  %and = and i64 %shr, 256
77  ret i64 %and
78}
79