1; Test 32-bit comparisons in which the second operand is zero-extended
2; from a PC-relative i16.
3;
4; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
5
6@g = global i16 1
7@h = global i16 1, align 1, section "foo"
8
9; Check unsigned comparison.
10define i32 @f1(i32 %src1) {
11; CHECK: f1:
12; CHECK: clhrl %r2, g
13; CHECK-NEXT: jl
14; CHECK: br %r14
15entry:
16  %val = load i16 *@g
17  %src2 = zext i16 %val to i32
18  %cond = icmp ult i32 %src1, %src2
19  br i1 %cond, label %exit, label %mulb
20mulb:
21  %mul = mul i32 %src1, %src1
22  br label %exit
23exit:
24  %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
25  ret i32 %res
26}
27
28; Check signed comparison.
29define i32 @f2(i32 %src1) {
30; CHECK: f2:
31; CHECK-NOT: clhrl
32; CHECK: br %r14
33entry:
34  %val = load i16 *@g
35  %src2 = zext i16 %val to i32
36  %cond = icmp slt i32 %src1, %src2
37  br i1 %cond, label %exit, label %mulb
38mulb:
39  %mul = mul i32 %src1, %src1
40  br label %exit
41exit:
42  %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
43  ret i32 %res
44}
45
46; Check equality.
47define i32 @f3(i32 %src1) {
48; CHECK: f3:
49; CHECK: clhrl %r2, g
50; CHECK-NEXT: je
51; CHECK: br %r14
52entry:
53  %val = load i16 *@g
54  %src2 = zext i16 %val to i32
55  %cond = icmp eq i32 %src1, %src2
56  br i1 %cond, label %exit, label %mulb
57mulb:
58  %mul = mul i32 %src1, %src1
59  br label %exit
60exit:
61  %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
62  ret i32 %res
63}
64
65; Check inequality.
66define i32 @f4(i32 %src1) {
67; CHECK: f4:
68; CHECK: clhrl %r2, g
69; CHECK-NEXT: jlh
70; CHECK: br %r14
71entry:
72  %val = load i16 *@g
73  %src2 = zext i16 %val to i32
74  %cond = icmp ne i32 %src1, %src2
75  br i1 %cond, label %exit, label %mulb
76mulb:
77  %mul = mul i32 %src1, %src1
78  br label %exit
79exit:
80  %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
81  ret i32 %res
82}
83
84; Repeat f1 with an unaligned address.
85define i32 @f5(i32 %src1) {
86; CHECK: f5:
87; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
88; CHECK: llh [[VAL:%r[0-5]]], 0([[REG]])
89; CHECK: clr %r2, [[VAL]]
90; CHECK-NEXT: jl
91; CHECK: br %r14
92entry:
93  %val = load i16 *@h, align 1
94  %src2 = zext i16 %val to i32
95  %cond = icmp ult i32 %src1, %src2
96  br i1 %cond, label %exit, label %mulb
97mulb:
98  %mul = mul i32 %src1, %src1
99  br label %exit
100exit:
101  %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
102  ret i32 %res
103}
104