1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; Test 32-bit comparisons in which the second operand is zero-extended
3; from a PC-relative i16.
4;
5; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
6
7@g = global i16 1
8@h = global i16 1, align 1, section "foo"
9
10; Check unsigned comparison.
11define i32 @f1(i32 %src1) {
12; CHECK-LABEL: f1:
13; CHECK:       # %bb.0: # %entry
14; CHECK-NEXT:    clhrl %r2, g
15; CHECK-NEXT:    jhe .LBB0_2
16; CHECK-NEXT:  # %bb.1: # %exit
17; CHECK-NEXT:    ahi %r2, 1
18; CHECK-NEXT:    br %r14
19; CHECK-NEXT:  .LBB0_2: # %mulb
20; CHECK-NEXT:    msr %r2, %r2
21; CHECK-NEXT:    ahi %r2, 1
22; CHECK-NEXT:    br %r14
23entry:
24  %val = load i16, i16 *@g
25  %src2 = zext i16 %val to i32
26  %cond = icmp ult i32 %src1, %src2
27  br i1 %cond, label %exit, label %mulb
28mulb:
29  %mul = mul i32 %src1, %src1
30  br label %exit
31exit:
32  %tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
33  %res = add i32 %tmp, 1
34  ret i32 %res
35}
36
37; Check signed comparison.
38define i32 @f2(i32 %src1) {
39; CHECK-LABEL: f2:
40; CHECK:       # %bb.0: # %entry
41; CHECK-NEXT:    llhrl %r0, g
42; CHECK-NEXT:    crjhe %r2, %r0, .LBB1_2
43; CHECK-NEXT:  # %bb.1: # %exit
44; CHECK-NEXT:    ahi %r2, 1
45; CHECK-NEXT:    br %r14
46; CHECK-NEXT:  .LBB1_2: # %mulb
47; CHECK-NEXT:    msr %r2, %r2
48; CHECK-NEXT:    ahi %r2, 1
49; CHECK-NEXT:    br %r14
50entry:
51  %val = load i16, i16 *@g
52  %src2 = zext i16 %val to i32
53  %cond = icmp slt i32 %src1, %src2
54  br i1 %cond, label %exit, label %mulb
55mulb:
56  %mul = mul i32 %src1, %src1
57  br label %exit
58exit:
59  %tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
60  %res = add i32 %tmp, 1
61  ret i32 %res
62}
63
64; Check equality.
65define i32 @f3(i32 %src1) {
66; CHECK-LABEL: f3:
67; CHECK:       # %bb.0: # %entry
68; CHECK-NEXT:    clhrl %r2, g
69; CHECK-NEXT:    je .LBB2_2
70; CHECK-NEXT:  # %bb.1: # %mulb
71; CHECK-NEXT:    msr %r2, %r2
72; CHECK-NEXT:  .LBB2_2: # %exit
73; CHECK-NEXT:    ahi %r2, 1
74; CHECK-NEXT:    br %r14
75entry:
76  %val = load i16, i16 *@g
77  %src2 = zext i16 %val to i32
78  %cond = icmp eq i32 %src1, %src2
79  br i1 %cond, label %exit, label %mulb
80mulb:
81  %mul = mul i32 %src1, %src1
82  br label %exit
83exit:
84  %tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
85  %res = add i32 %tmp, 1
86  ret i32 %res
87}
88
89; Check inequality.
90define i32 @f4(i32 %src1) {
91; CHECK-LABEL: f4:
92; CHECK:       # %bb.0: # %entry
93; CHECK-NEXT:    clhrl %r2, g
94; CHECK-NEXT:    je .LBB3_2
95; CHECK-NEXT:  # %bb.1: # %exit
96; CHECK-NEXT:    ahi %r2, 1
97; CHECK-NEXT:    br %r14
98; CHECK-NEXT:  .LBB3_2: # %mulb
99; CHECK-NEXT:    msr %r2, %r2
100; CHECK-NEXT:    ahi %r2, 1
101; CHECK-NEXT:    br %r14
102entry:
103  %val = load i16, i16 *@g
104  %src2 = zext i16 %val to i32
105  %cond = icmp ne i32 %src1, %src2
106  br i1 %cond, label %exit, label %mulb
107mulb:
108  %mul = mul i32 %src1, %src1
109  br label %exit
110exit:
111  %tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
112  %res = add i32 %tmp, 1
113  ret i32 %res
114}
115
116; Repeat f1 with an unaligned address.
117define i32 @f5(i32 %src1) {
118; CHECK-LABEL: f5:
119; CHECK:       # %bb.0: # %entry
120; CHECK-NEXT:    lgrl %r1, h@GOT
121; CHECK-NEXT:    llh %r0, 0(%r1)
122; CHECK-NEXT:    clrjhe %r2, %r0, .LBB4_2
123; CHECK-NEXT:  # %bb.1: # %exit
124; CHECK-NEXT:    ahi %r2, 1
125; CHECK-NEXT:    br %r14
126; CHECK-NEXT:  .LBB4_2: # %mulb
127; CHECK-NEXT:    msr %r2, %r2
128; CHECK-NEXT:    ahi %r2, 1
129; CHECK-NEXT:    br %r14
130entry:
131  %val = load i16, i16 *@h, align 1
132  %src2 = zext i16 %val to i32
133  %cond = icmp ult i32 %src1, %src2
134  br i1 %cond, label %exit, label %mulb
135mulb:
136  %mul = mul i32 %src1, %src1
137  br label %exit
138exit:
139  %tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
140  %res = add i32 %tmp, 1
141  ret i32 %res
142}
143
144; Check the comparison can be reversed if that allows CLHRL to be used.
145define i32 @f6(i32 %src2) {
146; CHECK-LABEL: f6:
147; CHECK:       # %bb.0: # %entry
148; CHECK-NEXT:    clhrl %r2, g
149; CHECK-NEXT:    jle .LBB5_2
150; CHECK-NEXT:  # %bb.1: # %exit
151; CHECK-NEXT:    ahi %r2, 1
152; CHECK-NEXT:    br %r14
153; CHECK-NEXT:  .LBB5_2: # %mulb
154; CHECK-NEXT:    msr %r2, %r2
155; CHECK-NEXT:    ahi %r2, 1
156; CHECK-NEXT:    br %r14
157entry:
158  %val = load i16, i16 *@g
159  %src1 = zext i16 %val to i32
160  %cond = icmp ult i32 %src1, %src2
161  br i1 %cond, label %exit, label %mulb
162mulb:
163  %mul = mul i32 %src2, %src2
164  br label %exit
165exit:
166  %tmp = phi i32 [ %src2, %entry ], [ %mul, %mulb ]
167  %res = add i32 %tmp, 1
168  ret i32 %res
169}
170