1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=s390x-linux-gnu -no-integrated-as < %s | FileCheck %s
3;
4; Test i128 (tied) operands.
5
6define i32 @fun0(i8* %p1, i32 signext %l1, i8* %p2, i32 signext %l2, i8 zeroext %pad) {
7; CHECK-LABEL: fun0:
8; CHECK:       # %bb.0: # %entry
9; CHECK-NEXT:    lgr %r0, %r5
10; CHECK-NEXT:    # kill: def $r4d killed $r4d def $r4q
11; CHECK-NEXT:    lgr %r1, %r3
12; CHECK-NEXT:    # kill: def $r2d killed $r2d def $r2q
13; CHECK-NEXT:    sllg %r5, %r6, 24
14; CHECK-NEXT:    rosbg %r5, %r0, 40, 63, 0
15; CHECK-NEXT:    risbg %r3, %r1, 40, 191, 0
16; CHECK-NEXT:    #APP
17; CHECK-NEXT:    clcl %r2, %r4
18; CHECK-NEXT:    #NO_APP
19; CHECK-NEXT:    ogr %r3, %r5
20; CHECK-NEXT:    risbg %r0, %r3, 40, 191, 0
21; CHECK-NEXT:    ipm %r2
22; CHECK-NEXT:    afi %r2, -268435456
23; CHECK-NEXT:    srl %r2, 31
24; CHECK-NEXT:    br %r14
25entry:
26  %0 = ptrtoint i8* %p1 to i64
27  %1 = ptrtoint i8* %p2 to i64
28  %and5 = and i32 %l2, 16777215
29  %2 = zext i32 %and5 to i64
30  %conv7 = zext i8 %pad to i64
31  %shl = shl nuw nsw i64 %conv7, 24
32  %or = or i64 %shl, %2
33  %u1.sroa.0.0.insert.ext = zext i64 %0 to i128
34  %u1.sroa.0.0.insert.shift = shl nuw i128 %u1.sroa.0.0.insert.ext, 64
35  %3 = and i32 %l1, 16777215
36  %u1.sroa.0.0.insert.mask = zext i32 %3 to i128
37  %u1.sroa.0.0.insert.insert = or i128 %u1.sroa.0.0.insert.shift, %u1.sroa.0.0.insert.mask
38  %u2.sroa.5.0.insert.ext = zext i64 %or to i128
39  %u2.sroa.0.0.insert.ext = zext i64 %1 to i128
40  %u2.sroa.0.0.insert.shift = shl nuw i128 %u2.sroa.0.0.insert.ext, 64
41  %u2.sroa.0.0.insert.insert = or i128 %u2.sroa.0.0.insert.shift, %u2.sroa.5.0.insert.ext
42  %4 = tail call { i128, i128 } asm "clcl $0, $1", "=r,=r,0,1"(i128 %u1.sroa.0.0.insert.insert, i128 %u2.sroa.0.0.insert.insert)
43  %asmresult = extractvalue { i128, i128 } %4, 0
44  %asmresult11 = extractvalue { i128, i128 } %4, 1
45  %5 = or i128 %asmresult, %asmresult11
46  %6 = and i128 %5, 16777215
47  %7 = icmp eq i128 %6, 0
48  %land.ext = zext i1 %7 to i32
49  ret i32 %land.ext
50}
51
52; Test a phys-reg def.
53define void @fun1(i128* %Src, i128* %Dst) {
54; CHECK-LABEL: fun1:
55; CHECK:       # %bb.0: # %entry
56; CHECK-NEXT:    #APP
57; CHECK-NEXT:    BLA %r4
58; CHECK-NEXT:    #NO_APP
59; CHECK-NEXT:    stg %r5, 8(%r3)
60; CHECK-NEXT:    stg %r4, 0(%r3)
61; CHECK-NEXT:    br %r14
62entry:
63   %IAsm = call i128 asm "BLA $0", "={r4}"()
64  store volatile i128 %IAsm, i128* %Dst
65  ret void
66}
67
68; Test a phys-reg use.
69define void @fun2(i128* %Src, i128* %Dst) {
70; CHECK-LABEL: fun2:
71; CHECK:       # %bb.0: # %entry
72; CHECK-NEXT:    lg %r5, 8(%r2)
73; CHECK-NEXT:    lg %r4, 0(%r2)
74; CHECK-NEXT:    #APP
75; CHECK-NEXT:    BLA %r4
76; CHECK-NEXT:    #NO_APP
77; CHECK-NEXT:    br %r14
78entry:
79  %L = load i128, i128* %Src
80  call void asm "BLA $0", "{r4}"(i128 %L)
81  ret void
82}
83
84; Test phys-reg use and phys-reg def.
85define void @fun3(i128* %Src, i128* %Dst) {
86; CHECK-LABEL: fun3:
87; CHECK:       # %bb.0: # %entry
88; CHECK-NEXT:    lg %r1, 8(%r2)
89; CHECK-NEXT:    lg %r0, 0(%r2)
90; CHECK-NEXT:    #APP
91; CHECK-NEXT:    BLA %r4, %r0
92; CHECK-NEXT:    #NO_APP
93; CHECK-NEXT:    stg %r5, 8(%r3)
94; CHECK-NEXT:    stg %r4, 0(%r3)
95; CHECK-NEXT:    br %r14
96entry:
97  %L = load i128, i128* %Src
98  %IAsm = call i128 asm "BLA $0, $1", "={r4},{r0}"(i128 %L)
99  store volatile i128 %IAsm, i128* %Dst
100  ret void
101}
102
103; Test a tied phys-reg.
104define void @fun4(i128* %Src, i128* %Dst) {
105; CHECK-LABEL: fun4:
106; CHECK:       # %bb.0: # %entry
107; CHECK-NEXT:    lg %r5, 8(%r2)
108; CHECK-NEXT:    lg %r4, 0(%r2)
109; CHECK-NEXT:    #APP
110; CHECK-NEXT:    BLA %r4, %r4
111; CHECK-NEXT:    #NO_APP
112; CHECK-NEXT:    stg %r5, 8(%r3)
113; CHECK-NEXT:    stg %r4, 0(%r3)
114; CHECK-NEXT:    br %r14
115entry:
116  %L = load i128, i128* %Src
117  %IAsm = call i128 asm "BLA $0, $1", "={r4},0"(i128 %L)
118  store volatile i128 %IAsm, i128* %Dst
119  ret void
120}
121