1# Check that the backend can handle consecutive select instructions also in
2# the presence of DEBUG_VALUE machine instructions.
3#
4# RUN: llc %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z13 \
5# RUN:   -start-before=finalize-isel -o - 2>&1 | FileCheck %s
6#
7# CHECK-LABEL: %bb.1:
8# CHECK:       ldr
9# CHECK-NEXT:  ldr
10# CHECK-NEXT:  ldr
11
12--- |
13  ; ModuleID = 'tc.ll'
14  source_filename = "tc.ll"
15  target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
16
17  define float @fun(i1 %cmp, float %arg0, float %arg1, float %arg2, float %arg3, float %arg4) #0 {
18    %fs0 = select i1 %cmp, float %arg0, float %arg1
19    ; Keep the dbg metadata live by referencing it in the IR.
20    call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !7, metadata !DIExpression()), !dbg !9
21    %fs1 = select i1 %cmp, float %arg2, float %arg3
22    call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !7, metadata !DIExpression()), !dbg !9
23    %fs2 = select i1 %cmp, float %arg0, float %arg3
24    %s0 = fadd float %fs0, %fs1
25    %s1 = fadd float %s0, %fs2
26    ret float %s1
27  }
28
29  declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
30
31  attributes #0 = { "target-cpu"="z13" }
32
33  !llvm.dbg.cu = !{!0}
34  !llvm.module.flags = !{!3, !4}
35
36  !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "llvm", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
37  !1 = !DIFile(filename: "test.ll", directory: "/tmp")
38  !2 = !{}
39  !3 = !{i32 2, !"Dwarf Version", i32 4}
40  !4 = !{i32 2, !"Debug Info Version", i32 3}
41  !5 = distinct !DISubprogram(name: "test_dbg_value", scope: !1, file: !1, line: 1, type: !6, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, retainedNodes: !2)
42  !6 = !DISubroutineType(types: !2)
43  !7 = !DILocalVariable(name: "in", arg: 1, scope: !5, file: !1, line: 1, type: !8)
44  !8 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
45  !9 = !DILocation(line: 1, column: 1, scope: !5)
46
47...
48---
49name:            fun
50alignment:       4
51tracksRegLiveness: true
52registers:
53  - { id: 0, class: gr32bit }
54  - { id: 1, class: fp32bit }
55  - { id: 2, class: fp32bit }
56  - { id: 3, class: fp32bit }
57  - { id: 4, class: fp32bit }
58  - { id: 5, class: fp32bit }
59  - { id: 6, class: fp32bit }
60  - { id: 7, class: fp32bit }
61  - { id: 8, class: fp32bit }
62  - { id: 9, class: fp32bit }
63liveins:
64  - { reg: '$r2l', virtual-reg: '%0' }
65  - { reg: '$f0s', virtual-reg: '%1' }
66  - { reg: '$f2s', virtual-reg: '%2' }
67  - { reg: '$f4s', virtual-reg: '%3' }
68  - { reg: '$f6s', virtual-reg: '%4' }
69frameInfo:
70  maxAlignment:    8
71fixedStack:
72  - { id: 0, size: 4, alignment: 8, stack-id: default, isImmutable: true }
73body:             |
74  bb.0 (%ir-block.0):
75    liveins: $r2l, $f0s, $f2s, $f4s, $f6s
76
77    %4:fp32bit = COPY $f6s
78    %3:fp32bit = COPY $f4s
79    %2:fp32bit = COPY $f2s
80    %1:fp32bit = COPY $f0s
81    %0:gr32bit = COPY $r2l
82    TMLMux %0, 1, implicit-def $cc
83    %5:fp32bit = SelectVR32 %1, %2, 15, 7, implicit $cc
84    DBG_VALUE %5, $noreg, !7, !DIExpression(), debug-location !9
85    %6:fp32bit = SelectVR32 %3, %4, 15, 7, implicit $cc
86    DBG_VALUE %6, $noreg, !7, !DIExpression(), debug-location !9
87    %7:fp32bit = SelectVR32 %1, %4, 15, 7, implicit $cc
88    %8:fp32bit = AEBR %5, killed %6, implicit-def dead $cc, implicit $fpc
89    %9:fp32bit = AEBR %8, killed %7, implicit-def dead $cc, implicit $fpc
90    $f0s = COPY %9
91    Return implicit $f0s
92
93...
94