1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV32I
4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s -check-prefix=RV64I
6
7declare void @callee(i8*)
8
9define void @caller32() nounwind {
10; RV32I-LABEL: caller32:
11; RV32I:       # %bb.0:
12; RV32I-NEXT:    addi sp, sp, -64
13; RV32I-NEXT:    sw ra, 60(sp)
14; RV32I-NEXT:    sw s0, 56(sp)
15; RV32I-NEXT:    addi s0, sp, 64
16; RV32I-NEXT:    andi sp, sp, -32
17; RV32I-NEXT:    addi a0, sp, 32
18; RV32I-NEXT:    call callee
19; RV32I-NEXT:    addi sp, s0, -64
20; RV32I-NEXT:    lw s0, 56(sp)
21; RV32I-NEXT:    lw ra, 60(sp)
22; RV32I-NEXT:    addi sp, sp, 64
23; RV32I-NEXT:    ret
24;
25; RV64I-LABEL: caller32:
26; RV64I:       # %bb.0:
27; RV64I-NEXT:    addi sp, sp, -64
28; RV64I-NEXT:    sd ra, 56(sp)
29; RV64I-NEXT:    sd s0, 48(sp)
30; RV64I-NEXT:    addi s0, sp, 64
31; RV64I-NEXT:    andi sp, sp, -32
32; RV64I-NEXT:    addi a0, sp, 32
33; RV64I-NEXT:    call callee
34; RV64I-NEXT:    addi sp, s0, -64
35; RV64I-NEXT:    ld s0, 48(sp)
36; RV64I-NEXT:    ld ra, 56(sp)
37; RV64I-NEXT:    addi sp, sp, 64
38; RV64I-NEXT:    ret
39  %1 = alloca i8, align 32
40  call void @callee(i8* %1)
41  ret void
42}
43
44define void @caller_no_realign32() nounwind "no-realign-stack" {
45; RV32I-LABEL: caller_no_realign32:
46; RV32I:       # %bb.0:
47; RV32I-NEXT:    addi sp, sp, -16
48; RV32I-NEXT:    sw ra, 12(sp)
49; RV32I-NEXT:    mv a0, sp
50; RV32I-NEXT:    call callee
51; RV32I-NEXT:    lw ra, 12(sp)
52; RV32I-NEXT:    addi sp, sp, 16
53; RV32I-NEXT:    ret
54;
55; RV64I-LABEL: caller_no_realign32:
56; RV64I:       # %bb.0:
57; RV64I-NEXT:    addi sp, sp, -16
58; RV64I-NEXT:    sd ra, 8(sp)
59; RV64I-NEXT:    mv a0, sp
60; RV64I-NEXT:    call callee
61; RV64I-NEXT:    ld ra, 8(sp)
62; RV64I-NEXT:    addi sp, sp, 16
63; RV64I-NEXT:    ret
64  %1 = alloca i8, align 32
65  call void @callee(i8* %1)
66  ret void
67}
68
69define void @caller64() nounwind {
70; RV32I-LABEL: caller64:
71; RV32I:       # %bb.0:
72; RV32I-NEXT:    addi sp, sp, -128
73; RV32I-NEXT:    sw ra, 124(sp)
74; RV32I-NEXT:    sw s0, 120(sp)
75; RV32I-NEXT:    addi s0, sp, 128
76; RV32I-NEXT:    andi sp, sp, -64
77; RV32I-NEXT:    addi a0, sp, 64
78; RV32I-NEXT:    call callee
79; RV32I-NEXT:    addi sp, s0, -128
80; RV32I-NEXT:    lw s0, 120(sp)
81; RV32I-NEXT:    lw ra, 124(sp)
82; RV32I-NEXT:    addi sp, sp, 128
83; RV32I-NEXT:    ret
84;
85; RV64I-LABEL: caller64:
86; RV64I:       # %bb.0:
87; RV64I-NEXT:    addi sp, sp, -128
88; RV64I-NEXT:    sd ra, 120(sp)
89; RV64I-NEXT:    sd s0, 112(sp)
90; RV64I-NEXT:    addi s0, sp, 128
91; RV64I-NEXT:    andi sp, sp, -64
92; RV64I-NEXT:    addi a0, sp, 64
93; RV64I-NEXT:    call callee
94; RV64I-NEXT:    addi sp, s0, -128
95; RV64I-NEXT:    ld s0, 112(sp)
96; RV64I-NEXT:    ld ra, 120(sp)
97; RV64I-NEXT:    addi sp, sp, 128
98; RV64I-NEXT:    ret
99  %1 = alloca i8, align 64
100  call void @callee(i8* %1)
101  ret void
102}
103
104define void @caller_no_realign64() nounwind "no-realign-stack" {
105; RV32I-LABEL: caller_no_realign64:
106; RV32I:       # %bb.0:
107; RV32I-NEXT:    addi sp, sp, -16
108; RV32I-NEXT:    sw ra, 12(sp)
109; RV32I-NEXT:    mv a0, sp
110; RV32I-NEXT:    call callee
111; RV32I-NEXT:    lw ra, 12(sp)
112; RV32I-NEXT:    addi sp, sp, 16
113; RV32I-NEXT:    ret
114;
115; RV64I-LABEL: caller_no_realign64:
116; RV64I:       # %bb.0:
117; RV64I-NEXT:    addi sp, sp, -16
118; RV64I-NEXT:    sd ra, 8(sp)
119; RV64I-NEXT:    mv a0, sp
120; RV64I-NEXT:    call callee
121; RV64I-NEXT:    ld ra, 8(sp)
122; RV64I-NEXT:    addi sp, sp, 16
123; RV64I-NEXT:    ret
124  %1 = alloca i8, align 64
125  call void @callee(i8* %1)
126  ret void
127}
128
129define void @caller128() nounwind {
130; RV32I-LABEL: caller128:
131; RV32I:       # %bb.0:
132; RV32I-NEXT:    addi sp, sp, -256
133; RV32I-NEXT:    sw ra, 252(sp)
134; RV32I-NEXT:    sw s0, 248(sp)
135; RV32I-NEXT:    addi s0, sp, 256
136; RV32I-NEXT:    andi sp, sp, -128
137; RV32I-NEXT:    addi a0, sp, 128
138; RV32I-NEXT:    call callee
139; RV32I-NEXT:    addi sp, s0, -256
140; RV32I-NEXT:    lw s0, 248(sp)
141; RV32I-NEXT:    lw ra, 252(sp)
142; RV32I-NEXT:    addi sp, sp, 256
143; RV32I-NEXT:    ret
144;
145; RV64I-LABEL: caller128:
146; RV64I:       # %bb.0:
147; RV64I-NEXT:    addi sp, sp, -256
148; RV64I-NEXT:    sd ra, 248(sp)
149; RV64I-NEXT:    sd s0, 240(sp)
150; RV64I-NEXT:    addi s0, sp, 256
151; RV64I-NEXT:    andi sp, sp, -128
152; RV64I-NEXT:    addi a0, sp, 128
153; RV64I-NEXT:    call callee
154; RV64I-NEXT:    addi sp, s0, -256
155; RV64I-NEXT:    ld s0, 240(sp)
156; RV64I-NEXT:    ld ra, 248(sp)
157; RV64I-NEXT:    addi sp, sp, 256
158; RV64I-NEXT:    ret
159  %1 = alloca i8, align 128
160  call void @callee(i8* %1)
161  ret void
162}
163
164define void @caller_no_realign128() nounwind "no-realign-stack" {
165; RV32I-LABEL: caller_no_realign128:
166; RV32I:       # %bb.0:
167; RV32I-NEXT:    addi sp, sp, -16
168; RV32I-NEXT:    sw ra, 12(sp)
169; RV32I-NEXT:    mv a0, sp
170; RV32I-NEXT:    call callee
171; RV32I-NEXT:    lw ra, 12(sp)
172; RV32I-NEXT:    addi sp, sp, 16
173; RV32I-NEXT:    ret
174;
175; RV64I-LABEL: caller_no_realign128:
176; RV64I:       # %bb.0:
177; RV64I-NEXT:    addi sp, sp, -16
178; RV64I-NEXT:    sd ra, 8(sp)
179; RV64I-NEXT:    mv a0, sp
180; RV64I-NEXT:    call callee
181; RV64I-NEXT:    ld ra, 8(sp)
182; RV64I-NEXT:    addi sp, sp, 16
183; RV64I-NEXT:    ret
184  %1 = alloca i8, align 128
185  call void @callee(i8* %1)
186  ret void
187}
188
189define void @caller256() nounwind {
190; RV32I-LABEL: caller256:
191; RV32I:       # %bb.0:
192; RV32I-NEXT:    addi sp, sp, -512
193; RV32I-NEXT:    sw ra, 508(sp)
194; RV32I-NEXT:    sw s0, 504(sp)
195; RV32I-NEXT:    addi s0, sp, 512
196; RV32I-NEXT:    andi sp, sp, -256
197; RV32I-NEXT:    addi a0, sp, 256
198; RV32I-NEXT:    call callee
199; RV32I-NEXT:    addi sp, s0, -512
200; RV32I-NEXT:    lw s0, 504(sp)
201; RV32I-NEXT:    lw ra, 508(sp)
202; RV32I-NEXT:    addi sp, sp, 512
203; RV32I-NEXT:    ret
204;
205; RV64I-LABEL: caller256:
206; RV64I:       # %bb.0:
207; RV64I-NEXT:    addi sp, sp, -512
208; RV64I-NEXT:    sd ra, 504(sp)
209; RV64I-NEXT:    sd s0, 496(sp)
210; RV64I-NEXT:    addi s0, sp, 512
211; RV64I-NEXT:    andi sp, sp, -256
212; RV64I-NEXT:    addi a0, sp, 256
213; RV64I-NEXT:    call callee
214; RV64I-NEXT:    addi sp, s0, -512
215; RV64I-NEXT:    ld s0, 496(sp)
216; RV64I-NEXT:    ld ra, 504(sp)
217; RV64I-NEXT:    addi sp, sp, 512
218; RV64I-NEXT:    ret
219  %1 = alloca i8, align 256
220  call void @callee(i8* %1)
221  ret void
222}
223
224define void @caller_no_realign256() nounwind "no-realign-stack" {
225; RV32I-LABEL: caller_no_realign256:
226; RV32I:       # %bb.0:
227; RV32I-NEXT:    addi sp, sp, -16
228; RV32I-NEXT:    sw ra, 12(sp)
229; RV32I-NEXT:    mv a0, sp
230; RV32I-NEXT:    call callee
231; RV32I-NEXT:    lw ra, 12(sp)
232; RV32I-NEXT:    addi sp, sp, 16
233; RV32I-NEXT:    ret
234;
235; RV64I-LABEL: caller_no_realign256:
236; RV64I:       # %bb.0:
237; RV64I-NEXT:    addi sp, sp, -16
238; RV64I-NEXT:    sd ra, 8(sp)
239; RV64I-NEXT:    mv a0, sp
240; RV64I-NEXT:    call callee
241; RV64I-NEXT:    ld ra, 8(sp)
242; RV64I-NEXT:    addi sp, sp, 16
243; RV64I-NEXT:    ret
244  %1 = alloca i8, align 256
245  call void @callee(i8* %1)
246  ret void
247}
248
249define void @caller512() nounwind {
250; RV32I-LABEL: caller512:
251; RV32I:       # %bb.0:
252; RV32I-NEXT:    addi sp, sp, -1536
253; RV32I-NEXT:    sw ra, 1532(sp)
254; RV32I-NEXT:    sw s0, 1528(sp)
255; RV32I-NEXT:    addi s0, sp, 1536
256; RV32I-NEXT:    andi sp, sp, -512
257; RV32I-NEXT:    addi a0, sp, 1024
258; RV32I-NEXT:    call callee
259; RV32I-NEXT:    addi sp, s0, -1536
260; RV32I-NEXT:    lw s0, 1528(sp)
261; RV32I-NEXT:    lw ra, 1532(sp)
262; RV32I-NEXT:    addi sp, sp, 1536
263; RV32I-NEXT:    ret
264;
265; RV64I-LABEL: caller512:
266; RV64I:       # %bb.0:
267; RV64I-NEXT:    addi sp, sp, -1536
268; RV64I-NEXT:    sd ra, 1528(sp)
269; RV64I-NEXT:    sd s0, 1520(sp)
270; RV64I-NEXT:    addi s0, sp, 1536
271; RV64I-NEXT:    andi sp, sp, -512
272; RV64I-NEXT:    addi a0, sp, 1024
273; RV64I-NEXT:    call callee
274; RV64I-NEXT:    addi sp, s0, -1536
275; RV64I-NEXT:    ld s0, 1520(sp)
276; RV64I-NEXT:    ld ra, 1528(sp)
277; RV64I-NEXT:    addi sp, sp, 1536
278; RV64I-NEXT:    ret
279  %1 = alloca i8, align 512
280  call void @callee(i8* %1)
281  ret void
282}
283
284define void @caller_no_realign512() nounwind "no-realign-stack" {
285; RV32I-LABEL: caller_no_realign512:
286; RV32I:       # %bb.0:
287; RV32I-NEXT:    addi sp, sp, -16
288; RV32I-NEXT:    sw ra, 12(sp)
289; RV32I-NEXT:    mv a0, sp
290; RV32I-NEXT:    call callee
291; RV32I-NEXT:    lw ra, 12(sp)
292; RV32I-NEXT:    addi sp, sp, 16
293; RV32I-NEXT:    ret
294;
295; RV64I-LABEL: caller_no_realign512:
296; RV64I:       # %bb.0:
297; RV64I-NEXT:    addi sp, sp, -16
298; RV64I-NEXT:    sd ra, 8(sp)
299; RV64I-NEXT:    mv a0, sp
300; RV64I-NEXT:    call callee
301; RV64I-NEXT:    ld ra, 8(sp)
302; RV64I-NEXT:    addi sp, sp, 16
303; RV64I-NEXT:    ret
304  %1 = alloca i8, align 512
305  call void @callee(i8* %1)
306  ret void
307}
308
309define void @caller1024() nounwind {
310; RV32I-LABEL: caller1024:
311; RV32I:       # %bb.0:
312; RV32I-NEXT:    lui a0, 1
313; RV32I-NEXT:    addi a0, a0, -1024
314; RV32I-NEXT:    sub sp, sp, a0
315; RV32I-NEXT:    lui a0, 1
316; RV32I-NEXT:    addi a0, a0, -1028
317; RV32I-NEXT:    add a0, sp, a0
318; RV32I-NEXT:    sw ra, 0(a0)
319; RV32I-NEXT:    lui a0, 1
320; RV32I-NEXT:    addi a0, a0, -1032
321; RV32I-NEXT:    add a0, sp, a0
322; RV32I-NEXT:    sw s0, 0(a0)
323; RV32I-NEXT:    lui a0, 1
324; RV32I-NEXT:    addi a0, a0, -1024
325; RV32I-NEXT:    add s0, sp, a0
326; RV32I-NEXT:    andi sp, sp, -1024
327; RV32I-NEXT:    lui a0, 1
328; RV32I-NEXT:    addi a0, a0, -2048
329; RV32I-NEXT:    add a0, sp, a0
330; RV32I-NEXT:    mv a0, a0
331; RV32I-NEXT:    call callee
332; RV32I-NEXT:    lui a0, 1
333; RV32I-NEXT:    addi a0, a0, -1024
334; RV32I-NEXT:    sub sp, s0, a0
335; RV32I-NEXT:    lui a0, 1
336; RV32I-NEXT:    addi a0, a0, -1032
337; RV32I-NEXT:    add a0, sp, a0
338; RV32I-NEXT:    lw s0, 0(a0)
339; RV32I-NEXT:    lui a0, 1
340; RV32I-NEXT:    addi a0, a0, -1028
341; RV32I-NEXT:    add a0, sp, a0
342; RV32I-NEXT:    lw ra, 0(a0)
343; RV32I-NEXT:    lui a0, 1
344; RV32I-NEXT:    addi a0, a0, -1024
345; RV32I-NEXT:    add sp, sp, a0
346; RV32I-NEXT:    ret
347;
348; RV64I-LABEL: caller1024:
349; RV64I:       # %bb.0:
350; RV64I-NEXT:    lui a0, 1
351; RV64I-NEXT:    addiw a0, a0, -1024
352; RV64I-NEXT:    sub sp, sp, a0
353; RV64I-NEXT:    lui a0, 1
354; RV64I-NEXT:    addiw a0, a0, -1032
355; RV64I-NEXT:    add a0, sp, a0
356; RV64I-NEXT:    sd ra, 0(a0)
357; RV64I-NEXT:    lui a0, 1
358; RV64I-NEXT:    addiw a0, a0, -1040
359; RV64I-NEXT:    add a0, sp, a0
360; RV64I-NEXT:    sd s0, 0(a0)
361; RV64I-NEXT:    lui a0, 1
362; RV64I-NEXT:    addiw a0, a0, -1024
363; RV64I-NEXT:    add s0, sp, a0
364; RV64I-NEXT:    andi sp, sp, -1024
365; RV64I-NEXT:    lui a0, 1
366; RV64I-NEXT:    addiw a0, a0, -2048
367; RV64I-NEXT:    add a0, sp, a0
368; RV64I-NEXT:    mv a0, a0
369; RV64I-NEXT:    call callee
370; RV64I-NEXT:    lui a0, 1
371; RV64I-NEXT:    addiw a0, a0, -1024
372; RV64I-NEXT:    sub sp, s0, a0
373; RV64I-NEXT:    lui a0, 1
374; RV64I-NEXT:    addiw a0, a0, -1040
375; RV64I-NEXT:    add a0, sp, a0
376; RV64I-NEXT:    ld s0, 0(a0)
377; RV64I-NEXT:    lui a0, 1
378; RV64I-NEXT:    addiw a0, a0, -1032
379; RV64I-NEXT:    add a0, sp, a0
380; RV64I-NEXT:    ld ra, 0(a0)
381; RV64I-NEXT:    lui a0, 1
382; RV64I-NEXT:    addiw a0, a0, -1024
383; RV64I-NEXT:    add sp, sp, a0
384; RV64I-NEXT:    ret
385  %1 = alloca i8, align 1024
386  call void @callee(i8* %1)
387  ret void
388}
389
390define void @caller_no_realign1024() nounwind "no-realign-stack" {
391; RV32I-LABEL: caller_no_realign1024:
392; RV32I:       # %bb.0:
393; RV32I-NEXT:    addi sp, sp, -16
394; RV32I-NEXT:    sw ra, 12(sp)
395; RV32I-NEXT:    mv a0, sp
396; RV32I-NEXT:    call callee
397; RV32I-NEXT:    lw ra, 12(sp)
398; RV32I-NEXT:    addi sp, sp, 16
399; RV32I-NEXT:    ret
400;
401; RV64I-LABEL: caller_no_realign1024:
402; RV64I:       # %bb.0:
403; RV64I-NEXT:    addi sp, sp, -16
404; RV64I-NEXT:    sd ra, 8(sp)
405; RV64I-NEXT:    mv a0, sp
406; RV64I-NEXT:    call callee
407; RV64I-NEXT:    ld ra, 8(sp)
408; RV64I-NEXT:    addi sp, sp, 16
409; RV64I-NEXT:    ret
410  %1 = alloca i8, align 1024
411  call void @callee(i8* %1)
412  ret void
413}
414
415define void @caller2048() nounwind {
416; RV32I-LABEL: caller2048:
417; RV32I:       # %bb.0:
418; RV32I-NEXT:    lui a0, 2
419; RV32I-NEXT:    addi a0, a0, -2048
420; RV32I-NEXT:    sub sp, sp, a0
421; RV32I-NEXT:    lui a0, 1
422; RV32I-NEXT:    addi a0, a0, 2044
423; RV32I-NEXT:    add a0, sp, a0
424; RV32I-NEXT:    sw ra, 0(a0)
425; RV32I-NEXT:    lui a0, 1
426; RV32I-NEXT:    addi a0, a0, 2040
427; RV32I-NEXT:    add a0, sp, a0
428; RV32I-NEXT:    sw s0, 0(a0)
429; RV32I-NEXT:    lui a0, 2
430; RV32I-NEXT:    addi a0, a0, -2048
431; RV32I-NEXT:    add s0, sp, a0
432; RV32I-NEXT:    andi sp, sp, -2048
433; RV32I-NEXT:    lui a0, 1
434; RV32I-NEXT:    add a0, sp, a0
435; RV32I-NEXT:    mv a0, a0
436; RV32I-NEXT:    call callee
437; RV32I-NEXT:    lui a0, 2
438; RV32I-NEXT:    addi a0, a0, -2048
439; RV32I-NEXT:    sub sp, s0, a0
440; RV32I-NEXT:    lui a0, 1
441; RV32I-NEXT:    addi a0, a0, 2040
442; RV32I-NEXT:    add a0, sp, a0
443; RV32I-NEXT:    lw s0, 0(a0)
444; RV32I-NEXT:    lui a0, 1
445; RV32I-NEXT:    addi a0, a0, 2044
446; RV32I-NEXT:    add a0, sp, a0
447; RV32I-NEXT:    lw ra, 0(a0)
448; RV32I-NEXT:    lui a0, 2
449; RV32I-NEXT:    addi a0, a0, -2048
450; RV32I-NEXT:    add sp, sp, a0
451; RV32I-NEXT:    ret
452;
453; RV64I-LABEL: caller2048:
454; RV64I:       # %bb.0:
455; RV64I-NEXT:    lui a0, 2
456; RV64I-NEXT:    addiw a0, a0, -2048
457; RV64I-NEXT:    sub sp, sp, a0
458; RV64I-NEXT:    lui a0, 1
459; RV64I-NEXT:    addiw a0, a0, 2040
460; RV64I-NEXT:    add a0, sp, a0
461; RV64I-NEXT:    sd ra, 0(a0)
462; RV64I-NEXT:    lui a0, 1
463; RV64I-NEXT:    addiw a0, a0, 2032
464; RV64I-NEXT:    add a0, sp, a0
465; RV64I-NEXT:    sd s0, 0(a0)
466; RV64I-NEXT:    lui a0, 2
467; RV64I-NEXT:    addiw a0, a0, -2048
468; RV64I-NEXT:    add s0, sp, a0
469; RV64I-NEXT:    andi sp, sp, -2048
470; RV64I-NEXT:    lui a0, 1
471; RV64I-NEXT:    add a0, sp, a0
472; RV64I-NEXT:    mv a0, a0
473; RV64I-NEXT:    call callee
474; RV64I-NEXT:    lui a0, 2
475; RV64I-NEXT:    addiw a0, a0, -2048
476; RV64I-NEXT:    sub sp, s0, a0
477; RV64I-NEXT:    lui a0, 1
478; RV64I-NEXT:    addiw a0, a0, 2032
479; RV64I-NEXT:    add a0, sp, a0
480; RV64I-NEXT:    ld s0, 0(a0)
481; RV64I-NEXT:    lui a0, 1
482; RV64I-NEXT:    addiw a0, a0, 2040
483; RV64I-NEXT:    add a0, sp, a0
484; RV64I-NEXT:    ld ra, 0(a0)
485; RV64I-NEXT:    lui a0, 2
486; RV64I-NEXT:    addiw a0, a0, -2048
487; RV64I-NEXT:    add sp, sp, a0
488; RV64I-NEXT:    ret
489  %1 = alloca i8, align 2048
490  call void @callee(i8* %1)
491  ret void
492}
493
494define void @caller_no_realign2048() nounwind "no-realign-stack" {
495; RV32I-LABEL: caller_no_realign2048:
496; RV32I:       # %bb.0:
497; RV32I-NEXT:    addi sp, sp, -16
498; RV32I-NEXT:    sw ra, 12(sp)
499; RV32I-NEXT:    mv a0, sp
500; RV32I-NEXT:    call callee
501; RV32I-NEXT:    lw ra, 12(sp)
502; RV32I-NEXT:    addi sp, sp, 16
503; RV32I-NEXT:    ret
504;
505; RV64I-LABEL: caller_no_realign2048:
506; RV64I:       # %bb.0:
507; RV64I-NEXT:    addi sp, sp, -16
508; RV64I-NEXT:    sd ra, 8(sp)
509; RV64I-NEXT:    mv a0, sp
510; RV64I-NEXT:    call callee
511; RV64I-NEXT:    ld ra, 8(sp)
512; RV64I-NEXT:    addi sp, sp, 16
513; RV64I-NEXT:    ret
514  %1 = alloca i8, align 2048
515  call void @callee(i8* %1)
516  ret void
517}
518
519define void @caller4096() nounwind {
520; RV32I-LABEL: caller4096:
521; RV32I:       # %bb.0:
522; RV32I-NEXT:    lui a0, 3
523; RV32I-NEXT:    sub sp, sp, a0
524; RV32I-NEXT:    lui a0, 3
525; RV32I-NEXT:    addi a0, a0, -4
526; RV32I-NEXT:    add a0, sp, a0
527; RV32I-NEXT:    sw ra, 0(a0)
528; RV32I-NEXT:    lui a0, 3
529; RV32I-NEXT:    addi a0, a0, -8
530; RV32I-NEXT:    add a0, sp, a0
531; RV32I-NEXT:    sw s0, 0(a0)
532; RV32I-NEXT:    lui a0, 3
533; RV32I-NEXT:    add s0, sp, a0
534; RV32I-NEXT:    srli a0, sp, 12
535; RV32I-NEXT:    slli sp, a0, 12
536; RV32I-NEXT:    lui a0, 2
537; RV32I-NEXT:    add a0, sp, a0
538; RV32I-NEXT:    mv a0, a0
539; RV32I-NEXT:    call callee
540; RV32I-NEXT:    lui a0, 3
541; RV32I-NEXT:    sub sp, s0, a0
542; RV32I-NEXT:    lui a0, 3
543; RV32I-NEXT:    addi a0, a0, -8
544; RV32I-NEXT:    add a0, sp, a0
545; RV32I-NEXT:    lw s0, 0(a0)
546; RV32I-NEXT:    lui a0, 3
547; RV32I-NEXT:    addi a0, a0, -4
548; RV32I-NEXT:    add a0, sp, a0
549; RV32I-NEXT:    lw ra, 0(a0)
550; RV32I-NEXT:    lui a0, 3
551; RV32I-NEXT:    add sp, sp, a0
552; RV32I-NEXT:    ret
553;
554; RV64I-LABEL: caller4096:
555; RV64I:       # %bb.0:
556; RV64I-NEXT:    lui a0, 3
557; RV64I-NEXT:    sub sp, sp, a0
558; RV64I-NEXT:    lui a0, 3
559; RV64I-NEXT:    addiw a0, a0, -8
560; RV64I-NEXT:    add a0, sp, a0
561; RV64I-NEXT:    sd ra, 0(a0)
562; RV64I-NEXT:    lui a0, 3
563; RV64I-NEXT:    addiw a0, a0, -16
564; RV64I-NEXT:    add a0, sp, a0
565; RV64I-NEXT:    sd s0, 0(a0)
566; RV64I-NEXT:    lui a0, 3
567; RV64I-NEXT:    add s0, sp, a0
568; RV64I-NEXT:    srli a0, sp, 12
569; RV64I-NEXT:    slli sp, a0, 12
570; RV64I-NEXT:    lui a0, 2
571; RV64I-NEXT:    add a0, sp, a0
572; RV64I-NEXT:    mv a0, a0
573; RV64I-NEXT:    call callee
574; RV64I-NEXT:    lui a0, 3
575; RV64I-NEXT:    sub sp, s0, a0
576; RV64I-NEXT:    lui a0, 3
577; RV64I-NEXT:    addiw a0, a0, -16
578; RV64I-NEXT:    add a0, sp, a0
579; RV64I-NEXT:    ld s0, 0(a0)
580; RV64I-NEXT:    lui a0, 3
581; RV64I-NEXT:    addiw a0, a0, -8
582; RV64I-NEXT:    add a0, sp, a0
583; RV64I-NEXT:    ld ra, 0(a0)
584; RV64I-NEXT:    lui a0, 3
585; RV64I-NEXT:    add sp, sp, a0
586; RV64I-NEXT:    ret
587  %1 = alloca i8, align 4096
588  call void @callee(i8* %1)
589  ret void
590}
591
592define void @caller_no_realign4096() nounwind "no-realign-stack" {
593; RV32I-LABEL: caller_no_realign4096:
594; RV32I:       # %bb.0:
595; RV32I-NEXT:    addi sp, sp, -16
596; RV32I-NEXT:    sw ra, 12(sp)
597; RV32I-NEXT:    mv a0, sp
598; RV32I-NEXT:    call callee
599; RV32I-NEXT:    lw ra, 12(sp)
600; RV32I-NEXT:    addi sp, sp, 16
601; RV32I-NEXT:    ret
602;
603; RV64I-LABEL: caller_no_realign4096:
604; RV64I:       # %bb.0:
605; RV64I-NEXT:    addi sp, sp, -16
606; RV64I-NEXT:    sd ra, 8(sp)
607; RV64I-NEXT:    mv a0, sp
608; RV64I-NEXT:    call callee
609; RV64I-NEXT:    ld ra, 8(sp)
610; RV64I-NEXT:    addi sp, sp, 16
611; RV64I-NEXT:    ret
612  %1 = alloca i8, align 4096
613  call void @callee(i8* %1)
614  ret void
615}
616