1*cf6cf0cdSShiva Chen; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2*cf6cf0cdSShiva Chen; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3*cf6cf0cdSShiva Chen; RUN:   | FileCheck %s -check-prefix=RV32I
4*cf6cf0cdSShiva Chen; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
5*cf6cf0cdSShiva Chen; RUN:   | FileCheck %s -check-prefix=RV64I
6*cf6cf0cdSShiva Chen
7*cf6cf0cdSShiva Chendeclare void @callee(i8*, i32*)
8*cf6cf0cdSShiva Chen
9*cf6cf0cdSShiva Chendefine void @caller(i32 %n) {
10*cf6cf0cdSShiva Chen; RV32I-LABEL: caller:
11*cf6cf0cdSShiva Chen; RV32I:       # %bb.0:
12*cf6cf0cdSShiva Chen; RV32I-NEXT:    addi sp, sp, -128
13*cf6cf0cdSShiva Chen; RV32I-NEXT:    .cfi_def_cfa_offset 128
14*cf6cf0cdSShiva Chen; RV32I-NEXT:    sw ra, 124(sp)
15*cf6cf0cdSShiva Chen; RV32I-NEXT:    sw s0, 120(sp)
16*cf6cf0cdSShiva Chen; RV32I-NEXT:    sw s1, 116(sp)
17*cf6cf0cdSShiva Chen; RV32I-NEXT:    .cfi_offset ra, -4
18*cf6cf0cdSShiva Chen; RV32I-NEXT:    .cfi_offset s0, -8
19*cf6cf0cdSShiva Chen; RV32I-NEXT:    .cfi_offset s1, -12
20*cf6cf0cdSShiva Chen; RV32I-NEXT:    addi s0, sp, 128
21*cf6cf0cdSShiva Chen; RV32I-NEXT:    .cfi_def_cfa s0, 0
22*cf6cf0cdSShiva Chen; RV32I-NEXT:    andi sp, sp, -64
23*cf6cf0cdSShiva Chen; RV32I-NEXT:    mv s1, sp
24*cf6cf0cdSShiva Chen; RV32I-NEXT:    addi a0, a0, 15
25*cf6cf0cdSShiva Chen; RV32I-NEXT:    andi a0, a0, -16
26*cf6cf0cdSShiva Chen; RV32I-NEXT:    sub a0, sp, a0
27*cf6cf0cdSShiva Chen; RV32I-NEXT:    mv sp, a0
28*cf6cf0cdSShiva Chen; RV32I-NEXT:    addi a1, s1, 64
29*cf6cf0cdSShiva Chen; RV32I-NEXT:    call callee
30*cf6cf0cdSShiva Chen; RV32I-NEXT:    addi sp, s0, -128
31*cf6cf0cdSShiva Chen; RV32I-NEXT:    lw s1, 116(sp)
32*cf6cf0cdSShiva Chen; RV32I-NEXT:    lw s0, 120(sp)
33*cf6cf0cdSShiva Chen; RV32I-NEXT:    lw ra, 124(sp)
34*cf6cf0cdSShiva Chen; RV32I-NEXT:    addi sp, sp, 128
35*cf6cf0cdSShiva Chen; RV32I-NEXT:    ret
36*cf6cf0cdSShiva Chen;
37*cf6cf0cdSShiva Chen; RV64I-LABEL: caller:
38*cf6cf0cdSShiva Chen; RV64I:       # %bb.0:
39*cf6cf0cdSShiva Chen; RV64I-NEXT:    addi sp, sp, -128
40*cf6cf0cdSShiva Chen; RV64I-NEXT:    .cfi_def_cfa_offset 128
41*cf6cf0cdSShiva Chen; RV64I-NEXT:    sd ra, 120(sp)
42*cf6cf0cdSShiva Chen; RV64I-NEXT:    sd s0, 112(sp)
43*cf6cf0cdSShiva Chen; RV64I-NEXT:    sd s1, 104(sp)
44*cf6cf0cdSShiva Chen; RV64I-NEXT:    .cfi_offset ra, -8
45*cf6cf0cdSShiva Chen; RV64I-NEXT:    .cfi_offset s0, -16
46*cf6cf0cdSShiva Chen; RV64I-NEXT:    .cfi_offset s1, -24
47*cf6cf0cdSShiva Chen; RV64I-NEXT:    addi s0, sp, 128
48*cf6cf0cdSShiva Chen; RV64I-NEXT:    .cfi_def_cfa s0, 0
49*cf6cf0cdSShiva Chen; RV64I-NEXT:    andi sp, sp, -64
50*cf6cf0cdSShiva Chen; RV64I-NEXT:    mv s1, sp
51*cf6cf0cdSShiva Chen; RV64I-NEXT:    slli a0, a0, 32
52*cf6cf0cdSShiva Chen; RV64I-NEXT:    srli a0, a0, 32
53*cf6cf0cdSShiva Chen; RV64I-NEXT:    addi a0, a0, 15
54*cf6cf0cdSShiva Chen; RV64I-NEXT:    addi a1, zero, 1
55*cf6cf0cdSShiva Chen; RV64I-NEXT:    slli a1, a1, 33
56*cf6cf0cdSShiva Chen; RV64I-NEXT:    addi a1, a1, -16
57*cf6cf0cdSShiva Chen; RV64I-NEXT:    and a0, a0, a1
58*cf6cf0cdSShiva Chen; RV64I-NEXT:    sub a0, sp, a0
59*cf6cf0cdSShiva Chen; RV64I-NEXT:    mv sp, a0
60*cf6cf0cdSShiva Chen; RV64I-NEXT:    addi a1, s1, 64
61*cf6cf0cdSShiva Chen; RV64I-NEXT:    call callee
62*cf6cf0cdSShiva Chen; RV64I-NEXT:    addi sp, s0, -128
63*cf6cf0cdSShiva Chen; RV64I-NEXT:    ld s1, 104(sp)
64*cf6cf0cdSShiva Chen; RV64I-NEXT:    ld s0, 112(sp)
65*cf6cf0cdSShiva Chen; RV64I-NEXT:    ld ra, 120(sp)
66*cf6cf0cdSShiva Chen; RV64I-NEXT:    addi sp, sp, 128
67*cf6cf0cdSShiva Chen; RV64I-NEXT:    ret
68*cf6cf0cdSShiva Chen  %1 = alloca i8, i32 %n
69*cf6cf0cdSShiva Chen  %2 = alloca i32, align 64
70*cf6cf0cdSShiva Chen  call void @callee(i8* %1, i32 *%2)
71*cf6cf0cdSShiva Chen  ret void
72*cf6cf0cdSShiva Chen}
73