1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=riscv32 -run-pass=finalize-isel -simplify-mir -o - %s \
3# RUN:  | FileCheck -check-prefix=RV32I %s
4# RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -run-pass=finalize-isel -simplify-mir -o - %s \
5# RUN:  | FileCheck -check-prefix=RV32IBT %s
6# RUN: llc -mtriple=riscv64 -run-pass=finalize-isel -simplify-mir -o - %s \
7# RUN:  | FileCheck -check-prefix=RV64I %s
8# RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -run-pass=finalize-isel -simplify-mir -o - %s \
9# RUN:  | FileCheck -check-prefix=RV64IBT %s
10
11# Provide dummy definitions of functions and just enough metadata to create a
12# DBG_VALUE.
13--- |
14  define void @cmov_interleaved_bad() {
15    ret void
16  }
17  define void @cmov_interleaved_debug_value() {
18    ret void
19  }
20...
21---
22# Here we have a sequence of select instructions with a non-select instruction
23# in the middle. Because the non-select depends on the result of a previous
24# select, we cannot optimize the sequence to share control-flow.
25name:            cmov_interleaved_bad
26alignment:       4
27tracksRegLiveness: true
28registers:
29  - { id: 0, class: gpr }
30  - { id: 1, class: gpr }
31  - { id: 2, class: gpr }
32  - { id: 3, class: gpr }
33  - { id: 4, class: gpr }
34  - { id: 5, class: gpr }
35  - { id: 6, class: gpr }
36  - { id: 7, class: gpr }
37  - { id: 8, class: gpr }
38  - { id: 9, class: gpr }
39  - { id: 10, class: gpr }
40liveins:
41  - { reg: '$x10', virtual-reg: '%0' }
42  - { reg: '$x11', virtual-reg: '%1' }
43  - { reg: '$x12', virtual-reg: '%2' }
44  - { reg: '$x13', virtual-reg: '%3' }
45body:             |
46  bb.0:
47    liveins: $x10, $x11, $x12, $x13
48
49    ; RV32I-LABEL: name: cmov_interleaved_bad
50    ; RV32I: successors: %bb.1, %bb.2
51    ; RV32I: liveins: $x10, $x11, $x12, $x13
52    ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x13
53    ; RV32I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
54    ; RV32I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
55    ; RV32I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
56    ; RV32I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
57    ; RV32I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
58    ; RV32I: BNE [[ANDI]], [[COPY4]], %bb.2
59    ; RV32I: .1:
60    ; RV32I: .2:
61    ; RV32I: successors: %bb.3, %bb.4
62    ; RV32I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
63    ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
64    ; RV32I: BNE [[ANDI]], [[COPY4]], %bb.4
65    ; RV32I: .3:
66    ; RV32I: .4:
67    ; RV32I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
68    ; RV32I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
69    ; RV32I: $x10 = COPY [[ADD]]
70    ; RV32I: PseudoRET implicit $x10
71    ; RV32IBT-LABEL: name: cmov_interleaved_bad
72    ; RV32IBT: successors: %bb.1, %bb.2
73    ; RV32IBT: liveins: $x10, $x11, $x12, $x13
74    ; RV32IBT: [[COPY:%[0-9]+]]:gpr = COPY $x13
75    ; RV32IBT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
76    ; RV32IBT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
77    ; RV32IBT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
78    ; RV32IBT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
79    ; RV32IBT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
80    ; RV32IBT: BNE [[ANDI]], [[COPY4]], %bb.2
81    ; RV32IBT: .1:
82    ; RV32IBT: .2:
83    ; RV32IBT: successors: %bb.3, %bb.4
84    ; RV32IBT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
85    ; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
86    ; RV32IBT: BNE [[ANDI]], [[COPY4]], %bb.4
87    ; RV32IBT: .3:
88    ; RV32IBT: .4:
89    ; RV32IBT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
90    ; RV32IBT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
91    ; RV32IBT: $x10 = COPY [[ADD]]
92    ; RV32IBT: PseudoRET implicit $x10
93    ; RV64I-LABEL: name: cmov_interleaved_bad
94    ; RV64I: successors: %bb.1, %bb.2
95    ; RV64I: liveins: $x10, $x11, $x12, $x13
96    ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x13
97    ; RV64I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
98    ; RV64I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
99    ; RV64I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
100    ; RV64I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
101    ; RV64I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
102    ; RV64I: BNE [[ANDI]], [[COPY4]], %bb.2
103    ; RV64I: .1:
104    ; RV64I: .2:
105    ; RV64I: successors: %bb.3, %bb.4
106    ; RV64I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
107    ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
108    ; RV64I: BNE [[ANDI]], [[COPY4]], %bb.4
109    ; RV64I: .3:
110    ; RV64I: .4:
111    ; RV64I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
112    ; RV64I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
113    ; RV64I: $x10 = COPY [[ADD]]
114    ; RV64I: PseudoRET implicit $x10
115    ; RV64IBT-LABEL: name: cmov_interleaved_bad
116    ; RV64IBT: successors: %bb.1, %bb.2
117    ; RV64IBT: liveins: $x10, $x11, $x12, $x13
118    ; RV64IBT: [[COPY:%[0-9]+]]:gpr = COPY $x13
119    ; RV64IBT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
120    ; RV64IBT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
121    ; RV64IBT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
122    ; RV64IBT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
123    ; RV64IBT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
124    ; RV64IBT: BNE [[ANDI]], [[COPY4]], %bb.2
125    ; RV64IBT: .1:
126    ; RV64IBT: .2:
127    ; RV64IBT: successors: %bb.3, %bb.4
128    ; RV64IBT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
129    ; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
130    ; RV64IBT: BNE [[ANDI]], [[COPY4]], %bb.4
131    ; RV64IBT: .3:
132    ; RV64IBT: .4:
133    ; RV64IBT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3
134    ; RV64IBT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
135    ; RV64IBT: $x10 = COPY [[ADD]]
136    ; RV64IBT: PseudoRET implicit $x10
137    %3:gpr = COPY $x13
138    %2:gpr = COPY $x12
139    %1:gpr = COPY $x11
140    %0:gpr = COPY $x10
141    %5:gpr = ANDI %0, 1
142    %6:gpr = COPY $x0
143    %7:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %1, %2
144    %8:gpr = ADDI %7, 1
145    %9:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %3, %2
146    %10:gpr = ADD %7, killed %9
147    $x10 = COPY %10
148    PseudoRET implicit $x10
149
150...
151---
152# Demonstrate that debug info associated with selects is correctly moved to
153# the tail basic block, while debug info associated with non-selects is left
154# in the head basic block.
155name:            cmov_interleaved_debug_value
156alignment:       4
157tracksRegLiveness: true
158registers:
159  - { id: 0, class: gpr }
160  - { id: 1, class: gpr }
161  - { id: 2, class: gpr }
162  - { id: 3, class: gpr }
163  - { id: 4, class: gpr }
164  - { id: 5, class: gpr }
165  - { id: 6, class: gpr }
166  - { id: 7, class: gpr }
167  - { id: 8, class: gpr }
168  - { id: 9, class: gpr }
169  - { id: 10, class: gpr }
170liveins:
171  - { reg: '$x10', virtual-reg: '%0' }
172  - { reg: '$x11', virtual-reg: '%1' }
173  - { reg: '$x12', virtual-reg: '%2' }
174  - { reg: '$x13', virtual-reg: '%3' }
175body:             |
176  bb.0:
177    liveins: $x10, $x11, $x12, $x13
178
179    ; RV32I-LABEL: name: cmov_interleaved_debug_value
180    ; RV32I: successors: %bb.1, %bb.2
181    ; RV32I: liveins: $x10, $x11, $x12, $x13
182    ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x13
183    ; RV32I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
184    ; RV32I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
185    ; RV32I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
186    ; RV32I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
187    ; RV32I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
188    ; RV32I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
189    ; RV32I: DBG_VALUE [[ADDI]], $noreg
190    ; RV32I: BNE [[ANDI]], [[COPY4]], %bb.2
191    ; RV32I: .1:
192    ; RV32I: .2:
193    ; RV32I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
194    ; RV32I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
195    ; RV32I: DBG_VALUE [[PHI]], $noreg
196    ; RV32I: DBG_VALUE [[PHI1]], $noreg
197    ; RV32I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
198    ; RV32I: $x10 = COPY [[ADD]]
199    ; RV32I: PseudoRET implicit $x10
200    ; RV32IBT-LABEL: name: cmov_interleaved_debug_value
201    ; RV32IBT: successors: %bb.1, %bb.2
202    ; RV32IBT: liveins: $x10, $x11, $x12, $x13
203    ; RV32IBT: [[COPY:%[0-9]+]]:gpr = COPY $x13
204    ; RV32IBT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
205    ; RV32IBT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
206    ; RV32IBT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
207    ; RV32IBT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
208    ; RV32IBT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
209    ; RV32IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
210    ; RV32IBT: DBG_VALUE [[ADDI]], $noreg
211    ; RV32IBT: BNE [[ANDI]], [[COPY4]], %bb.2
212    ; RV32IBT: .1:
213    ; RV32IBT: .2:
214    ; RV32IBT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
215    ; RV32IBT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
216    ; RV32IBT: DBG_VALUE [[PHI]], $noreg
217    ; RV32IBT: DBG_VALUE [[PHI1]], $noreg
218    ; RV32IBT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
219    ; RV32IBT: $x10 = COPY [[ADD]]
220    ; RV32IBT: PseudoRET implicit $x10
221    ; RV64I-LABEL: name: cmov_interleaved_debug_value
222    ; RV64I: successors: %bb.1, %bb.2
223    ; RV64I: liveins: $x10, $x11, $x12, $x13
224    ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x13
225    ; RV64I: [[COPY1:%[0-9]+]]:gpr = COPY $x12
226    ; RV64I: [[COPY2:%[0-9]+]]:gpr = COPY $x11
227    ; RV64I: [[COPY3:%[0-9]+]]:gpr = COPY $x10
228    ; RV64I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
229    ; RV64I: [[COPY4:%[0-9]+]]:gpr = COPY $x0
230    ; RV64I: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
231    ; RV64I: DBG_VALUE [[ADDI]], $noreg
232    ; RV64I: BNE [[ANDI]], [[COPY4]], %bb.2
233    ; RV64I: .1:
234    ; RV64I: .2:
235    ; RV64I: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
236    ; RV64I: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
237    ; RV64I: DBG_VALUE [[PHI]], $noreg
238    ; RV64I: DBG_VALUE [[PHI1]], $noreg
239    ; RV64I: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
240    ; RV64I: $x10 = COPY [[ADD]]
241    ; RV64I: PseudoRET implicit $x10
242    ; RV64IBT-LABEL: name: cmov_interleaved_debug_value
243    ; RV64IBT: successors: %bb.1, %bb.2
244    ; RV64IBT: liveins: $x10, $x11, $x12, $x13
245    ; RV64IBT: [[COPY:%[0-9]+]]:gpr = COPY $x13
246    ; RV64IBT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
247    ; RV64IBT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
248    ; RV64IBT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
249    ; RV64IBT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
250    ; RV64IBT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
251    ; RV64IBT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1
252    ; RV64IBT: DBG_VALUE [[ADDI]], $noreg
253    ; RV64IBT: BNE [[ANDI]], [[COPY4]], %bb.2
254    ; RV64IBT: .1:
255    ; RV64IBT: .2:
256    ; RV64IBT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1
257    ; RV64IBT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
258    ; RV64IBT: DBG_VALUE [[PHI]], $noreg
259    ; RV64IBT: DBG_VALUE [[PHI1]], $noreg
260    ; RV64IBT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
261    ; RV64IBT: $x10 = COPY [[ADD]]
262    ; RV64IBT: PseudoRET implicit $x10
263    %3:gpr = COPY $x13
264    %2:gpr = COPY $x12
265    %1:gpr = COPY $x11
266    %0:gpr = COPY $x10
267    %5:gpr = ANDI %0, 1
268    %6:gpr = COPY $x0
269    %7:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %1, %2
270    DBG_VALUE %7, $noreg
271    %8:gpr = ADDI %0, 1
272    DBG_VALUE %8, $noreg
273    %9:gpr = Select_GPR_Using_CC_GPR %5, %6, 22, %3, %2
274    DBG_VALUE %9, $noreg
275    %10:gpr = ADD %7, killed %9
276    $x10 = COPY %10
277    PseudoRET implicit $x10
278
279...
280---
281