1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -disable-block-placement -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32I %s
4; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -disable-block-placement -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV32IBT %s
6
7define signext i32 @foo(i32 signext %a, i32 *%b) nounwind {
8; RV32I-LABEL: foo:
9; RV32I:       # %bb.0:
10; RV32I-NEXT:    lw a2, 0(a1)
11; RV32I-NEXT:    beq a0, a2, .LBB0_2
12; RV32I-NEXT:  # %bb.1:
13; RV32I-NEXT:    mv a0, a2
14; RV32I-NEXT:  .LBB0_2:
15; RV32I-NEXT:    lw a2, 0(a1)
16; RV32I-NEXT:    bne a0, a2, .LBB0_4
17; RV32I-NEXT:  # %bb.3:
18; RV32I-NEXT:    mv a0, a2
19; RV32I-NEXT:  .LBB0_4:
20; RV32I-NEXT:    lw a2, 0(a1)
21; RV32I-NEXT:    bltu a2, a0, .LBB0_6
22; RV32I-NEXT:  # %bb.5:
23; RV32I-NEXT:    mv a0, a2
24; RV32I-NEXT:  .LBB0_6:
25; RV32I-NEXT:    lw a2, 0(a1)
26; RV32I-NEXT:    bgeu a0, a2, .LBB0_8
27; RV32I-NEXT:  # %bb.7:
28; RV32I-NEXT:    mv a0, a2
29; RV32I-NEXT:  .LBB0_8:
30; RV32I-NEXT:    lw a2, 0(a1)
31; RV32I-NEXT:    bltu a0, a2, .LBB0_10
32; RV32I-NEXT:  # %bb.9:
33; RV32I-NEXT:    mv a0, a2
34; RV32I-NEXT:  .LBB0_10:
35; RV32I-NEXT:    lw a2, 0(a1)
36; RV32I-NEXT:    bgeu a2, a0, .LBB0_12
37; RV32I-NEXT:  # %bb.11:
38; RV32I-NEXT:    mv a0, a2
39; RV32I-NEXT:  .LBB0_12:
40; RV32I-NEXT:    lw a2, 0(a1)
41; RV32I-NEXT:    blt a2, a0, .LBB0_14
42; RV32I-NEXT:  # %bb.13:
43; RV32I-NEXT:    mv a0, a2
44; RV32I-NEXT:  .LBB0_14:
45; RV32I-NEXT:    lw a2, 0(a1)
46; RV32I-NEXT:    bge a0, a2, .LBB0_16
47; RV32I-NEXT:  # %bb.15:
48; RV32I-NEXT:    mv a0, a2
49; RV32I-NEXT:  .LBB0_16:
50; RV32I-NEXT:    lw a2, 0(a1)
51; RV32I-NEXT:    blt a0, a2, .LBB0_18
52; RV32I-NEXT:  # %bb.17:
53; RV32I-NEXT:    mv a0, a2
54; RV32I-NEXT:  .LBB0_18:
55; RV32I-NEXT:    lw a2, 0(a1)
56; RV32I-NEXT:    bge a2, a0, .LBB0_20
57; RV32I-NEXT:  # %bb.19:
58; RV32I-NEXT:    mv a0, a2
59; RV32I-NEXT:  .LBB0_20:
60; RV32I-NEXT:    lw a2, 0(a1)
61; RV32I-NEXT:    blez a2, .LBB0_22
62; RV32I-NEXT:  # %bb.21:
63; RV32I-NEXT:    mv a0, a2
64; RV32I-NEXT:  .LBB0_22:
65; RV32I-NEXT:    lw a3, 0(a1)
66; RV32I-NEXT:    bgez a2, .LBB0_24
67; RV32I-NEXT:  # %bb.23:
68; RV32I-NEXT:    mv a0, a3
69; RV32I-NEXT:  .LBB0_24:
70; RV32I-NEXT:    lw a3, 0(a1)
71; RV32I-NEXT:    li a4, 1024
72; RV32I-NEXT:    blt a4, a3, .LBB0_26
73; RV32I-NEXT:  # %bb.25:
74; RV32I-NEXT:    mv a0, a3
75; RV32I-NEXT:  .LBB0_26:
76; RV32I-NEXT:    lw a1, 0(a1)
77; RV32I-NEXT:    li a3, 2046
78; RV32I-NEXT:    bltu a3, a2, .LBB0_28
79; RV32I-NEXT:  # %bb.27:
80; RV32I-NEXT:    mv a0, a1
81; RV32I-NEXT:  .LBB0_28:
82; RV32I-NEXT:    ret
83;
84; RV32IBT-LABEL: foo:
85; RV32IBT:       # %bb.0:
86; RV32IBT-NEXT:    lw a2, 0(a1)
87; RV32IBT-NEXT:    lw a3, 0(a1)
88; RV32IBT-NEXT:    xor a4, a0, a2
89; RV32IBT-NEXT:    cmov a0, a4, a2, a0
90; RV32IBT-NEXT:    lw a2, 0(a1)
91; RV32IBT-NEXT:    xor a4, a0, a3
92; RV32IBT-NEXT:    cmov a0, a4, a0, a3
93; RV32IBT-NEXT:    lw a3, 0(a1)
94; RV32IBT-NEXT:    sltu a4, a2, a0
95; RV32IBT-NEXT:    cmov a0, a4, a0, a2
96; RV32IBT-NEXT:    lw a2, 0(a1)
97; RV32IBT-NEXT:    sltu a4, a0, a3
98; RV32IBT-NEXT:    cmov a0, a4, a3, a0
99; RV32IBT-NEXT:    lw a3, 0(a1)
100; RV32IBT-NEXT:    sltu a4, a0, a2
101; RV32IBT-NEXT:    cmov a0, a4, a0, a2
102; RV32IBT-NEXT:    lw a2, 0(a1)
103; RV32IBT-NEXT:    sltu a4, a3, a0
104; RV32IBT-NEXT:    cmov a0, a4, a3, a0
105; RV32IBT-NEXT:    lw a3, 0(a1)
106; RV32IBT-NEXT:    slt a4, a2, a0
107; RV32IBT-NEXT:    cmov a0, a4, a0, a2
108; RV32IBT-NEXT:    lw a2, 0(a1)
109; RV32IBT-NEXT:    slt a4, a0, a3
110; RV32IBT-NEXT:    cmov a0, a4, a3, a0
111; RV32IBT-NEXT:    lw a3, 0(a1)
112; RV32IBT-NEXT:    slt a4, a0, a2
113; RV32IBT-NEXT:    lw a5, 0(a1)
114; RV32IBT-NEXT:    cmov a0, a4, a0, a2
115; RV32IBT-NEXT:    slt a2, a3, a0
116; RV32IBT-NEXT:    cmov a0, a2, a3, a0
117; RV32IBT-NEXT:    slti a2, a5, 1
118; RV32IBT-NEXT:    lw a3, 0(a1)
119; RV32IBT-NEXT:    cmov a0, a2, a0, a5
120; RV32IBT-NEXT:    lw a2, 0(a1)
121; RV32IBT-NEXT:    slti a4, a5, 0
122; RV32IBT-NEXT:    cmov a0, a4, a3, a0
123; RV32IBT-NEXT:    lw a1, 0(a1)
124; RV32IBT-NEXT:    slti a3, a2, 1025
125; RV32IBT-NEXT:    cmov a0, a3, a2, a0
126; RV32IBT-NEXT:    sltiu a2, a5, 2047
127; RV32IBT-NEXT:    cmov a0, a2, a1, a0
128; RV32IBT-NEXT:    ret
129  %val1 = load volatile i32, i32* %b
130  %tst1 = icmp eq i32 %a, %val1
131  %val2 = select i1 %tst1, i32 %a, i32 %val1
132
133  %val3 = load volatile i32, i32* %b
134  %tst2 = icmp ne i32 %val2, %val3
135  %val4 = select i1 %tst2, i32 %val2, i32 %val3
136
137  %val5 = load volatile i32, i32* %b
138  %tst3 = icmp ugt i32 %val4, %val5
139  %val6 = select i1 %tst3, i32 %val4, i32 %val5
140
141  %val7 = load volatile i32, i32* %b
142  %tst4 = icmp uge i32 %val6, %val7
143  %val8 = select i1 %tst4, i32 %val6, i32 %val7
144
145  %val9 = load volatile i32, i32* %b
146  %tst5 = icmp ult i32 %val8, %val9
147  %val10 = select i1 %tst5, i32 %val8, i32 %val9
148
149  %val11 = load volatile i32, i32* %b
150  %tst6 = icmp ule i32 %val10, %val11
151  %val12 = select i1 %tst6, i32 %val10, i32 %val11
152
153  %val13 = load volatile i32, i32* %b
154  %tst7 = icmp sgt i32 %val12, %val13
155  %val14 = select i1 %tst7, i32 %val12, i32 %val13
156
157  %val15 = load volatile i32, i32* %b
158  %tst8 = icmp sge i32 %val14, %val15
159  %val16 = select i1 %tst8, i32 %val14, i32 %val15
160
161  %val17 = load volatile i32, i32* %b
162  %tst9 = icmp slt i32 %val16, %val17
163  %val18 = select i1 %tst9, i32 %val16, i32 %val17
164
165  %val19 = load volatile i32, i32* %b
166  %tst10 = icmp sle i32 %val18, %val19
167  %val20 = select i1 %tst10, i32 %val18, i32 %val19
168
169  %val21 = load volatile i32, i32* %b
170  %tst11 = icmp slt i32 %val21, 1
171  %val22 = select i1 %tst11, i32 %val20, i32 %val21
172
173  %val23 = load volatile i32, i32* %b
174  %tst12 = icmp sgt i32 %val21, -1
175  %val24 = select i1 %tst12, i32 %val22, i32 %val23
176
177  %val25 = load volatile i32, i32* %b
178  %tst13 = icmp sgt i32 %val25, 1024
179  %val26 = select i1 %tst13, i32 %val24, i32 %val25
180
181  %val27 = load volatile i32, i32* %b
182  %tst14 = icmp ugt i32 %val21, 2046
183  %val28 = select i1 %tst14, i32 %val26, i32 %val27
184  ret i32 %val28
185}
186
187; Test that we can ComputeNumSignBits across basic blocks when the live out is
188; RISCVISD::SELECT_CC. There should be no slli+srai or sext.h in the output.
189define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2, i16 signext %3) nounwind {
190; RV32I-LABEL: numsignbits:
191; RV32I:       # %bb.0:
192; RV32I-NEXT:    addi sp, sp, -16
193; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
194; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
195; RV32I-NEXT:    mv s0, a3
196; RV32I-NEXT:    beqz a0, .LBB1_2
197; RV32I-NEXT:  # %bb.1:
198; RV32I-NEXT:    mv s0, a2
199; RV32I-NEXT:  .LBB1_2:
200; RV32I-NEXT:    beqz a1, .LBB1_4
201; RV32I-NEXT:  # %bb.3:
202; RV32I-NEXT:    mv a0, s0
203; RV32I-NEXT:    call bar@plt
204; RV32I-NEXT:  .LBB1_4:
205; RV32I-NEXT:    mv a0, s0
206; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
207; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
208; RV32I-NEXT:    addi sp, sp, 16
209; RV32I-NEXT:    ret
210;
211; RV32IBT-LABEL: numsignbits:
212; RV32IBT:       # %bb.0:
213; RV32IBT-NEXT:    addi sp, sp, -16
214; RV32IBT-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
215; RV32IBT-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
216; RV32IBT-NEXT:    cmov s0, a0, a2, a3
217; RV32IBT-NEXT:    beqz a1, .LBB1_2
218; RV32IBT-NEXT:  # %bb.1:
219; RV32IBT-NEXT:    mv a0, s0
220; RV32IBT-NEXT:    call bar@plt
221; RV32IBT-NEXT:  .LBB1_2:
222; RV32IBT-NEXT:    mv a0, s0
223; RV32IBT-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
224; RV32IBT-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
225; RV32IBT-NEXT:    addi sp, sp, 16
226; RV32IBT-NEXT:    ret
227  %5 = icmp eq i16 %0, 0
228  %6 = select i1 %5, i16 %3, i16 %2
229  %7 = icmp eq i16 %1, 0
230  br i1 %7, label %9, label %8
231
2328:                                                ; preds = %4
233  tail call void @bar(i16 signext %6)
234  br label %9
235
2369:                                                ; preds = %8, %4
237  ret i16 %6
238}
239
240declare void @bar(i16 signext)
241