1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I
3; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I
4
5declare i4 @llvm.sadd.sat.i4(i4, i4)
6declare i8 @llvm.sadd.sat.i8(i8, i8)
7declare i16 @llvm.sadd.sat.i16(i16, i16)
8declare i32 @llvm.sadd.sat.i32(i32, i32)
9declare i64 @llvm.sadd.sat.i64(i64, i64)
10
11define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
12; RV32I-LABEL: func32:
13; RV32I:       # %bb.0:
14; RV32I-NEXT:    mul a2, a1, a2
15; RV32I-NEXT:    add a1, a0, a2
16; RV32I-NEXT:    slt a0, a1, a0
17; RV32I-NEXT:    slti a2, a2, 0
18; RV32I-NEXT:    xor a2, a2, a0
19; RV32I-NEXT:    lui a0, 524288
20; RV32I-NEXT:    bltz a1, .LBB0_3
21; RV32I-NEXT:  # %bb.1:
22; RV32I-NEXT:    beqz a2, .LBB0_4
23; RV32I-NEXT:  .LBB0_2:
24; RV32I-NEXT:    ret
25; RV32I-NEXT:  .LBB0_3:
26; RV32I-NEXT:    addi a0, a0, -1
27; RV32I-NEXT:    bnez a2, .LBB0_2
28; RV32I-NEXT:  .LBB0_4:
29; RV32I-NEXT:    mv a0, a1
30; RV32I-NEXT:    ret
31;
32; RV64I-LABEL: func32:
33; RV64I:       # %bb.0:
34; RV64I-NEXT:    sext.w a0, a0
35; RV64I-NEXT:    mulw a1, a1, a2
36; RV64I-NEXT:    add a0, a0, a1
37; RV64I-NEXT:    lui a1, 524288
38; RV64I-NEXT:    addiw a2, a1, -1
39; RV64I-NEXT:    bge a0, a2, .LBB0_3
40; RV64I-NEXT:  # %bb.1:
41; RV64I-NEXT:    bge a1, a0, .LBB0_4
42; RV64I-NEXT:  .LBB0_2:
43; RV64I-NEXT:    ret
44; RV64I-NEXT:  .LBB0_3:
45; RV64I-NEXT:    mv a0, a2
46; RV64I-NEXT:    blt a1, a0, .LBB0_2
47; RV64I-NEXT:  .LBB0_4:
48; RV64I-NEXT:    lui a0, 524288
49; RV64I-NEXT:    ret
50  %a = mul i32 %y, %z
51  %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %a)
52  ret i32 %tmp
53}
54
55define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
56; RV32I-LABEL: func64:
57; RV32I:       # %bb.0:
58; RV32I-NEXT:    mv a2, a0
59; RV32I-NEXT:    add a3, a1, a5
60; RV32I-NEXT:    add a0, a0, a4
61; RV32I-NEXT:    sltu a2, a0, a2
62; RV32I-NEXT:    add a2, a3, a2
63; RV32I-NEXT:    addi a6, zero, -1
64; RV32I-NEXT:    addi a7, zero, 1
65; RV32I-NEXT:    addi a3, zero, 1
66; RV32I-NEXT:    beqz a2, .LBB1_2
67; RV32I-NEXT:  # %bb.1:
68; RV32I-NEXT:    slt a3, a6, a2
69; RV32I-NEXT:  .LBB1_2:
70; RV32I-NEXT:    addi a4, zero, 1
71; RV32I-NEXT:    beqz a1, .LBB1_4
72; RV32I-NEXT:  # %bb.3:
73; RV32I-NEXT:    slt a4, a6, a1
74; RV32I-NEXT:  .LBB1_4:
75; RV32I-NEXT:    xor a1, a4, a3
76; RV32I-NEXT:    snez a1, a1
77; RV32I-NEXT:    beqz a5, .LBB1_6
78; RV32I-NEXT:  # %bb.5:
79; RV32I-NEXT:    slt a7, a6, a5
80; RV32I-NEXT:  .LBB1_6:
81; RV32I-NEXT:    xor a3, a4, a7
82; RV32I-NEXT:    seqz a3, a3
83; RV32I-NEXT:    and a3, a3, a1
84; RV32I-NEXT:    bnez a3, .LBB1_10
85; RV32I-NEXT:  # %bb.7:
86; RV32I-NEXT:    lui a1, 524288
87; RV32I-NEXT:    bltz a2, .LBB1_11
88; RV32I-NEXT:  .LBB1_8:
89; RV32I-NEXT:    beqz a3, .LBB1_12
90; RV32I-NEXT:  .LBB1_9:
91; RV32I-NEXT:    ret
92; RV32I-NEXT:  .LBB1_10:
93; RV32I-NEXT:    srai a0, a2, 31
94; RV32I-NEXT:    lui a1, 524288
95; RV32I-NEXT:    bgez a2, .LBB1_8
96; RV32I-NEXT:  .LBB1_11:
97; RV32I-NEXT:    addi a1, a1, -1
98; RV32I-NEXT:    bnez a3, .LBB1_9
99; RV32I-NEXT:  .LBB1_12:
100; RV32I-NEXT:    mv a1, a2
101; RV32I-NEXT:    ret
102;
103; RV64I-LABEL: func64:
104; RV64I:       # %bb.0:
105; RV64I-NEXT:    mv a1, a0
106; RV64I-NEXT:    add a3, a0, a2
107; RV64I-NEXT:    addi a0, zero, -1
108; RV64I-NEXT:    slli a0, a0, 63
109; RV64I-NEXT:    bgez a3, .LBB1_2
110; RV64I-NEXT:  # %bb.1:
111; RV64I-NEXT:    addi a0, a0, -1
112; RV64I-NEXT:  .LBB1_2:
113; RV64I-NEXT:    slt a1, a3, a1
114; RV64I-NEXT:    slti a2, a2, 0
115; RV64I-NEXT:    xor a1, a2, a1
116; RV64I-NEXT:    bnez a1, .LBB1_4
117; RV64I-NEXT:  # %bb.3:
118; RV64I-NEXT:    mv a0, a3
119; RV64I-NEXT:  .LBB1_4:
120; RV64I-NEXT:    ret
121  %a = mul i64 %y, %z
122  %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %z)
123  ret i64 %tmp
124}
125
126define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
127; RV32I-LABEL: func16:
128; RV32I:       # %bb.0:
129; RV32I-NEXT:    slli a0, a0, 16
130; RV32I-NEXT:    srai a0, a0, 16
131; RV32I-NEXT:    mul a1, a1, a2
132; RV32I-NEXT:    slli a1, a1, 16
133; RV32I-NEXT:    srai a1, a1, 16
134; RV32I-NEXT:    add a0, a0, a1
135; RV32I-NEXT:    lui a1, 8
136; RV32I-NEXT:    addi a1, a1, -1
137; RV32I-NEXT:    bge a0, a1, .LBB2_3
138; RV32I-NEXT:  # %bb.1:
139; RV32I-NEXT:    lui a1, 1048568
140; RV32I-NEXT:    bge a1, a0, .LBB2_4
141; RV32I-NEXT:  .LBB2_2:
142; RV32I-NEXT:    ret
143; RV32I-NEXT:  .LBB2_3:
144; RV32I-NEXT:    mv a0, a1
145; RV32I-NEXT:    lui a1, 1048568
146; RV32I-NEXT:    blt a1, a0, .LBB2_2
147; RV32I-NEXT:  .LBB2_4:
148; RV32I-NEXT:    lui a0, 1048568
149; RV32I-NEXT:    ret
150;
151; RV64I-LABEL: func16:
152; RV64I:       # %bb.0:
153; RV64I-NEXT:    slli a0, a0, 48
154; RV64I-NEXT:    srai a0, a0, 48
155; RV64I-NEXT:    mul a1, a1, a2
156; RV64I-NEXT:    slli a1, a1, 48
157; RV64I-NEXT:    srai a1, a1, 48
158; RV64I-NEXT:    add a0, a0, a1
159; RV64I-NEXT:    lui a1, 8
160; RV64I-NEXT:    addiw a1, a1, -1
161; RV64I-NEXT:    bge a0, a1, .LBB2_3
162; RV64I-NEXT:  # %bb.1:
163; RV64I-NEXT:    lui a1, 1048568
164; RV64I-NEXT:    bge a1, a0, .LBB2_4
165; RV64I-NEXT:  .LBB2_2:
166; RV64I-NEXT:    ret
167; RV64I-NEXT:  .LBB2_3:
168; RV64I-NEXT:    mv a0, a1
169; RV64I-NEXT:    lui a1, 1048568
170; RV64I-NEXT:    blt a1, a0, .LBB2_2
171; RV64I-NEXT:  .LBB2_4:
172; RV64I-NEXT:    lui a0, 1048568
173; RV64I-NEXT:    ret
174  %a = mul i16 %y, %z
175  %tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %a)
176  ret i16 %tmp
177}
178
179define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
180; RV32I-LABEL: func8:
181; RV32I:       # %bb.0:
182; RV32I-NEXT:    slli a0, a0, 24
183; RV32I-NEXT:    srai a0, a0, 24
184; RV32I-NEXT:    mul a1, a1, a2
185; RV32I-NEXT:    slli a1, a1, 24
186; RV32I-NEXT:    srai a1, a1, 24
187; RV32I-NEXT:    add a0, a0, a1
188; RV32I-NEXT:    addi a1, zero, 127
189; RV32I-NEXT:    bge a0, a1, .LBB3_3
190; RV32I-NEXT:  # %bb.1:
191; RV32I-NEXT:    addi a1, zero, -128
192; RV32I-NEXT:    bge a1, a0, .LBB3_4
193; RV32I-NEXT:  .LBB3_2:
194; RV32I-NEXT:    ret
195; RV32I-NEXT:  .LBB3_3:
196; RV32I-NEXT:    addi a0, zero, 127
197; RV32I-NEXT:    addi a1, zero, -128
198; RV32I-NEXT:    blt a1, a0, .LBB3_2
199; RV32I-NEXT:  .LBB3_4:
200; RV32I-NEXT:    addi a0, zero, -128
201; RV32I-NEXT:    ret
202;
203; RV64I-LABEL: func8:
204; RV64I:       # %bb.0:
205; RV64I-NEXT:    slli a0, a0, 56
206; RV64I-NEXT:    srai a0, a0, 56
207; RV64I-NEXT:    mul a1, a1, a2
208; RV64I-NEXT:    slli a1, a1, 56
209; RV64I-NEXT:    srai a1, a1, 56
210; RV64I-NEXT:    add a0, a0, a1
211; RV64I-NEXT:    addi a1, zero, 127
212; RV64I-NEXT:    bge a0, a1, .LBB3_3
213; RV64I-NEXT:  # %bb.1:
214; RV64I-NEXT:    addi a1, zero, -128
215; RV64I-NEXT:    bge a1, a0, .LBB3_4
216; RV64I-NEXT:  .LBB3_2:
217; RV64I-NEXT:    ret
218; RV64I-NEXT:  .LBB3_3:
219; RV64I-NEXT:    addi a0, zero, 127
220; RV64I-NEXT:    addi a1, zero, -128
221; RV64I-NEXT:    blt a1, a0, .LBB3_2
222; RV64I-NEXT:  .LBB3_4:
223; RV64I-NEXT:    addi a0, zero, -128
224; RV64I-NEXT:    ret
225  %a = mul i8 %y, %z
226  %tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %a)
227  ret i8 %tmp
228}
229
230define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
231; RV32I-LABEL: func4:
232; RV32I:       # %bb.0:
233; RV32I-NEXT:    slli a0, a0, 28
234; RV32I-NEXT:    srai a0, a0, 28
235; RV32I-NEXT:    mul a1, a1, a2
236; RV32I-NEXT:    slli a1, a1, 28
237; RV32I-NEXT:    srai a1, a1, 28
238; RV32I-NEXT:    add a0, a0, a1
239; RV32I-NEXT:    addi a1, zero, 7
240; RV32I-NEXT:    bge a0, a1, .LBB4_3
241; RV32I-NEXT:  # %bb.1:
242; RV32I-NEXT:    addi a1, zero, -8
243; RV32I-NEXT:    bge a1, a0, .LBB4_4
244; RV32I-NEXT:  .LBB4_2:
245; RV32I-NEXT:    ret
246; RV32I-NEXT:  .LBB4_3:
247; RV32I-NEXT:    addi a0, zero, 7
248; RV32I-NEXT:    addi a1, zero, -8
249; RV32I-NEXT:    blt a1, a0, .LBB4_2
250; RV32I-NEXT:  .LBB4_4:
251; RV32I-NEXT:    addi a0, zero, -8
252; RV32I-NEXT:    ret
253;
254; RV64I-LABEL: func4:
255; RV64I:       # %bb.0:
256; RV64I-NEXT:    slli a0, a0, 60
257; RV64I-NEXT:    srai a0, a0, 60
258; RV64I-NEXT:    mul a1, a1, a2
259; RV64I-NEXT:    slli a1, a1, 60
260; RV64I-NEXT:    srai a1, a1, 60
261; RV64I-NEXT:    add a0, a0, a1
262; RV64I-NEXT:    addi a1, zero, 7
263; RV64I-NEXT:    bge a0, a1, .LBB4_3
264; RV64I-NEXT:  # %bb.1:
265; RV64I-NEXT:    addi a1, zero, -8
266; RV64I-NEXT:    bge a1, a0, .LBB4_4
267; RV64I-NEXT:  .LBB4_2:
268; RV64I-NEXT:    ret
269; RV64I-NEXT:  .LBB4_3:
270; RV64I-NEXT:    addi a0, zero, 7
271; RV64I-NEXT:    addi a1, zero, -8
272; RV64I-NEXT:    blt a1, a0, .LBB4_2
273; RV64I-NEXT:  .LBB4_4:
274; RV64I-NEXT:    addi a0, zero, -8
275; RV64I-NEXT:    ret
276  %a = mul i4 %y, %z
277  %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %a)
278  ret i4 %tmp
279}
280