1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
3; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
4
5define <vscale x 1 x i8> @vsub_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
6; CHECK-LABEL: vsub_vv_nxv1i8:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
9; CHECK-NEXT:    vsub.vv v8, v8, v9
10; CHECK-NEXT:    ret
11  %vc = sub <vscale x 1 x i8> %va, %vb
12  ret <vscale x 1 x i8> %vc
13}
14
15define <vscale x 1 x i8> @vsub_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
16; CHECK-LABEL: vsub_vx_nxv1i8:
17; CHECK:       # %bb.0:
18; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
19; CHECK-NEXT:    vsub.vx v8, v8, a0
20; CHECK-NEXT:    ret
21  %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
22  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
23  %vc = sub <vscale x 1 x i8> %va, %splat
24  ret <vscale x 1 x i8> %vc
25}
26
27define <vscale x 1 x i8> @vsub_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
28; CHECK-LABEL: vsub_vx_nxv1i8_0:
29; CHECK:       # %bb.0:
30; CHECK-NEXT:    li a0, 1
31; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
32; CHECK-NEXT:    vsub.vx v8, v8, a0
33; CHECK-NEXT:    ret
34  %head = insertelement <vscale x 1 x i8> undef, i8 1, i32 0
35  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
36  %vc = sub <vscale x 1 x i8> %va, %splat
37  ret <vscale x 1 x i8> %vc
38}
39
40; Test constant subs to see if we can optimize them away for scalable vectors.
41define <vscale x 1 x i8> @vsub_ii_nxv1i8_1() {
42; CHECK-LABEL: vsub_ii_nxv1i8_1:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
45; CHECK-NEXT:    vmv.v.i v8, -1
46; CHECK-NEXT:    ret
47  %heada = insertelement <vscale x 1 x i8> undef, i8 2, i32 0
48  %splata = shufflevector <vscale x 1 x i8> %heada, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
49  %headb = insertelement <vscale x 1 x i8> undef, i8 3, i32 0
50  %splatb = shufflevector <vscale x 1 x i8> %headb, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
51  %vc = sub <vscale x 1 x i8> %splata, %splatb
52  ret <vscale x 1 x i8> %vc
53}
54
55define <vscale x 2 x i8> @vsub_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
56; CHECK-LABEL: vsub_vv_nxv2i8:
57; CHECK:       # %bb.0:
58; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
59; CHECK-NEXT:    vsub.vv v8, v8, v9
60; CHECK-NEXT:    ret
61  %vc = sub <vscale x 2 x i8> %va, %vb
62  ret <vscale x 2 x i8> %vc
63}
64
65define <vscale x 2 x i8> @vsub_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
66; CHECK-LABEL: vsub_vx_nxv2i8:
67; CHECK:       # %bb.0:
68; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
69; CHECK-NEXT:    vsub.vx v8, v8, a0
70; CHECK-NEXT:    ret
71  %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
72  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
73  %vc = sub <vscale x 2 x i8> %va, %splat
74  ret <vscale x 2 x i8> %vc
75}
76
77define <vscale x 2 x i8> @vsub_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
78; CHECK-LABEL: vsub_vx_nxv2i8_0:
79; CHECK:       # %bb.0:
80; CHECK-NEXT:    li a0, 1
81; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
82; CHECK-NEXT:    vsub.vx v8, v8, a0
83; CHECK-NEXT:    ret
84  %head = insertelement <vscale x 2 x i8> undef, i8 1, i32 0
85  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
86  %vc = sub <vscale x 2 x i8> %va, %splat
87  ret <vscale x 2 x i8> %vc
88}
89
90define <vscale x 4 x i8> @vsub_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
91; CHECK-LABEL: vsub_vv_nxv4i8:
92; CHECK:       # %bb.0:
93; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
94; CHECK-NEXT:    vsub.vv v8, v8, v9
95; CHECK-NEXT:    ret
96  %vc = sub <vscale x 4 x i8> %va, %vb
97  ret <vscale x 4 x i8> %vc
98}
99
100define <vscale x 4 x i8> @vsub_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
101; CHECK-LABEL: vsub_vx_nxv4i8:
102; CHECK:       # %bb.0:
103; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
104; CHECK-NEXT:    vsub.vx v8, v8, a0
105; CHECK-NEXT:    ret
106  %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
107  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
108  %vc = sub <vscale x 4 x i8> %va, %splat
109  ret <vscale x 4 x i8> %vc
110}
111
112define <vscale x 4 x i8> @vsub_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
113; CHECK-LABEL: vsub_vx_nxv4i8_0:
114; CHECK:       # %bb.0:
115; CHECK-NEXT:    li a0, 1
116; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
117; CHECK-NEXT:    vsub.vx v8, v8, a0
118; CHECK-NEXT:    ret
119  %head = insertelement <vscale x 4 x i8> undef, i8 1, i32 0
120  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
121  %vc = sub <vscale x 4 x i8> %va, %splat
122  ret <vscale x 4 x i8> %vc
123}
124
125define <vscale x 8 x i8> @vsub_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
126; CHECK-LABEL: vsub_vv_nxv8i8:
127; CHECK:       # %bb.0:
128; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
129; CHECK-NEXT:    vsub.vv v8, v8, v9
130; CHECK-NEXT:    ret
131  %vc = sub <vscale x 8 x i8> %va, %vb
132  ret <vscale x 8 x i8> %vc
133}
134
135define <vscale x 8 x i8> @vsub_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
136; CHECK-LABEL: vsub_vx_nxv8i8:
137; CHECK:       # %bb.0:
138; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
139; CHECK-NEXT:    vsub.vx v8, v8, a0
140; CHECK-NEXT:    ret
141  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
142  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
143  %vc = sub <vscale x 8 x i8> %va, %splat
144  ret <vscale x 8 x i8> %vc
145}
146
147define <vscale x 8 x i8> @vsub_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
148; CHECK-LABEL: vsub_vx_nxv8i8_0:
149; CHECK:       # %bb.0:
150; CHECK-NEXT:    li a0, 1
151; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
152; CHECK-NEXT:    vsub.vx v8, v8, a0
153; CHECK-NEXT:    ret
154  %head = insertelement <vscale x 8 x i8> undef, i8 1, i32 0
155  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
156  %vc = sub <vscale x 8 x i8> %va, %splat
157  ret <vscale x 8 x i8> %vc
158}
159
160define <vscale x 16 x i8> @vsub_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
161; CHECK-LABEL: vsub_vv_nxv16i8:
162; CHECK:       # %bb.0:
163; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
164; CHECK-NEXT:    vsub.vv v8, v8, v10
165; CHECK-NEXT:    ret
166  %vc = sub <vscale x 16 x i8> %va, %vb
167  ret <vscale x 16 x i8> %vc
168}
169
170define <vscale x 16 x i8> @vsub_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
171; CHECK-LABEL: vsub_vx_nxv16i8:
172; CHECK:       # %bb.0:
173; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
174; CHECK-NEXT:    vsub.vx v8, v8, a0
175; CHECK-NEXT:    ret
176  %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
177  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
178  %vc = sub <vscale x 16 x i8> %va, %splat
179  ret <vscale x 16 x i8> %vc
180}
181
182define <vscale x 16 x i8> @vsub_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
183; CHECK-LABEL: vsub_vx_nxv16i8_0:
184; CHECK:       # %bb.0:
185; CHECK-NEXT:    li a0, 1
186; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
187; CHECK-NEXT:    vsub.vx v8, v8, a0
188; CHECK-NEXT:    ret
189  %head = insertelement <vscale x 16 x i8> undef, i8 1, i32 0
190  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
191  %vc = sub <vscale x 16 x i8> %va, %splat
192  ret <vscale x 16 x i8> %vc
193}
194
195define <vscale x 32 x i8> @vsub_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
196; CHECK-LABEL: vsub_vv_nxv32i8:
197; CHECK:       # %bb.0:
198; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
199; CHECK-NEXT:    vsub.vv v8, v8, v12
200; CHECK-NEXT:    ret
201  %vc = sub <vscale x 32 x i8> %va, %vb
202  ret <vscale x 32 x i8> %vc
203}
204
205define <vscale x 32 x i8> @vsub_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
206; CHECK-LABEL: vsub_vx_nxv32i8:
207; CHECK:       # %bb.0:
208; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
209; CHECK-NEXT:    vsub.vx v8, v8, a0
210; CHECK-NEXT:    ret
211  %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
212  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
213  %vc = sub <vscale x 32 x i8> %va, %splat
214  ret <vscale x 32 x i8> %vc
215}
216
217define <vscale x 32 x i8> @vsub_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
218; CHECK-LABEL: vsub_vx_nxv32i8_0:
219; CHECK:       # %bb.0:
220; CHECK-NEXT:    li a0, 1
221; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
222; CHECK-NEXT:    vsub.vx v8, v8, a0
223; CHECK-NEXT:    ret
224  %head = insertelement <vscale x 32 x i8> undef, i8 1, i32 0
225  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
226  %vc = sub <vscale x 32 x i8> %va, %splat
227  ret <vscale x 32 x i8> %vc
228}
229
230define <vscale x 64 x i8> @vsub_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
231; CHECK-LABEL: vsub_vv_nxv64i8:
232; CHECK:       # %bb.0:
233; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
234; CHECK-NEXT:    vsub.vv v8, v8, v16
235; CHECK-NEXT:    ret
236  %vc = sub <vscale x 64 x i8> %va, %vb
237  ret <vscale x 64 x i8> %vc
238}
239
240define <vscale x 64 x i8> @vsub_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
241; CHECK-LABEL: vsub_vx_nxv64i8:
242; CHECK:       # %bb.0:
243; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
244; CHECK-NEXT:    vsub.vx v8, v8, a0
245; CHECK-NEXT:    ret
246  %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
247  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
248  %vc = sub <vscale x 64 x i8> %va, %splat
249  ret <vscale x 64 x i8> %vc
250}
251
252define <vscale x 64 x i8> @vsub_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
253; CHECK-LABEL: vsub_vx_nxv64i8_0:
254; CHECK:       # %bb.0:
255; CHECK-NEXT:    li a0, 1
256; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
257; CHECK-NEXT:    vsub.vx v8, v8, a0
258; CHECK-NEXT:    ret
259  %head = insertelement <vscale x 64 x i8> undef, i8 1, i32 0
260  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
261  %vc = sub <vscale x 64 x i8> %va, %splat
262  ret <vscale x 64 x i8> %vc
263}
264
265define <vscale x 1 x i16> @vsub_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
266; CHECK-LABEL: vsub_vv_nxv1i16:
267; CHECK:       # %bb.0:
268; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
269; CHECK-NEXT:    vsub.vv v8, v8, v9
270; CHECK-NEXT:    ret
271  %vc = sub <vscale x 1 x i16> %va, %vb
272  ret <vscale x 1 x i16> %vc
273}
274
275define <vscale x 1 x i16> @vsub_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
276; CHECK-LABEL: vsub_vx_nxv1i16:
277; CHECK:       # %bb.0:
278; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
279; CHECK-NEXT:    vsub.vx v8, v8, a0
280; CHECK-NEXT:    ret
281  %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
282  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
283  %vc = sub <vscale x 1 x i16> %va, %splat
284  ret <vscale x 1 x i16> %vc
285}
286
287define <vscale x 1 x i16> @vsub_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
288; CHECK-LABEL: vsub_vx_nxv1i16_0:
289; CHECK:       # %bb.0:
290; CHECK-NEXT:    li a0, 1
291; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
292; CHECK-NEXT:    vsub.vx v8, v8, a0
293; CHECK-NEXT:    ret
294  %head = insertelement <vscale x 1 x i16> undef, i16 1, i32 0
295  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
296  %vc = sub <vscale x 1 x i16> %va, %splat
297  ret <vscale x 1 x i16> %vc
298}
299
300define <vscale x 2 x i16> @vsub_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
301; CHECK-LABEL: vsub_vv_nxv2i16:
302; CHECK:       # %bb.0:
303; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
304; CHECK-NEXT:    vsub.vv v8, v8, v9
305; CHECK-NEXT:    ret
306  %vc = sub <vscale x 2 x i16> %va, %vb
307  ret <vscale x 2 x i16> %vc
308}
309
310define <vscale x 2 x i16> @vsub_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
311; CHECK-LABEL: vsub_vx_nxv2i16:
312; CHECK:       # %bb.0:
313; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
314; CHECK-NEXT:    vsub.vx v8, v8, a0
315; CHECK-NEXT:    ret
316  %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
317  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
318  %vc = sub <vscale x 2 x i16> %va, %splat
319  ret <vscale x 2 x i16> %vc
320}
321
322define <vscale x 2 x i16> @vsub_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
323; CHECK-LABEL: vsub_vx_nxv2i16_0:
324; CHECK:       # %bb.0:
325; CHECK-NEXT:    li a0, 1
326; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
327; CHECK-NEXT:    vsub.vx v8, v8, a0
328; CHECK-NEXT:    ret
329  %head = insertelement <vscale x 2 x i16> undef, i16 1, i32 0
330  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
331  %vc = sub <vscale x 2 x i16> %va, %splat
332  ret <vscale x 2 x i16> %vc
333}
334
335define <vscale x 4 x i16> @vsub_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
336; CHECK-LABEL: vsub_vv_nxv4i16:
337; CHECK:       # %bb.0:
338; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
339; CHECK-NEXT:    vsub.vv v8, v8, v9
340; CHECK-NEXT:    ret
341  %vc = sub <vscale x 4 x i16> %va, %vb
342  ret <vscale x 4 x i16> %vc
343}
344
345define <vscale x 4 x i16> @vsub_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
346; CHECK-LABEL: vsub_vx_nxv4i16:
347; CHECK:       # %bb.0:
348; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
349; CHECK-NEXT:    vsub.vx v8, v8, a0
350; CHECK-NEXT:    ret
351  %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
352  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
353  %vc = sub <vscale x 4 x i16> %va, %splat
354  ret <vscale x 4 x i16> %vc
355}
356
357define <vscale x 4 x i16> @vsub_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
358; CHECK-LABEL: vsub_vx_nxv4i16_0:
359; CHECK:       # %bb.0:
360; CHECK-NEXT:    li a0, 1
361; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
362; CHECK-NEXT:    vsub.vx v8, v8, a0
363; CHECK-NEXT:    ret
364  %head = insertelement <vscale x 4 x i16> undef, i16 1, i32 0
365  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
366  %vc = sub <vscale x 4 x i16> %va, %splat
367  ret <vscale x 4 x i16> %vc
368}
369
370define <vscale x 8 x i16> @vsub_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
371; CHECK-LABEL: vsub_vv_nxv8i16:
372; CHECK:       # %bb.0:
373; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
374; CHECK-NEXT:    vsub.vv v8, v8, v10
375; CHECK-NEXT:    ret
376  %vc = sub <vscale x 8 x i16> %va, %vb
377  ret <vscale x 8 x i16> %vc
378}
379
380define <vscale x 8 x i16> @vsub_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
381; CHECK-LABEL: vsub_vx_nxv8i16:
382; CHECK:       # %bb.0:
383; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
384; CHECK-NEXT:    vsub.vx v8, v8, a0
385; CHECK-NEXT:    ret
386  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
387  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
388  %vc = sub <vscale x 8 x i16> %va, %splat
389  ret <vscale x 8 x i16> %vc
390}
391
392define <vscale x 8 x i16> @vsub_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
393; CHECK-LABEL: vsub_vx_nxv8i16_0:
394; CHECK:       # %bb.0:
395; CHECK-NEXT:    li a0, 1
396; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
397; CHECK-NEXT:    vsub.vx v8, v8, a0
398; CHECK-NEXT:    ret
399  %head = insertelement <vscale x 8 x i16> undef, i16 1, i32 0
400  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
401  %vc = sub <vscale x 8 x i16> %va, %splat
402  ret <vscale x 8 x i16> %vc
403}
404
405define <vscale x 16 x i16> @vsub_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
406; CHECK-LABEL: vsub_vv_nxv16i16:
407; CHECK:       # %bb.0:
408; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
409; CHECK-NEXT:    vsub.vv v8, v8, v12
410; CHECK-NEXT:    ret
411  %vc = sub <vscale x 16 x i16> %va, %vb
412  ret <vscale x 16 x i16> %vc
413}
414
415define <vscale x 16 x i16> @vsub_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
416; CHECK-LABEL: vsub_vx_nxv16i16:
417; CHECK:       # %bb.0:
418; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
419; CHECK-NEXT:    vsub.vx v8, v8, a0
420; CHECK-NEXT:    ret
421  %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
422  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
423  %vc = sub <vscale x 16 x i16> %va, %splat
424  ret <vscale x 16 x i16> %vc
425}
426
427define <vscale x 16 x i16> @vsub_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
428; CHECK-LABEL: vsub_vx_nxv16i16_0:
429; CHECK:       # %bb.0:
430; CHECK-NEXT:    li a0, 1
431; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
432; CHECK-NEXT:    vsub.vx v8, v8, a0
433; CHECK-NEXT:    ret
434  %head = insertelement <vscale x 16 x i16> undef, i16 1, i32 0
435  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
436  %vc = sub <vscale x 16 x i16> %va, %splat
437  ret <vscale x 16 x i16> %vc
438}
439
440define <vscale x 32 x i16> @vsub_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
441; CHECK-LABEL: vsub_vv_nxv32i16:
442; CHECK:       # %bb.0:
443; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
444; CHECK-NEXT:    vsub.vv v8, v8, v16
445; CHECK-NEXT:    ret
446  %vc = sub <vscale x 32 x i16> %va, %vb
447  ret <vscale x 32 x i16> %vc
448}
449
450define <vscale x 32 x i16> @vsub_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
451; CHECK-LABEL: vsub_vx_nxv32i16:
452; CHECK:       # %bb.0:
453; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
454; CHECK-NEXT:    vsub.vx v8, v8, a0
455; CHECK-NEXT:    ret
456  %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
457  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
458  %vc = sub <vscale x 32 x i16> %va, %splat
459  ret <vscale x 32 x i16> %vc
460}
461
462define <vscale x 32 x i16> @vsub_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
463; CHECK-LABEL: vsub_vx_nxv32i16_0:
464; CHECK:       # %bb.0:
465; CHECK-NEXT:    li a0, 1
466; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
467; CHECK-NEXT:    vsub.vx v8, v8, a0
468; CHECK-NEXT:    ret
469  %head = insertelement <vscale x 32 x i16> undef, i16 1, i32 0
470  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
471  %vc = sub <vscale x 32 x i16> %va, %splat
472  ret <vscale x 32 x i16> %vc
473}
474
475define <vscale x 1 x i32> @vsub_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
476; CHECK-LABEL: vsub_vv_nxv1i32:
477; CHECK:       # %bb.0:
478; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
479; CHECK-NEXT:    vsub.vv v8, v8, v9
480; CHECK-NEXT:    ret
481  %vc = sub <vscale x 1 x i32> %va, %vb
482  ret <vscale x 1 x i32> %vc
483}
484
485define <vscale x 1 x i32> @vsub_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
486; CHECK-LABEL: vsub_vx_nxv1i32:
487; CHECK:       # %bb.0:
488; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
489; CHECK-NEXT:    vsub.vx v8, v8, a0
490; CHECK-NEXT:    ret
491  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
492  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
493  %vc = sub <vscale x 1 x i32> %va, %splat
494  ret <vscale x 1 x i32> %vc
495}
496
497define <vscale x 1 x i32> @vsub_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
498; CHECK-LABEL: vsub_vx_nxv1i32_0:
499; CHECK:       # %bb.0:
500; CHECK-NEXT:    li a0, 1
501; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
502; CHECK-NEXT:    vsub.vx v8, v8, a0
503; CHECK-NEXT:    ret
504  %head = insertelement <vscale x 1 x i32> undef, i32 1, i32 0
505  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
506  %vc = sub <vscale x 1 x i32> %va, %splat
507  ret <vscale x 1 x i32> %vc
508}
509
510define <vscale x 2 x i32> @vsub_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
511; CHECK-LABEL: vsub_vv_nxv2i32:
512; CHECK:       # %bb.0:
513; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
514; CHECK-NEXT:    vsub.vv v8, v8, v9
515; CHECK-NEXT:    ret
516  %vc = sub <vscale x 2 x i32> %va, %vb
517  ret <vscale x 2 x i32> %vc
518}
519
520define <vscale x 2 x i32> @vsub_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
521; CHECK-LABEL: vsub_vx_nxv2i32:
522; CHECK:       # %bb.0:
523; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
524; CHECK-NEXT:    vsub.vx v8, v8, a0
525; CHECK-NEXT:    ret
526  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
527  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
528  %vc = sub <vscale x 2 x i32> %va, %splat
529  ret <vscale x 2 x i32> %vc
530}
531
532define <vscale x 2 x i32> @vsub_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
533; CHECK-LABEL: vsub_vx_nxv2i32_0:
534; CHECK:       # %bb.0:
535; CHECK-NEXT:    li a0, 1
536; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
537; CHECK-NEXT:    vsub.vx v8, v8, a0
538; CHECK-NEXT:    ret
539  %head = insertelement <vscale x 2 x i32> undef, i32 1, i32 0
540  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
541  %vc = sub <vscale x 2 x i32> %va, %splat
542  ret <vscale x 2 x i32> %vc
543}
544
545define <vscale x 4 x i32> @vsub_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
546; CHECK-LABEL: vsub_vv_nxv4i32:
547; CHECK:       # %bb.0:
548; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
549; CHECK-NEXT:    vsub.vv v8, v8, v10
550; CHECK-NEXT:    ret
551  %vc = sub <vscale x 4 x i32> %va, %vb
552  ret <vscale x 4 x i32> %vc
553}
554
555define <vscale x 4 x i32> @vsub_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
556; CHECK-LABEL: vsub_vx_nxv4i32:
557; CHECK:       # %bb.0:
558; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
559; CHECK-NEXT:    vsub.vx v8, v8, a0
560; CHECK-NEXT:    ret
561  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
562  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
563  %vc = sub <vscale x 4 x i32> %va, %splat
564  ret <vscale x 4 x i32> %vc
565}
566
567define <vscale x 4 x i32> @vsub_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
568; CHECK-LABEL: vsub_vx_nxv4i32_0:
569; CHECK:       # %bb.0:
570; CHECK-NEXT:    li a0, 1
571; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
572; CHECK-NEXT:    vsub.vx v8, v8, a0
573; CHECK-NEXT:    ret
574  %head = insertelement <vscale x 4 x i32> undef, i32 1, i32 0
575  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
576  %vc = sub <vscale x 4 x i32> %va, %splat
577  ret <vscale x 4 x i32> %vc
578}
579
580define <vscale x 8 x i32> @vsub_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
581; CHECK-LABEL: vsub_vv_nxv8i32:
582; CHECK:       # %bb.0:
583; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
584; CHECK-NEXT:    vsub.vv v8, v8, v12
585; CHECK-NEXT:    ret
586  %vc = sub <vscale x 8 x i32> %va, %vb
587  ret <vscale x 8 x i32> %vc
588}
589
590define <vscale x 8 x i32> @vsub_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
591; CHECK-LABEL: vsub_vx_nxv8i32:
592; CHECK:       # %bb.0:
593; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
594; CHECK-NEXT:    vsub.vx v8, v8, a0
595; CHECK-NEXT:    ret
596  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
597  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
598  %vc = sub <vscale x 8 x i32> %va, %splat
599  ret <vscale x 8 x i32> %vc
600}
601
602define <vscale x 8 x i32> @vsub_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
603; CHECK-LABEL: vsub_vx_nxv8i32_0:
604; CHECK:       # %bb.0:
605; CHECK-NEXT:    li a0, 1
606; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
607; CHECK-NEXT:    vsub.vx v8, v8, a0
608; CHECK-NEXT:    ret
609  %head = insertelement <vscale x 8 x i32> undef, i32 1, i32 0
610  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
611  %vc = sub <vscale x 8 x i32> %va, %splat
612  ret <vscale x 8 x i32> %vc
613}
614
615define <vscale x 16 x i32> @vsub_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
616; CHECK-LABEL: vsub_vv_nxv16i32:
617; CHECK:       # %bb.0:
618; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
619; CHECK-NEXT:    vsub.vv v8, v8, v16
620; CHECK-NEXT:    ret
621  %vc = sub <vscale x 16 x i32> %va, %vb
622  ret <vscale x 16 x i32> %vc
623}
624
625define <vscale x 16 x i32> @vsub_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
626; CHECK-LABEL: vsub_vx_nxv16i32:
627; CHECK:       # %bb.0:
628; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
629; CHECK-NEXT:    vsub.vx v8, v8, a0
630; CHECK-NEXT:    ret
631  %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
632  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
633  %vc = sub <vscale x 16 x i32> %va, %splat
634  ret <vscale x 16 x i32> %vc
635}
636
637define <vscale x 16 x i32> @vsub_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
638; CHECK-LABEL: vsub_vx_nxv16i32_0:
639; CHECK:       # %bb.0:
640; CHECK-NEXT:    li a0, 1
641; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
642; CHECK-NEXT:    vsub.vx v8, v8, a0
643; CHECK-NEXT:    ret
644  %head = insertelement <vscale x 16 x i32> undef, i32 1, i32 0
645  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
646  %vc = sub <vscale x 16 x i32> %va, %splat
647  ret <vscale x 16 x i32> %vc
648}
649
650define <vscale x 1 x i64> @vsub_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
651; CHECK-LABEL: vsub_vv_nxv1i64:
652; CHECK:       # %bb.0:
653; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
654; CHECK-NEXT:    vsub.vv v8, v8, v9
655; CHECK-NEXT:    ret
656  %vc = sub <vscale x 1 x i64> %va, %vb
657  ret <vscale x 1 x i64> %vc
658}
659
660define <vscale x 1 x i64> @vsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
661; RV32-LABEL: vsub_vx_nxv1i64:
662; RV32:       # %bb.0:
663; RV32-NEXT:    addi sp, sp, -16
664; RV32-NEXT:    .cfi_def_cfa_offset 16
665; RV32-NEXT:    sw a1, 12(sp)
666; RV32-NEXT:    sw a0, 8(sp)
667; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
668; RV32-NEXT:    addi a0, sp, 8
669; RV32-NEXT:    vlse64.v v9, (a0), zero
670; RV32-NEXT:    vsub.vv v8, v8, v9
671; RV32-NEXT:    addi sp, sp, 16
672; RV32-NEXT:    ret
673;
674; RV64-LABEL: vsub_vx_nxv1i64:
675; RV64:       # %bb.0:
676; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
677; RV64-NEXT:    vsub.vx v8, v8, a0
678; RV64-NEXT:    ret
679  %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
680  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
681  %vc = sub <vscale x 1 x i64> %va, %splat
682  ret <vscale x 1 x i64> %vc
683}
684
685define <vscale x 1 x i64> @vsub_vx_nxv1i64_0(<vscale x 1 x i64> %va) {
686; CHECK-LABEL: vsub_vx_nxv1i64_0:
687; CHECK:       # %bb.0:
688; CHECK-NEXT:    li a0, 1
689; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
690; CHECK-NEXT:    vsub.vx v8, v8, a0
691; CHECK-NEXT:    ret
692  %head = insertelement <vscale x 1 x i64> undef, i64 1, i32 0
693  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
694  %vc = sub <vscale x 1 x i64> %va, %splat
695  ret <vscale x 1 x i64> %vc
696}
697
698define <vscale x 2 x i64> @vsub_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
699; CHECK-LABEL: vsub_vv_nxv2i64:
700; CHECK:       # %bb.0:
701; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
702; CHECK-NEXT:    vsub.vv v8, v8, v10
703; CHECK-NEXT:    ret
704  %vc = sub <vscale x 2 x i64> %va, %vb
705  ret <vscale x 2 x i64> %vc
706}
707
708define <vscale x 2 x i64> @vsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
709; RV32-LABEL: vsub_vx_nxv2i64:
710; RV32:       # %bb.0:
711; RV32-NEXT:    addi sp, sp, -16
712; RV32-NEXT:    .cfi_def_cfa_offset 16
713; RV32-NEXT:    sw a1, 12(sp)
714; RV32-NEXT:    sw a0, 8(sp)
715; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
716; RV32-NEXT:    addi a0, sp, 8
717; RV32-NEXT:    vlse64.v v10, (a0), zero
718; RV32-NEXT:    vsub.vv v8, v8, v10
719; RV32-NEXT:    addi sp, sp, 16
720; RV32-NEXT:    ret
721;
722; RV64-LABEL: vsub_vx_nxv2i64:
723; RV64:       # %bb.0:
724; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
725; RV64-NEXT:    vsub.vx v8, v8, a0
726; RV64-NEXT:    ret
727  %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
728  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
729  %vc = sub <vscale x 2 x i64> %va, %splat
730  ret <vscale x 2 x i64> %vc
731}
732
733define <vscale x 2 x i64> @vsub_vx_nxv2i64_0(<vscale x 2 x i64> %va) {
734; CHECK-LABEL: vsub_vx_nxv2i64_0:
735; CHECK:       # %bb.0:
736; CHECK-NEXT:    li a0, 1
737; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
738; CHECK-NEXT:    vsub.vx v8, v8, a0
739; CHECK-NEXT:    ret
740  %head = insertelement <vscale x 2 x i64> undef, i64 1, i32 0
741  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
742  %vc = sub <vscale x 2 x i64> %va, %splat
743  ret <vscale x 2 x i64> %vc
744}
745
746define <vscale x 4 x i64> @vsub_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
747; CHECK-LABEL: vsub_vv_nxv4i64:
748; CHECK:       # %bb.0:
749; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
750; CHECK-NEXT:    vsub.vv v8, v8, v12
751; CHECK-NEXT:    ret
752  %vc = sub <vscale x 4 x i64> %va, %vb
753  ret <vscale x 4 x i64> %vc
754}
755
756define <vscale x 4 x i64> @vsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
757; RV32-LABEL: vsub_vx_nxv4i64:
758; RV32:       # %bb.0:
759; RV32-NEXT:    addi sp, sp, -16
760; RV32-NEXT:    .cfi_def_cfa_offset 16
761; RV32-NEXT:    sw a1, 12(sp)
762; RV32-NEXT:    sw a0, 8(sp)
763; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
764; RV32-NEXT:    addi a0, sp, 8
765; RV32-NEXT:    vlse64.v v12, (a0), zero
766; RV32-NEXT:    vsub.vv v8, v8, v12
767; RV32-NEXT:    addi sp, sp, 16
768; RV32-NEXT:    ret
769;
770; RV64-LABEL: vsub_vx_nxv4i64:
771; RV64:       # %bb.0:
772; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
773; RV64-NEXT:    vsub.vx v8, v8, a0
774; RV64-NEXT:    ret
775  %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
776  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
777  %vc = sub <vscale x 4 x i64> %va, %splat
778  ret <vscale x 4 x i64> %vc
779}
780
781define <vscale x 4 x i64> @vsub_vx_nxv4i64_0(<vscale x 4 x i64> %va) {
782; CHECK-LABEL: vsub_vx_nxv4i64_0:
783; CHECK:       # %bb.0:
784; CHECK-NEXT:    li a0, 1
785; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
786; CHECK-NEXT:    vsub.vx v8, v8, a0
787; CHECK-NEXT:    ret
788  %head = insertelement <vscale x 4 x i64> undef, i64 1, i32 0
789  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
790  %vc = sub <vscale x 4 x i64> %va, %splat
791  ret <vscale x 4 x i64> %vc
792}
793
794define <vscale x 8 x i64> @vsub_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
795; CHECK-LABEL: vsub_vv_nxv8i64:
796; CHECK:       # %bb.0:
797; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
798; CHECK-NEXT:    vsub.vv v8, v8, v16
799; CHECK-NEXT:    ret
800  %vc = sub <vscale x 8 x i64> %va, %vb
801  ret <vscale x 8 x i64> %vc
802}
803
804define <vscale x 8 x i64> @vsub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
805; RV32-LABEL: vsub_vx_nxv8i64:
806; RV32:       # %bb.0:
807; RV32-NEXT:    addi sp, sp, -16
808; RV32-NEXT:    .cfi_def_cfa_offset 16
809; RV32-NEXT:    sw a1, 12(sp)
810; RV32-NEXT:    sw a0, 8(sp)
811; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
812; RV32-NEXT:    addi a0, sp, 8
813; RV32-NEXT:    vlse64.v v16, (a0), zero
814; RV32-NEXT:    vsub.vv v8, v8, v16
815; RV32-NEXT:    addi sp, sp, 16
816; RV32-NEXT:    ret
817;
818; RV64-LABEL: vsub_vx_nxv8i64:
819; RV64:       # %bb.0:
820; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
821; RV64-NEXT:    vsub.vx v8, v8, a0
822; RV64-NEXT:    ret
823  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
824  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
825  %vc = sub <vscale x 8 x i64> %va, %splat
826  ret <vscale x 8 x i64> %vc
827}
828
829define <vscale x 8 x i64> @vsub_vx_nxv8i64_0(<vscale x 8 x i64> %va) {
830; CHECK-LABEL: vsub_vx_nxv8i64_0:
831; CHECK:       # %bb.0:
832; CHECK-NEXT:    li a0, 1
833; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
834; CHECK-NEXT:    vsub.vx v8, v8, a0
835; CHECK-NEXT:    ret
836  %head = insertelement <vscale x 8 x i64> undef, i64 1, i32 0
837  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
838  %vc = sub <vscale x 8 x i64> %va, %splat
839  ret <vscale x 8 x i64> %vc
840}
841
842