1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 3; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 4 5define <vscale x 1 x i8> @vrem_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) { 6; CHECK-LABEL: vrem_vv_nxv1i8: 7; CHECK: # %bb.0: 8; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu 9; CHECK-NEXT: vrem.vv v8, v8, v9 10; CHECK-NEXT: ret 11 %vc = srem <vscale x 1 x i8> %va, %vb 12 ret <vscale x 1 x i8> %vc 13} 14 15define <vscale x 1 x i8> @vrem_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) { 16; CHECK-LABEL: vrem_vx_nxv1i8: 17; CHECK: # %bb.0: 18; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu 19; CHECK-NEXT: vrem.vx v8, v8, a0 20; CHECK-NEXT: ret 21 %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0 22 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer 23 %vc = srem <vscale x 1 x i8> %va, %splat 24 ret <vscale x 1 x i8> %vc 25} 26 27define <vscale x 1 x i8> @vrem_vi_nxv1i8_0(<vscale x 1 x i8> %va) { 28; CHECK-LABEL: vrem_vi_nxv1i8_0: 29; CHECK: # %bb.0: 30; CHECK-NEXT: li a0, 109 31; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu 32; CHECK-NEXT: vmulh.vx v9, v8, a0 33; CHECK-NEXT: vsub.vv v9, v9, v8 34; CHECK-NEXT: vsra.vi v9, v9, 2 35; CHECK-NEXT: vsrl.vi v10, v9, 7 36; CHECK-NEXT: vadd.vv v9, v9, v10 37; CHECK-NEXT: li a0, -7 38; CHECK-NEXT: vnmsac.vx v8, a0, v9 39; CHECK-NEXT: ret 40 %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0 41 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer 42 %vc = srem <vscale x 1 x i8> %va, %splat 43 ret <vscale x 1 x i8> %vc 44} 45 46define <vscale x 2 x i8> @vrem_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) { 47; CHECK-LABEL: vrem_vv_nxv2i8: 48; CHECK: # %bb.0: 49; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu 50; CHECK-NEXT: vrem.vv v8, v8, v9 51; CHECK-NEXT: ret 52 %vc = srem <vscale x 2 x i8> %va, %vb 53 ret <vscale x 2 x i8> %vc 54} 55 56define <vscale x 2 x i8> @vrem_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) { 57; CHECK-LABEL: vrem_vx_nxv2i8: 58; CHECK: # %bb.0: 59; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu 60; CHECK-NEXT: vrem.vx v8, v8, a0 61; CHECK-NEXT: ret 62 %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0 63 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer 64 %vc = srem <vscale x 2 x i8> %va, %splat 65 ret <vscale x 2 x i8> %vc 66} 67 68define <vscale x 2 x i8> @vrem_vi_nxv2i8_0(<vscale x 2 x i8> %va) { 69; CHECK-LABEL: vrem_vi_nxv2i8_0: 70; CHECK: # %bb.0: 71; CHECK-NEXT: li a0, 109 72; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu 73; CHECK-NEXT: vmulh.vx v9, v8, a0 74; CHECK-NEXT: vsub.vv v9, v9, v8 75; CHECK-NEXT: vsra.vi v9, v9, 2 76; CHECK-NEXT: vsrl.vi v10, v9, 7 77; CHECK-NEXT: vadd.vv v9, v9, v10 78; CHECK-NEXT: li a0, -7 79; CHECK-NEXT: vnmsac.vx v8, a0, v9 80; CHECK-NEXT: ret 81 %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0 82 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer 83 %vc = srem <vscale x 2 x i8> %va, %splat 84 ret <vscale x 2 x i8> %vc 85} 86 87define <vscale x 4 x i8> @vrem_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) { 88; CHECK-LABEL: vrem_vv_nxv4i8: 89; CHECK: # %bb.0: 90; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu 91; CHECK-NEXT: vrem.vv v8, v8, v9 92; CHECK-NEXT: ret 93 %vc = srem <vscale x 4 x i8> %va, %vb 94 ret <vscale x 4 x i8> %vc 95} 96 97define <vscale x 4 x i8> @vrem_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) { 98; CHECK-LABEL: vrem_vx_nxv4i8: 99; CHECK: # %bb.0: 100; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu 101; CHECK-NEXT: vrem.vx v8, v8, a0 102; CHECK-NEXT: ret 103 %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0 104 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer 105 %vc = srem <vscale x 4 x i8> %va, %splat 106 ret <vscale x 4 x i8> %vc 107} 108 109define <vscale x 4 x i8> @vrem_vi_nxv4i8_0(<vscale x 4 x i8> %va) { 110; CHECK-LABEL: vrem_vi_nxv4i8_0: 111; CHECK: # %bb.0: 112; CHECK-NEXT: li a0, 109 113; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu 114; CHECK-NEXT: vmulh.vx v9, v8, a0 115; CHECK-NEXT: vsub.vv v9, v9, v8 116; CHECK-NEXT: vsra.vi v9, v9, 2 117; CHECK-NEXT: vsrl.vi v10, v9, 7 118; CHECK-NEXT: vadd.vv v9, v9, v10 119; CHECK-NEXT: li a0, -7 120; CHECK-NEXT: vnmsac.vx v8, a0, v9 121; CHECK-NEXT: ret 122 %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0 123 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer 124 %vc = srem <vscale x 4 x i8> %va, %splat 125 ret <vscale x 4 x i8> %vc 126} 127 128define <vscale x 8 x i8> @vrem_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { 129; CHECK-LABEL: vrem_vv_nxv8i8: 130; CHECK: # %bb.0: 131; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu 132; CHECK-NEXT: vrem.vv v8, v8, v9 133; CHECK-NEXT: ret 134 %vc = srem <vscale x 8 x i8> %va, %vb 135 ret <vscale x 8 x i8> %vc 136} 137 138define <vscale x 8 x i8> @vrem_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) { 139; CHECK-LABEL: vrem_vx_nxv8i8: 140; CHECK: # %bb.0: 141; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu 142; CHECK-NEXT: vrem.vx v8, v8, a0 143; CHECK-NEXT: ret 144 %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0 145 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer 146 %vc = srem <vscale x 8 x i8> %va, %splat 147 ret <vscale x 8 x i8> %vc 148} 149 150define <vscale x 8 x i8> @vrem_vi_nxv8i8_0(<vscale x 8 x i8> %va) { 151; CHECK-LABEL: vrem_vi_nxv8i8_0: 152; CHECK: # %bb.0: 153; CHECK-NEXT: li a0, 109 154; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu 155; CHECK-NEXT: vmulh.vx v9, v8, a0 156; CHECK-NEXT: vsub.vv v9, v9, v8 157; CHECK-NEXT: vsra.vi v9, v9, 2 158; CHECK-NEXT: vsrl.vi v10, v9, 7 159; CHECK-NEXT: vadd.vv v9, v9, v10 160; CHECK-NEXT: li a0, -7 161; CHECK-NEXT: vnmsac.vx v8, a0, v9 162; CHECK-NEXT: ret 163 %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0 164 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer 165 %vc = srem <vscale x 8 x i8> %va, %splat 166 ret <vscale x 8 x i8> %vc 167} 168 169define <vscale x 16 x i8> @vrem_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) { 170; CHECK-LABEL: vrem_vv_nxv16i8: 171; CHECK: # %bb.0: 172; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu 173; CHECK-NEXT: vrem.vv v8, v8, v10 174; CHECK-NEXT: ret 175 %vc = srem <vscale x 16 x i8> %va, %vb 176 ret <vscale x 16 x i8> %vc 177} 178 179define <vscale x 16 x i8> @vrem_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) { 180; CHECK-LABEL: vrem_vx_nxv16i8: 181; CHECK: # %bb.0: 182; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu 183; CHECK-NEXT: vrem.vx v8, v8, a0 184; CHECK-NEXT: ret 185 %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0 186 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer 187 %vc = srem <vscale x 16 x i8> %va, %splat 188 ret <vscale x 16 x i8> %vc 189} 190 191define <vscale x 16 x i8> @vrem_vi_nxv16i8_0(<vscale x 16 x i8> %va) { 192; CHECK-LABEL: vrem_vi_nxv16i8_0: 193; CHECK: # %bb.0: 194; CHECK-NEXT: li a0, 109 195; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu 196; CHECK-NEXT: vmulh.vx v10, v8, a0 197; CHECK-NEXT: vsub.vv v10, v10, v8 198; CHECK-NEXT: vsra.vi v10, v10, 2 199; CHECK-NEXT: vsrl.vi v12, v10, 7 200; CHECK-NEXT: vadd.vv v10, v10, v12 201; CHECK-NEXT: li a0, -7 202; CHECK-NEXT: vnmsac.vx v8, a0, v10 203; CHECK-NEXT: ret 204 %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0 205 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer 206 %vc = srem <vscale x 16 x i8> %va, %splat 207 ret <vscale x 16 x i8> %vc 208} 209 210define <vscale x 32 x i8> @vrem_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) { 211; CHECK-LABEL: vrem_vv_nxv32i8: 212; CHECK: # %bb.0: 213; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu 214; CHECK-NEXT: vrem.vv v8, v8, v12 215; CHECK-NEXT: ret 216 %vc = srem <vscale x 32 x i8> %va, %vb 217 ret <vscale x 32 x i8> %vc 218} 219 220define <vscale x 32 x i8> @vrem_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) { 221; CHECK-LABEL: vrem_vx_nxv32i8: 222; CHECK: # %bb.0: 223; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu 224; CHECK-NEXT: vrem.vx v8, v8, a0 225; CHECK-NEXT: ret 226 %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0 227 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer 228 %vc = srem <vscale x 32 x i8> %va, %splat 229 ret <vscale x 32 x i8> %vc 230} 231 232define <vscale x 32 x i8> @vrem_vi_nxv32i8_0(<vscale x 32 x i8> %va) { 233; CHECK-LABEL: vrem_vi_nxv32i8_0: 234; CHECK: # %bb.0: 235; CHECK-NEXT: li a0, 109 236; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu 237; CHECK-NEXT: vmulh.vx v12, v8, a0 238; CHECK-NEXT: vsub.vv v12, v12, v8 239; CHECK-NEXT: vsra.vi v12, v12, 2 240; CHECK-NEXT: vsrl.vi v16, v12, 7 241; CHECK-NEXT: vadd.vv v12, v12, v16 242; CHECK-NEXT: li a0, -7 243; CHECK-NEXT: vnmsac.vx v8, a0, v12 244; CHECK-NEXT: ret 245 %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0 246 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer 247 %vc = srem <vscale x 32 x i8> %va, %splat 248 ret <vscale x 32 x i8> %vc 249} 250 251define <vscale x 64 x i8> @vrem_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) { 252; CHECK-LABEL: vrem_vv_nxv64i8: 253; CHECK: # %bb.0: 254; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu 255; CHECK-NEXT: vrem.vv v8, v8, v16 256; CHECK-NEXT: ret 257 %vc = srem <vscale x 64 x i8> %va, %vb 258 ret <vscale x 64 x i8> %vc 259} 260 261define <vscale x 64 x i8> @vrem_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) { 262; CHECK-LABEL: vrem_vx_nxv64i8: 263; CHECK: # %bb.0: 264; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu 265; CHECK-NEXT: vrem.vx v8, v8, a0 266; CHECK-NEXT: ret 267 %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0 268 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer 269 %vc = srem <vscale x 64 x i8> %va, %splat 270 ret <vscale x 64 x i8> %vc 271} 272 273define <vscale x 64 x i8> @vrem_vi_nxv64i8_0(<vscale x 64 x i8> %va) { 274; CHECK-LABEL: vrem_vi_nxv64i8_0: 275; CHECK: # %bb.0: 276; CHECK-NEXT: li a0, 109 277; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu 278; CHECK-NEXT: vmulh.vx v16, v8, a0 279; CHECK-NEXT: vsub.vv v16, v16, v8 280; CHECK-NEXT: vsra.vi v16, v16, 2 281; CHECK-NEXT: vsrl.vi v24, v16, 7 282; CHECK-NEXT: vadd.vv v16, v16, v24 283; CHECK-NEXT: li a0, -7 284; CHECK-NEXT: vnmsac.vx v8, a0, v16 285; CHECK-NEXT: ret 286 %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0 287 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer 288 %vc = srem <vscale x 64 x i8> %va, %splat 289 ret <vscale x 64 x i8> %vc 290} 291 292define <vscale x 1 x i16> @vrem_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) { 293; CHECK-LABEL: vrem_vv_nxv1i16: 294; CHECK: # %bb.0: 295; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu 296; CHECK-NEXT: vrem.vv v8, v8, v9 297; CHECK-NEXT: ret 298 %vc = srem <vscale x 1 x i16> %va, %vb 299 ret <vscale x 1 x i16> %vc 300} 301 302define <vscale x 1 x i16> @vrem_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) { 303; CHECK-LABEL: vrem_vx_nxv1i16: 304; CHECK: # %bb.0: 305; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu 306; CHECK-NEXT: vrem.vx v8, v8, a0 307; CHECK-NEXT: ret 308 %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0 309 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer 310 %vc = srem <vscale x 1 x i16> %va, %splat 311 ret <vscale x 1 x i16> %vc 312} 313 314define <vscale x 1 x i16> @vrem_vi_nxv1i16_0(<vscale x 1 x i16> %va) { 315; RV32-LABEL: vrem_vi_nxv1i16_0: 316; RV32: # %bb.0: 317; RV32-NEXT: lui a0, 1048571 318; RV32-NEXT: addi a0, a0, 1755 319; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, mu 320; RV32-NEXT: vmulh.vx v9, v8, a0 321; RV32-NEXT: vsra.vi v9, v9, 1 322; RV32-NEXT: vsrl.vi v10, v9, 15 323; RV32-NEXT: vadd.vv v9, v9, v10 324; RV32-NEXT: li a0, -7 325; RV32-NEXT: vnmsac.vx v8, a0, v9 326; RV32-NEXT: ret 327; 328; RV64-LABEL: vrem_vi_nxv1i16_0: 329; RV64: # %bb.0: 330; RV64-NEXT: lui a0, 1048571 331; RV64-NEXT: addiw a0, a0, 1755 332; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, mu 333; RV64-NEXT: vmulh.vx v9, v8, a0 334; RV64-NEXT: vsra.vi v9, v9, 1 335; RV64-NEXT: vsrl.vi v10, v9, 15 336; RV64-NEXT: vadd.vv v9, v9, v10 337; RV64-NEXT: li a0, -7 338; RV64-NEXT: vnmsac.vx v8, a0, v9 339; RV64-NEXT: ret 340 %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0 341 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer 342 %vc = srem <vscale x 1 x i16> %va, %splat 343 ret <vscale x 1 x i16> %vc 344} 345 346define <vscale x 2 x i16> @vrem_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) { 347; CHECK-LABEL: vrem_vv_nxv2i16: 348; CHECK: # %bb.0: 349; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu 350; CHECK-NEXT: vrem.vv v8, v8, v9 351; CHECK-NEXT: ret 352 %vc = srem <vscale x 2 x i16> %va, %vb 353 ret <vscale x 2 x i16> %vc 354} 355 356define <vscale x 2 x i16> @vrem_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) { 357; CHECK-LABEL: vrem_vx_nxv2i16: 358; CHECK: # %bb.0: 359; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu 360; CHECK-NEXT: vrem.vx v8, v8, a0 361; CHECK-NEXT: ret 362 %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0 363 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer 364 %vc = srem <vscale x 2 x i16> %va, %splat 365 ret <vscale x 2 x i16> %vc 366} 367 368define <vscale x 2 x i16> @vrem_vi_nxv2i16_0(<vscale x 2 x i16> %va) { 369; RV32-LABEL: vrem_vi_nxv2i16_0: 370; RV32: # %bb.0: 371; RV32-NEXT: lui a0, 1048571 372; RV32-NEXT: addi a0, a0, 1755 373; RV32-NEXT: vsetvli a1, zero, e16, mf2, ta, mu 374; RV32-NEXT: vmulh.vx v9, v8, a0 375; RV32-NEXT: vsra.vi v9, v9, 1 376; RV32-NEXT: vsrl.vi v10, v9, 15 377; RV32-NEXT: vadd.vv v9, v9, v10 378; RV32-NEXT: li a0, -7 379; RV32-NEXT: vnmsac.vx v8, a0, v9 380; RV32-NEXT: ret 381; 382; RV64-LABEL: vrem_vi_nxv2i16_0: 383; RV64: # %bb.0: 384; RV64-NEXT: lui a0, 1048571 385; RV64-NEXT: addiw a0, a0, 1755 386; RV64-NEXT: vsetvli a1, zero, e16, mf2, ta, mu 387; RV64-NEXT: vmulh.vx v9, v8, a0 388; RV64-NEXT: vsra.vi v9, v9, 1 389; RV64-NEXT: vsrl.vi v10, v9, 15 390; RV64-NEXT: vadd.vv v9, v9, v10 391; RV64-NEXT: li a0, -7 392; RV64-NEXT: vnmsac.vx v8, a0, v9 393; RV64-NEXT: ret 394 %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0 395 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer 396 %vc = srem <vscale x 2 x i16> %va, %splat 397 ret <vscale x 2 x i16> %vc 398} 399 400define <vscale x 4 x i16> @vrem_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) { 401; CHECK-LABEL: vrem_vv_nxv4i16: 402; CHECK: # %bb.0: 403; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu 404; CHECK-NEXT: vrem.vv v8, v8, v9 405; CHECK-NEXT: ret 406 %vc = srem <vscale x 4 x i16> %va, %vb 407 ret <vscale x 4 x i16> %vc 408} 409 410define <vscale x 4 x i16> @vrem_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) { 411; CHECK-LABEL: vrem_vx_nxv4i16: 412; CHECK: # %bb.0: 413; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu 414; CHECK-NEXT: vrem.vx v8, v8, a0 415; CHECK-NEXT: ret 416 %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0 417 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer 418 %vc = srem <vscale x 4 x i16> %va, %splat 419 ret <vscale x 4 x i16> %vc 420} 421 422define <vscale x 4 x i16> @vrem_vi_nxv4i16_0(<vscale x 4 x i16> %va) { 423; RV32-LABEL: vrem_vi_nxv4i16_0: 424; RV32: # %bb.0: 425; RV32-NEXT: lui a0, 1048571 426; RV32-NEXT: addi a0, a0, 1755 427; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, mu 428; RV32-NEXT: vmulh.vx v9, v8, a0 429; RV32-NEXT: vsra.vi v9, v9, 1 430; RV32-NEXT: vsrl.vi v10, v9, 15 431; RV32-NEXT: vadd.vv v9, v9, v10 432; RV32-NEXT: li a0, -7 433; RV32-NEXT: vnmsac.vx v8, a0, v9 434; RV32-NEXT: ret 435; 436; RV64-LABEL: vrem_vi_nxv4i16_0: 437; RV64: # %bb.0: 438; RV64-NEXT: lui a0, 1048571 439; RV64-NEXT: addiw a0, a0, 1755 440; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, mu 441; RV64-NEXT: vmulh.vx v9, v8, a0 442; RV64-NEXT: vsra.vi v9, v9, 1 443; RV64-NEXT: vsrl.vi v10, v9, 15 444; RV64-NEXT: vadd.vv v9, v9, v10 445; RV64-NEXT: li a0, -7 446; RV64-NEXT: vnmsac.vx v8, a0, v9 447; RV64-NEXT: ret 448 %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0 449 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer 450 %vc = srem <vscale x 4 x i16> %va, %splat 451 ret <vscale x 4 x i16> %vc 452} 453 454define <vscale x 8 x i16> @vrem_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { 455; CHECK-LABEL: vrem_vv_nxv8i16: 456; CHECK: # %bb.0: 457; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu 458; CHECK-NEXT: vrem.vv v8, v8, v10 459; CHECK-NEXT: ret 460 %vc = srem <vscale x 8 x i16> %va, %vb 461 ret <vscale x 8 x i16> %vc 462} 463 464define <vscale x 8 x i16> @vrem_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) { 465; CHECK-LABEL: vrem_vx_nxv8i16: 466; CHECK: # %bb.0: 467; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu 468; CHECK-NEXT: vrem.vx v8, v8, a0 469; CHECK-NEXT: ret 470 %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0 471 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 472 %vc = srem <vscale x 8 x i16> %va, %splat 473 ret <vscale x 8 x i16> %vc 474} 475 476define <vscale x 8 x i16> @vrem_vi_nxv8i16_0(<vscale x 8 x i16> %va) { 477; RV32-LABEL: vrem_vi_nxv8i16_0: 478; RV32: # %bb.0: 479; RV32-NEXT: lui a0, 1048571 480; RV32-NEXT: addi a0, a0, 1755 481; RV32-NEXT: vsetvli a1, zero, e16, m2, ta, mu 482; RV32-NEXT: vmulh.vx v10, v8, a0 483; RV32-NEXT: vsra.vi v10, v10, 1 484; RV32-NEXT: vsrl.vi v12, v10, 15 485; RV32-NEXT: vadd.vv v10, v10, v12 486; RV32-NEXT: li a0, -7 487; RV32-NEXT: vnmsac.vx v8, a0, v10 488; RV32-NEXT: ret 489; 490; RV64-LABEL: vrem_vi_nxv8i16_0: 491; RV64: # %bb.0: 492; RV64-NEXT: lui a0, 1048571 493; RV64-NEXT: addiw a0, a0, 1755 494; RV64-NEXT: vsetvli a1, zero, e16, m2, ta, mu 495; RV64-NEXT: vmulh.vx v10, v8, a0 496; RV64-NEXT: vsra.vi v10, v10, 1 497; RV64-NEXT: vsrl.vi v12, v10, 15 498; RV64-NEXT: vadd.vv v10, v10, v12 499; RV64-NEXT: li a0, -7 500; RV64-NEXT: vnmsac.vx v8, a0, v10 501; RV64-NEXT: ret 502 %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0 503 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer 504 %vc = srem <vscale x 8 x i16> %va, %splat 505 ret <vscale x 8 x i16> %vc 506} 507 508define <vscale x 16 x i16> @vrem_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) { 509; CHECK-LABEL: vrem_vv_nxv16i16: 510; CHECK: # %bb.0: 511; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu 512; CHECK-NEXT: vrem.vv v8, v8, v12 513; CHECK-NEXT: ret 514 %vc = srem <vscale x 16 x i16> %va, %vb 515 ret <vscale x 16 x i16> %vc 516} 517 518define <vscale x 16 x i16> @vrem_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) { 519; CHECK-LABEL: vrem_vx_nxv16i16: 520; CHECK: # %bb.0: 521; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu 522; CHECK-NEXT: vrem.vx v8, v8, a0 523; CHECK-NEXT: ret 524 %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0 525 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer 526 %vc = srem <vscale x 16 x i16> %va, %splat 527 ret <vscale x 16 x i16> %vc 528} 529 530define <vscale x 16 x i16> @vrem_vi_nxv16i16_0(<vscale x 16 x i16> %va) { 531; RV32-LABEL: vrem_vi_nxv16i16_0: 532; RV32: # %bb.0: 533; RV32-NEXT: lui a0, 1048571 534; RV32-NEXT: addi a0, a0, 1755 535; RV32-NEXT: vsetvli a1, zero, e16, m4, ta, mu 536; RV32-NEXT: vmulh.vx v12, v8, a0 537; RV32-NEXT: vsra.vi v12, v12, 1 538; RV32-NEXT: vsrl.vi v16, v12, 15 539; RV32-NEXT: vadd.vv v12, v12, v16 540; RV32-NEXT: li a0, -7 541; RV32-NEXT: vnmsac.vx v8, a0, v12 542; RV32-NEXT: ret 543; 544; RV64-LABEL: vrem_vi_nxv16i16_0: 545; RV64: # %bb.0: 546; RV64-NEXT: lui a0, 1048571 547; RV64-NEXT: addiw a0, a0, 1755 548; RV64-NEXT: vsetvli a1, zero, e16, m4, ta, mu 549; RV64-NEXT: vmulh.vx v12, v8, a0 550; RV64-NEXT: vsra.vi v12, v12, 1 551; RV64-NEXT: vsrl.vi v16, v12, 15 552; RV64-NEXT: vadd.vv v12, v12, v16 553; RV64-NEXT: li a0, -7 554; RV64-NEXT: vnmsac.vx v8, a0, v12 555; RV64-NEXT: ret 556 %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0 557 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer 558 %vc = srem <vscale x 16 x i16> %va, %splat 559 ret <vscale x 16 x i16> %vc 560} 561 562define <vscale x 32 x i16> @vrem_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) { 563; CHECK-LABEL: vrem_vv_nxv32i16: 564; CHECK: # %bb.0: 565; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu 566; CHECK-NEXT: vrem.vv v8, v8, v16 567; CHECK-NEXT: ret 568 %vc = srem <vscale x 32 x i16> %va, %vb 569 ret <vscale x 32 x i16> %vc 570} 571 572define <vscale x 32 x i16> @vrem_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) { 573; CHECK-LABEL: vrem_vx_nxv32i16: 574; CHECK: # %bb.0: 575; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu 576; CHECK-NEXT: vrem.vx v8, v8, a0 577; CHECK-NEXT: ret 578 %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0 579 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer 580 %vc = srem <vscale x 32 x i16> %va, %splat 581 ret <vscale x 32 x i16> %vc 582} 583 584define <vscale x 32 x i16> @vrem_vi_nxv32i16_0(<vscale x 32 x i16> %va) { 585; RV32-LABEL: vrem_vi_nxv32i16_0: 586; RV32: # %bb.0: 587; RV32-NEXT: lui a0, 1048571 588; RV32-NEXT: addi a0, a0, 1755 589; RV32-NEXT: vsetvli a1, zero, e16, m8, ta, mu 590; RV32-NEXT: vmulh.vx v16, v8, a0 591; RV32-NEXT: vsra.vi v16, v16, 1 592; RV32-NEXT: vsrl.vi v24, v16, 15 593; RV32-NEXT: vadd.vv v16, v16, v24 594; RV32-NEXT: li a0, -7 595; RV32-NEXT: vnmsac.vx v8, a0, v16 596; RV32-NEXT: ret 597; 598; RV64-LABEL: vrem_vi_nxv32i16_0: 599; RV64: # %bb.0: 600; RV64-NEXT: lui a0, 1048571 601; RV64-NEXT: addiw a0, a0, 1755 602; RV64-NEXT: vsetvli a1, zero, e16, m8, ta, mu 603; RV64-NEXT: vmulh.vx v16, v8, a0 604; RV64-NEXT: vsra.vi v16, v16, 1 605; RV64-NEXT: vsrl.vi v24, v16, 15 606; RV64-NEXT: vadd.vv v16, v16, v24 607; RV64-NEXT: li a0, -7 608; RV64-NEXT: vnmsac.vx v8, a0, v16 609; RV64-NEXT: ret 610 %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0 611 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer 612 %vc = srem <vscale x 32 x i16> %va, %splat 613 ret <vscale x 32 x i16> %vc 614} 615 616define <vscale x 1 x i32> @vrem_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) { 617; CHECK-LABEL: vrem_vv_nxv1i32: 618; CHECK: # %bb.0: 619; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu 620; CHECK-NEXT: vrem.vv v8, v8, v9 621; CHECK-NEXT: ret 622 %vc = srem <vscale x 1 x i32> %va, %vb 623 ret <vscale x 1 x i32> %vc 624} 625 626define <vscale x 1 x i32> @vrem_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) { 627; CHECK-LABEL: vrem_vx_nxv1i32: 628; CHECK: # %bb.0: 629; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu 630; CHECK-NEXT: vrem.vx v8, v8, a0 631; CHECK-NEXT: ret 632 %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0 633 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer 634 %vc = srem <vscale x 1 x i32> %va, %splat 635 ret <vscale x 1 x i32> %vc 636} 637 638define <vscale x 1 x i32> @vrem_vi_nxv1i32_0(<vscale x 1 x i32> %va) { 639; RV32-LABEL: vrem_vi_nxv1i32_0: 640; RV32: # %bb.0: 641; RV32-NEXT: lui a0, 449390 642; RV32-NEXT: addi a0, a0, -1171 643; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, mu 644; RV32-NEXT: vmulh.vx v9, v8, a0 645; RV32-NEXT: vsub.vv v9, v9, v8 646; RV32-NEXT: vsrl.vi v10, v9, 31 647; RV32-NEXT: vsra.vi v9, v9, 2 648; RV32-NEXT: vadd.vv v9, v9, v10 649; RV32-NEXT: li a0, -7 650; RV32-NEXT: vnmsac.vx v8, a0, v9 651; RV32-NEXT: ret 652; 653; RV64-LABEL: vrem_vi_nxv1i32_0: 654; RV64: # %bb.0: 655; RV64-NEXT: lui a0, 449390 656; RV64-NEXT: addiw a0, a0, -1171 657; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, mu 658; RV64-NEXT: vmulh.vx v9, v8, a0 659; RV64-NEXT: vsub.vv v9, v9, v8 660; RV64-NEXT: vsra.vi v9, v9, 2 661; RV64-NEXT: vsrl.vi v10, v9, 31 662; RV64-NEXT: vadd.vv v9, v9, v10 663; RV64-NEXT: li a0, -7 664; RV64-NEXT: vnmsac.vx v8, a0, v9 665; RV64-NEXT: ret 666 %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0 667 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer 668 %vc = srem <vscale x 1 x i32> %va, %splat 669 ret <vscale x 1 x i32> %vc 670} 671 672define <vscale x 2 x i32> @vrem_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) { 673; CHECK-LABEL: vrem_vv_nxv2i32: 674; CHECK: # %bb.0: 675; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu 676; CHECK-NEXT: vrem.vv v8, v8, v9 677; CHECK-NEXT: ret 678 %vc = srem <vscale x 2 x i32> %va, %vb 679 ret <vscale x 2 x i32> %vc 680} 681 682define <vscale x 2 x i32> @vrem_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) { 683; CHECK-LABEL: vrem_vx_nxv2i32: 684; CHECK: # %bb.0: 685; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu 686; CHECK-NEXT: vrem.vx v8, v8, a0 687; CHECK-NEXT: ret 688 %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0 689 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer 690 %vc = srem <vscale x 2 x i32> %va, %splat 691 ret <vscale x 2 x i32> %vc 692} 693 694define <vscale x 2 x i32> @vrem_vi_nxv2i32_0(<vscale x 2 x i32> %va) { 695; RV32-LABEL: vrem_vi_nxv2i32_0: 696; RV32: # %bb.0: 697; RV32-NEXT: lui a0, 449390 698; RV32-NEXT: addi a0, a0, -1171 699; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, mu 700; RV32-NEXT: vmulh.vx v9, v8, a0 701; RV32-NEXT: vsub.vv v9, v9, v8 702; RV32-NEXT: vsrl.vi v10, v9, 31 703; RV32-NEXT: vsra.vi v9, v9, 2 704; RV32-NEXT: vadd.vv v9, v9, v10 705; RV32-NEXT: li a0, -7 706; RV32-NEXT: vnmsac.vx v8, a0, v9 707; RV32-NEXT: ret 708; 709; RV64-LABEL: vrem_vi_nxv2i32_0: 710; RV64: # %bb.0: 711; RV64-NEXT: lui a0, 449390 712; RV64-NEXT: addiw a0, a0, -1171 713; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, mu 714; RV64-NEXT: vmulh.vx v9, v8, a0 715; RV64-NEXT: vsub.vv v9, v9, v8 716; RV64-NEXT: vsra.vi v9, v9, 2 717; RV64-NEXT: vsrl.vi v10, v9, 31 718; RV64-NEXT: vadd.vv v9, v9, v10 719; RV64-NEXT: li a0, -7 720; RV64-NEXT: vnmsac.vx v8, a0, v9 721; RV64-NEXT: ret 722 %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0 723 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer 724 %vc = srem <vscale x 2 x i32> %va, %splat 725 ret <vscale x 2 x i32> %vc 726} 727 728define <vscale x 4 x i32> @vrem_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) { 729; CHECK-LABEL: vrem_vv_nxv4i32: 730; CHECK: # %bb.0: 731; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu 732; CHECK-NEXT: vrem.vv v8, v8, v10 733; CHECK-NEXT: ret 734 %vc = srem <vscale x 4 x i32> %va, %vb 735 ret <vscale x 4 x i32> %vc 736} 737 738define <vscale x 4 x i32> @vrem_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) { 739; CHECK-LABEL: vrem_vx_nxv4i32: 740; CHECK: # %bb.0: 741; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu 742; CHECK-NEXT: vrem.vx v8, v8, a0 743; CHECK-NEXT: ret 744 %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0 745 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 746 %vc = srem <vscale x 4 x i32> %va, %splat 747 ret <vscale x 4 x i32> %vc 748} 749 750define <vscale x 4 x i32> @vrem_vi_nxv4i32_0(<vscale x 4 x i32> %va) { 751; RV32-LABEL: vrem_vi_nxv4i32_0: 752; RV32: # %bb.0: 753; RV32-NEXT: lui a0, 449390 754; RV32-NEXT: addi a0, a0, -1171 755; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, mu 756; RV32-NEXT: vmulh.vx v10, v8, a0 757; RV32-NEXT: vsub.vv v10, v10, v8 758; RV32-NEXT: vsrl.vi v12, v10, 31 759; RV32-NEXT: vsra.vi v10, v10, 2 760; RV32-NEXT: vadd.vv v10, v10, v12 761; RV32-NEXT: li a0, -7 762; RV32-NEXT: vnmsac.vx v8, a0, v10 763; RV32-NEXT: ret 764; 765; RV64-LABEL: vrem_vi_nxv4i32_0: 766; RV64: # %bb.0: 767; RV64-NEXT: lui a0, 449390 768; RV64-NEXT: addiw a0, a0, -1171 769; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, mu 770; RV64-NEXT: vmulh.vx v10, v8, a0 771; RV64-NEXT: vsub.vv v10, v10, v8 772; RV64-NEXT: vsra.vi v10, v10, 2 773; RV64-NEXT: vsrl.vi v12, v10, 31 774; RV64-NEXT: vadd.vv v10, v10, v12 775; RV64-NEXT: li a0, -7 776; RV64-NEXT: vnmsac.vx v8, a0, v10 777; RV64-NEXT: ret 778 %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0 779 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer 780 %vc = srem <vscale x 4 x i32> %va, %splat 781 ret <vscale x 4 x i32> %vc 782} 783 784define <vscale x 8 x i32> @vrem_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { 785; CHECK-LABEL: vrem_vv_nxv8i32: 786; CHECK: # %bb.0: 787; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu 788; CHECK-NEXT: vrem.vv v8, v8, v12 789; CHECK-NEXT: ret 790 %vc = srem <vscale x 8 x i32> %va, %vb 791 ret <vscale x 8 x i32> %vc 792} 793 794define <vscale x 8 x i32> @vrem_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) { 795; CHECK-LABEL: vrem_vx_nxv8i32: 796; CHECK: # %bb.0: 797; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu 798; CHECK-NEXT: vrem.vx v8, v8, a0 799; CHECK-NEXT: ret 800 %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0 801 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer 802 %vc = srem <vscale x 8 x i32> %va, %splat 803 ret <vscale x 8 x i32> %vc 804} 805 806define <vscale x 8 x i32> @vrem_vi_nxv8i32_0(<vscale x 8 x i32> %va) { 807; RV32-LABEL: vrem_vi_nxv8i32_0: 808; RV32: # %bb.0: 809; RV32-NEXT: lui a0, 449390 810; RV32-NEXT: addi a0, a0, -1171 811; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu 812; RV32-NEXT: vmulh.vx v12, v8, a0 813; RV32-NEXT: vsub.vv v12, v12, v8 814; RV32-NEXT: vsrl.vi v16, v12, 31 815; RV32-NEXT: vsra.vi v12, v12, 2 816; RV32-NEXT: vadd.vv v12, v12, v16 817; RV32-NEXT: li a0, -7 818; RV32-NEXT: vnmsac.vx v8, a0, v12 819; RV32-NEXT: ret 820; 821; RV64-LABEL: vrem_vi_nxv8i32_0: 822; RV64: # %bb.0: 823; RV64-NEXT: lui a0, 449390 824; RV64-NEXT: addiw a0, a0, -1171 825; RV64-NEXT: vsetvli a1, zero, e32, m4, ta, mu 826; RV64-NEXT: vmulh.vx v12, v8, a0 827; RV64-NEXT: vsub.vv v12, v12, v8 828; RV64-NEXT: vsra.vi v12, v12, 2 829; RV64-NEXT: vsrl.vi v16, v12, 31 830; RV64-NEXT: vadd.vv v12, v12, v16 831; RV64-NEXT: li a0, -7 832; RV64-NEXT: vnmsac.vx v8, a0, v12 833; RV64-NEXT: ret 834 %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0 835 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer 836 %vc = srem <vscale x 8 x i32> %va, %splat 837 ret <vscale x 8 x i32> %vc 838} 839 840define <vscale x 16 x i32> @vrem_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) { 841; CHECK-LABEL: vrem_vv_nxv16i32: 842; CHECK: # %bb.0: 843; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu 844; CHECK-NEXT: vrem.vv v8, v8, v16 845; CHECK-NEXT: ret 846 %vc = srem <vscale x 16 x i32> %va, %vb 847 ret <vscale x 16 x i32> %vc 848} 849 850define <vscale x 16 x i32> @vrem_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) { 851; CHECK-LABEL: vrem_vx_nxv16i32: 852; CHECK: # %bb.0: 853; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu 854; CHECK-NEXT: vrem.vx v8, v8, a0 855; CHECK-NEXT: ret 856 %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0 857 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer 858 %vc = srem <vscale x 16 x i32> %va, %splat 859 ret <vscale x 16 x i32> %vc 860} 861 862define <vscale x 16 x i32> @vrem_vi_nxv16i32_0(<vscale x 16 x i32> %va) { 863; RV32-LABEL: vrem_vi_nxv16i32_0: 864; RV32: # %bb.0: 865; RV32-NEXT: lui a0, 449390 866; RV32-NEXT: addi a0, a0, -1171 867; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, mu 868; RV32-NEXT: vmulh.vx v16, v8, a0 869; RV32-NEXT: vsub.vv v16, v16, v8 870; RV32-NEXT: vsrl.vi v24, v16, 31 871; RV32-NEXT: vsra.vi v16, v16, 2 872; RV32-NEXT: vadd.vv v16, v16, v24 873; RV32-NEXT: li a0, -7 874; RV32-NEXT: vnmsac.vx v8, a0, v16 875; RV32-NEXT: ret 876; 877; RV64-LABEL: vrem_vi_nxv16i32_0: 878; RV64: # %bb.0: 879; RV64-NEXT: lui a0, 449390 880; RV64-NEXT: addiw a0, a0, -1171 881; RV64-NEXT: vsetvli a1, zero, e32, m8, ta, mu 882; RV64-NEXT: vmulh.vx v16, v8, a0 883; RV64-NEXT: vsub.vv v16, v16, v8 884; RV64-NEXT: vsra.vi v16, v16, 2 885; RV64-NEXT: vsrl.vi v24, v16, 31 886; RV64-NEXT: vadd.vv v16, v16, v24 887; RV64-NEXT: li a0, -7 888; RV64-NEXT: vnmsac.vx v8, a0, v16 889; RV64-NEXT: ret 890 %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0 891 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer 892 %vc = srem <vscale x 16 x i32> %va, %splat 893 ret <vscale x 16 x i32> %vc 894} 895 896define <vscale x 1 x i64> @vrem_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) { 897; CHECK-LABEL: vrem_vv_nxv1i64: 898; CHECK: # %bb.0: 899; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu 900; CHECK-NEXT: vrem.vv v8, v8, v9 901; CHECK-NEXT: ret 902 %vc = srem <vscale x 1 x i64> %va, %vb 903 ret <vscale x 1 x i64> %vc 904} 905 906define <vscale x 1 x i64> @vrem_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) { 907; RV32-LABEL: vrem_vx_nxv1i64: 908; RV32: # %bb.0: 909; RV32-NEXT: addi sp, sp, -16 910; RV32-NEXT: .cfi_def_cfa_offset 16 911; RV32-NEXT: sw a1, 12(sp) 912; RV32-NEXT: sw a0, 8(sp) 913; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu 914; RV32-NEXT: addi a0, sp, 8 915; RV32-NEXT: vlse64.v v9, (a0), zero 916; RV32-NEXT: vrem.vv v8, v8, v9 917; RV32-NEXT: addi sp, sp, 16 918; RV32-NEXT: ret 919; 920; RV64-LABEL: vrem_vx_nxv1i64: 921; RV64: # %bb.0: 922; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu 923; RV64-NEXT: vrem.vx v8, v8, a0 924; RV64-NEXT: ret 925 %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0 926 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer 927 %vc = srem <vscale x 1 x i64> %va, %splat 928 ret <vscale x 1 x i64> %vc 929} 930 931define <vscale x 1 x i64> @vrem_vi_nxv1i64_0(<vscale x 1 x i64> %va) { 932; RV32-LABEL: vrem_vi_nxv1i64_0: 933; RV32: # %bb.0: 934; RV32-NEXT: addi sp, sp, -16 935; RV32-NEXT: .cfi_def_cfa_offset 16 936; RV32-NEXT: lui a0, 748983 937; RV32-NEXT: addi a0, a0, -586 938; RV32-NEXT: sw a0, 12(sp) 939; RV32-NEXT: lui a0, 898779 940; RV32-NEXT: addi a0, a0, 1755 941; RV32-NEXT: sw a0, 8(sp) 942; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu 943; RV32-NEXT: addi a0, sp, 8 944; RV32-NEXT: vlse64.v v9, (a0), zero 945; RV32-NEXT: vmulh.vv v9, v8, v9 946; RV32-NEXT: li a0, 63 947; RV32-NEXT: vsrl.vx v10, v9, a0 948; RV32-NEXT: vsra.vi v9, v9, 1 949; RV32-NEXT: vadd.vv v9, v9, v10 950; RV32-NEXT: li a0, -7 951; RV32-NEXT: vnmsac.vx v8, a0, v9 952; RV32-NEXT: addi sp, sp, 16 953; RV32-NEXT: ret 954; 955; RV64-LABEL: vrem_vi_nxv1i64_0: 956; RV64: # %bb.0: 957; RV64-NEXT: lui a0, %hi(.LCPI56_0) 958; RV64-NEXT: ld a0, %lo(.LCPI56_0)(a0) 959; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, mu 960; RV64-NEXT: vmulh.vx v9, v8, a0 961; RV64-NEXT: li a0, 63 962; RV64-NEXT: vsrl.vx v10, v9, a0 963; RV64-NEXT: vsra.vi v9, v9, 1 964; RV64-NEXT: vadd.vv v9, v9, v10 965; RV64-NEXT: li a0, -7 966; RV64-NEXT: vnmsac.vx v8, a0, v9 967; RV64-NEXT: ret 968 %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0 969 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer 970 %vc = srem <vscale x 1 x i64> %va, %splat 971 ret <vscale x 1 x i64> %vc 972} 973 974define <vscale x 2 x i64> @vrem_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) { 975; CHECK-LABEL: vrem_vv_nxv2i64: 976; CHECK: # %bb.0: 977; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu 978; CHECK-NEXT: vrem.vv v8, v8, v10 979; CHECK-NEXT: ret 980 %vc = srem <vscale x 2 x i64> %va, %vb 981 ret <vscale x 2 x i64> %vc 982} 983 984define <vscale x 2 x i64> @vrem_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) { 985; RV32-LABEL: vrem_vx_nxv2i64: 986; RV32: # %bb.0: 987; RV32-NEXT: addi sp, sp, -16 988; RV32-NEXT: .cfi_def_cfa_offset 16 989; RV32-NEXT: sw a1, 12(sp) 990; RV32-NEXT: sw a0, 8(sp) 991; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu 992; RV32-NEXT: addi a0, sp, 8 993; RV32-NEXT: vlse64.v v10, (a0), zero 994; RV32-NEXT: vrem.vv v8, v8, v10 995; RV32-NEXT: addi sp, sp, 16 996; RV32-NEXT: ret 997; 998; RV64-LABEL: vrem_vx_nxv2i64: 999; RV64: # %bb.0: 1000; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu 1001; RV64-NEXT: vrem.vx v8, v8, a0 1002; RV64-NEXT: ret 1003 %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0 1004 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 1005 %vc = srem <vscale x 2 x i64> %va, %splat 1006 ret <vscale x 2 x i64> %vc 1007} 1008 1009define <vscale x 2 x i64> @vrem_vi_nxv2i64_0(<vscale x 2 x i64> %va) { 1010; RV32-LABEL: vrem_vi_nxv2i64_0: 1011; RV32: # %bb.0: 1012; RV32-NEXT: addi sp, sp, -16 1013; RV32-NEXT: .cfi_def_cfa_offset 16 1014; RV32-NEXT: lui a0, 748983 1015; RV32-NEXT: addi a0, a0, -586 1016; RV32-NEXT: sw a0, 12(sp) 1017; RV32-NEXT: lui a0, 898779 1018; RV32-NEXT: addi a0, a0, 1755 1019; RV32-NEXT: sw a0, 8(sp) 1020; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu 1021; RV32-NEXT: addi a0, sp, 8 1022; RV32-NEXT: vlse64.v v10, (a0), zero 1023; RV32-NEXT: vmulh.vv v10, v8, v10 1024; RV32-NEXT: li a0, 63 1025; RV32-NEXT: vsrl.vx v12, v10, a0 1026; RV32-NEXT: vsra.vi v10, v10, 1 1027; RV32-NEXT: vadd.vv v10, v10, v12 1028; RV32-NEXT: li a0, -7 1029; RV32-NEXT: vnmsac.vx v8, a0, v10 1030; RV32-NEXT: addi sp, sp, 16 1031; RV32-NEXT: ret 1032; 1033; RV64-LABEL: vrem_vi_nxv2i64_0: 1034; RV64: # %bb.0: 1035; RV64-NEXT: lui a0, %hi(.LCPI59_0) 1036; RV64-NEXT: ld a0, %lo(.LCPI59_0)(a0) 1037; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, mu 1038; RV64-NEXT: vmulh.vx v10, v8, a0 1039; RV64-NEXT: li a0, 63 1040; RV64-NEXT: vsrl.vx v12, v10, a0 1041; RV64-NEXT: vsra.vi v10, v10, 1 1042; RV64-NEXT: vadd.vv v10, v10, v12 1043; RV64-NEXT: li a0, -7 1044; RV64-NEXT: vnmsac.vx v8, a0, v10 1045; RV64-NEXT: ret 1046 %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0 1047 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer 1048 %vc = srem <vscale x 2 x i64> %va, %splat 1049 ret <vscale x 2 x i64> %vc 1050} 1051 1052define <vscale x 4 x i64> @vrem_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) { 1053; CHECK-LABEL: vrem_vv_nxv4i64: 1054; CHECK: # %bb.0: 1055; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu 1056; CHECK-NEXT: vrem.vv v8, v8, v12 1057; CHECK-NEXT: ret 1058 %vc = srem <vscale x 4 x i64> %va, %vb 1059 ret <vscale x 4 x i64> %vc 1060} 1061 1062define <vscale x 4 x i64> @vrem_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) { 1063; RV32-LABEL: vrem_vx_nxv4i64: 1064; RV32: # %bb.0: 1065; RV32-NEXT: addi sp, sp, -16 1066; RV32-NEXT: .cfi_def_cfa_offset 16 1067; RV32-NEXT: sw a1, 12(sp) 1068; RV32-NEXT: sw a0, 8(sp) 1069; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu 1070; RV32-NEXT: addi a0, sp, 8 1071; RV32-NEXT: vlse64.v v12, (a0), zero 1072; RV32-NEXT: vrem.vv v8, v8, v12 1073; RV32-NEXT: addi sp, sp, 16 1074; RV32-NEXT: ret 1075; 1076; RV64-LABEL: vrem_vx_nxv4i64: 1077; RV64: # %bb.0: 1078; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu 1079; RV64-NEXT: vrem.vx v8, v8, a0 1080; RV64-NEXT: ret 1081 %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0 1082 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer 1083 %vc = srem <vscale x 4 x i64> %va, %splat 1084 ret <vscale x 4 x i64> %vc 1085} 1086 1087define <vscale x 4 x i64> @vrem_vi_nxv4i64_0(<vscale x 4 x i64> %va) { 1088; RV32-LABEL: vrem_vi_nxv4i64_0: 1089; RV32: # %bb.0: 1090; RV32-NEXT: addi sp, sp, -16 1091; RV32-NEXT: .cfi_def_cfa_offset 16 1092; RV32-NEXT: lui a0, 748983 1093; RV32-NEXT: addi a0, a0, -586 1094; RV32-NEXT: sw a0, 12(sp) 1095; RV32-NEXT: lui a0, 898779 1096; RV32-NEXT: addi a0, a0, 1755 1097; RV32-NEXT: sw a0, 8(sp) 1098; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu 1099; RV32-NEXT: addi a0, sp, 8 1100; RV32-NEXT: vlse64.v v12, (a0), zero 1101; RV32-NEXT: vmulh.vv v12, v8, v12 1102; RV32-NEXT: li a0, 63 1103; RV32-NEXT: vsrl.vx v16, v12, a0 1104; RV32-NEXT: vsra.vi v12, v12, 1 1105; RV32-NEXT: vadd.vv v12, v12, v16 1106; RV32-NEXT: li a0, -7 1107; RV32-NEXT: vnmsac.vx v8, a0, v12 1108; RV32-NEXT: addi sp, sp, 16 1109; RV32-NEXT: ret 1110; 1111; RV64-LABEL: vrem_vi_nxv4i64_0: 1112; RV64: # %bb.0: 1113; RV64-NEXT: lui a0, %hi(.LCPI62_0) 1114; RV64-NEXT: ld a0, %lo(.LCPI62_0)(a0) 1115; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, mu 1116; RV64-NEXT: vmulh.vx v12, v8, a0 1117; RV64-NEXT: li a0, 63 1118; RV64-NEXT: vsrl.vx v16, v12, a0 1119; RV64-NEXT: vsra.vi v12, v12, 1 1120; RV64-NEXT: vadd.vv v12, v12, v16 1121; RV64-NEXT: li a0, -7 1122; RV64-NEXT: vnmsac.vx v8, a0, v12 1123; RV64-NEXT: ret 1124 %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0 1125 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer 1126 %vc = srem <vscale x 4 x i64> %va, %splat 1127 ret <vscale x 4 x i64> %vc 1128} 1129 1130define <vscale x 8 x i64> @vrem_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { 1131; CHECK-LABEL: vrem_vv_nxv8i64: 1132; CHECK: # %bb.0: 1133; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 1134; CHECK-NEXT: vrem.vv v8, v8, v16 1135; CHECK-NEXT: ret 1136 %vc = srem <vscale x 8 x i64> %va, %vb 1137 ret <vscale x 8 x i64> %vc 1138} 1139 1140define <vscale x 8 x i64> @vrem_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 1141; RV32-LABEL: vrem_vx_nxv8i64: 1142; RV32: # %bb.0: 1143; RV32-NEXT: addi sp, sp, -16 1144; RV32-NEXT: .cfi_def_cfa_offset 16 1145; RV32-NEXT: sw a1, 12(sp) 1146; RV32-NEXT: sw a0, 8(sp) 1147; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu 1148; RV32-NEXT: addi a0, sp, 8 1149; RV32-NEXT: vlse64.v v16, (a0), zero 1150; RV32-NEXT: vrem.vv v8, v8, v16 1151; RV32-NEXT: addi sp, sp, 16 1152; RV32-NEXT: ret 1153; 1154; RV64-LABEL: vrem_vx_nxv8i64: 1155; RV64: # %bb.0: 1156; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu 1157; RV64-NEXT: vrem.vx v8, v8, a0 1158; RV64-NEXT: ret 1159 %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0 1160 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer 1161 %vc = srem <vscale x 8 x i64> %va, %splat 1162 ret <vscale x 8 x i64> %vc 1163} 1164 1165define <vscale x 8 x i64> @vrem_vi_nxv8i64_0(<vscale x 8 x i64> %va) { 1166; RV32-LABEL: vrem_vi_nxv8i64_0: 1167; RV32: # %bb.0: 1168; RV32-NEXT: addi sp, sp, -16 1169; RV32-NEXT: .cfi_def_cfa_offset 16 1170; RV32-NEXT: lui a0, 748983 1171; RV32-NEXT: addi a0, a0, -586 1172; RV32-NEXT: sw a0, 12(sp) 1173; RV32-NEXT: lui a0, 898779 1174; RV32-NEXT: addi a0, a0, 1755 1175; RV32-NEXT: sw a0, 8(sp) 1176; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu 1177; RV32-NEXT: addi a0, sp, 8 1178; RV32-NEXT: vlse64.v v16, (a0), zero 1179; RV32-NEXT: vmulh.vv v16, v8, v16 1180; RV32-NEXT: li a0, 63 1181; RV32-NEXT: vsrl.vx v24, v16, a0 1182; RV32-NEXT: vsra.vi v16, v16, 1 1183; RV32-NEXT: vadd.vv v16, v16, v24 1184; RV32-NEXT: li a0, -7 1185; RV32-NEXT: vnmsac.vx v8, a0, v16 1186; RV32-NEXT: addi sp, sp, 16 1187; RV32-NEXT: ret 1188; 1189; RV64-LABEL: vrem_vi_nxv8i64_0: 1190; RV64: # %bb.0: 1191; RV64-NEXT: lui a0, %hi(.LCPI65_0) 1192; RV64-NEXT: ld a0, %lo(.LCPI65_0)(a0) 1193; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu 1194; RV64-NEXT: vmulh.vx v16, v8, a0 1195; RV64-NEXT: li a0, 63 1196; RV64-NEXT: vsrl.vx v24, v16, a0 1197; RV64-NEXT: vsra.vi v16, v16, 1 1198; RV64-NEXT: vadd.vv v16, v16, v24 1199; RV64-NEXT: li a0, -7 1200; RV64-NEXT: vnmsac.vx v8, a0, v16 1201; RV64-NEXT: ret 1202 %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0 1203 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer 1204 %vc = srem <vscale x 8 x i64> %va, %splat 1205 ret <vscale x 8 x i64> %vc 1206} 1207 1208