1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -target-abi=ilp32 \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
4; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -target-abi=lp64 \
5; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
6
7define <vscale x 1 x i32> @vnsra_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
8; CHECK-LABEL: vnsra_wv_nxv1i32_sext:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
11; CHECK-NEXT:    vnsra.wv v8, v8, v9
12; CHECK-NEXT:    ret
13  %vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
14  %x = ashr <vscale x 1 x i64> %va, %vc
15  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
16  ret <vscale x 1 x i32> %y
17}
18
19define <vscale x 1 x i32> @vnsra_wx_i32_nxv1i32_sext(<vscale x 1 x i64> %va, i32 %b) {
20; CHECK-LABEL: vnsra_wx_i32_nxv1i32_sext:
21; CHECK:       # %bb.0:
22; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
23; CHECK-NEXT:    vnsra.wx v8, v8, a0
24; CHECK-NEXT:    ret
25  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
26  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
27  %vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
28  %x = ashr <vscale x 1 x i64> %va, %vb
29  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
30  ret <vscale x 1 x i32> %y
31}
32
33define <vscale x 2 x i32> @vnsra_wv_nxv2i32_sext(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
34; CHECK-LABEL: vnsra_wv_nxv2i32_sext:
35; CHECK:       # %bb.0:
36; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
37; CHECK-NEXT:    vnsra.wv v11, v8, v10
38; CHECK-NEXT:    vmv.v.v v8, v11
39; CHECK-NEXT:    ret
40  %vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
41  %x = ashr <vscale x 2 x i64> %va, %vc
42  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
43  ret <vscale x 2 x i32> %y
44}
45
46define <vscale x 2 x i32> @vnsra_wx_i32_nxv2i32_sext(<vscale x 2 x i64> %va, i32 %b) {
47; CHECK-LABEL: vnsra_wx_i32_nxv2i32_sext:
48; CHECK:       # %bb.0:
49; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
50; CHECK-NEXT:    vnsra.wx v10, v8, a0
51; CHECK-NEXT:    vmv.v.v v8, v10
52; CHECK-NEXT:    ret
53  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
54  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
55  %vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
56  %x = ashr <vscale x 2 x i64> %va, %vb
57  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
58  ret <vscale x 2 x i32> %y
59}
60
61define <vscale x 4 x i32> @vnsra_wv_nxv4i32_sext(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
62; CHECK-LABEL: vnsra_wv_nxv4i32_sext:
63; CHECK:       # %bb.0:
64; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
65; CHECK-NEXT:    vnsra.wv v14, v8, v12
66; CHECK-NEXT:    vmv.v.v v8, v14
67; CHECK-NEXT:    ret
68  %vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
69  %x = ashr <vscale x 4 x i64> %va, %vc
70  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
71  ret <vscale x 4 x i32> %y
72}
73
74define <vscale x 4 x i32> @vnsra_wx_i32_nxv4i32_sext(<vscale x 4 x i64> %va, i32 %b) {
75; CHECK-LABEL: vnsra_wx_i32_nxv4i32_sext:
76; CHECK:       # %bb.0:
77; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
78; CHECK-NEXT:    vnsra.wx v12, v8, a0
79; CHECK-NEXT:    vmv.v.v v8, v12
80; CHECK-NEXT:    ret
81  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
82  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
83  %vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
84  %x = ashr <vscale x 4 x i64> %va, %vb
85  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
86  ret <vscale x 4 x i32> %y
87}
88
89define <vscale x 8 x i32> @vnsra_wv_nxv8i32_sext(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
90; CHECK-LABEL: vnsra_wv_nxv8i32_sext:
91; CHECK:       # %bb.0:
92; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
93; CHECK-NEXT:    vnsra.wv v20, v8, v16
94; CHECK-NEXT:    vmv.v.v v8, v20
95; CHECK-NEXT:    ret
96  %vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
97  %x = ashr <vscale x 8 x i64> %va, %vc
98  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
99  ret <vscale x 8 x i32> %y
100}
101
102define <vscale x 8 x i32> @vnsra_wx_i32_nxv8i32_sext(<vscale x 8 x i64> %va, i32 %b) {
103; CHECK-LABEL: vnsra_wx_i32_nxv8i32_sext:
104; CHECK:       # %bb.0:
105; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
106; CHECK-NEXT:    vnsra.wx v16, v8, a0
107; CHECK-NEXT:    vmv.v.v v8, v16
108; CHECK-NEXT:    ret
109  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
110  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
111  %vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
112  %x = ashr <vscale x 8 x i64> %va, %vb
113  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
114  ret <vscale x 8 x i32> %y
115}
116
117define <vscale x 1 x i32> @vnsra_wv_nxv1i32_zext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
118; CHECK-LABEL: vnsra_wv_nxv1i32_zext:
119; CHECK:       # %bb.0:
120; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
121; CHECK-NEXT:    vnsra.wv v8, v8, v9
122; CHECK-NEXT:    ret
123  %vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
124  %x = ashr <vscale x 1 x i64> %va, %vc
125  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
126  ret <vscale x 1 x i32> %y
127}
128
129define <vscale x 1 x i32> @vnsra_wx_i32_nxv1i32_zext(<vscale x 1 x i64> %va, i32 %b) {
130; CHECK-LABEL: vnsra_wx_i32_nxv1i32_zext:
131; CHECK:       # %bb.0:
132; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
133; CHECK-NEXT:    vnsra.wx v8, v8, a0
134; CHECK-NEXT:    ret
135  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
136  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
137  %vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
138  %x = ashr <vscale x 1 x i64> %va, %vb
139  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
140  ret <vscale x 1 x i32> %y
141}
142
143define <vscale x 2 x i32> @vnsra_wv_nxv2i32_zext(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
144; CHECK-LABEL: vnsra_wv_nxv2i32_zext:
145; CHECK:       # %bb.0:
146; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
147; CHECK-NEXT:    vnsra.wv v11, v8, v10
148; CHECK-NEXT:    vmv.v.v v8, v11
149; CHECK-NEXT:    ret
150  %vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
151  %x = ashr <vscale x 2 x i64> %va, %vc
152  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
153  ret <vscale x 2 x i32> %y
154}
155
156define <vscale x 2 x i32> @vnsra_wx_i32_nxv2i32_zext(<vscale x 2 x i64> %va, i32 %b) {
157; CHECK-LABEL: vnsra_wx_i32_nxv2i32_zext:
158; CHECK:       # %bb.0:
159; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
160; CHECK-NEXT:    vnsra.wx v10, v8, a0
161; CHECK-NEXT:    vmv.v.v v8, v10
162; CHECK-NEXT:    ret
163  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
164  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
165  %vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
166  %x = ashr <vscale x 2 x i64> %va, %vb
167  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
168  ret <vscale x 2 x i32> %y
169}
170
171define <vscale x 4 x i32> @vnsra_wv_nxv4i32_zext(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
172; CHECK-LABEL: vnsra_wv_nxv4i32_zext:
173; CHECK:       # %bb.0:
174; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
175; CHECK-NEXT:    vnsra.wv v14, v8, v12
176; CHECK-NEXT:    vmv.v.v v8, v14
177; CHECK-NEXT:    ret
178  %vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
179  %x = ashr <vscale x 4 x i64> %va, %vc
180  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
181  ret <vscale x 4 x i32> %y
182}
183
184define <vscale x 4 x i32> @vnsra_wx_i32_nxv4i32_zext(<vscale x 4 x i64> %va, i32 %b) {
185; CHECK-LABEL: vnsra_wx_i32_nxv4i32_zext:
186; CHECK:       # %bb.0:
187; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
188; CHECK-NEXT:    vnsra.wx v12, v8, a0
189; CHECK-NEXT:    vmv.v.v v8, v12
190; CHECK-NEXT:    ret
191  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
192  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
193  %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
194  %x = ashr <vscale x 4 x i64> %va, %vb
195  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
196  ret <vscale x 4 x i32> %y
197}
198
199define <vscale x 8 x i32> @vnsra_wv_nxv8i32_zext(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
200; CHECK-LABEL: vnsra_wv_nxv8i32_zext:
201; CHECK:       # %bb.0:
202; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
203; CHECK-NEXT:    vnsra.wv v20, v8, v16
204; CHECK-NEXT:    vmv.v.v v8, v20
205; CHECK-NEXT:    ret
206  %vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
207  %x = ashr <vscale x 8 x i64> %va, %vc
208  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
209  ret <vscale x 8 x i32> %y
210}
211
212define <vscale x 8 x i32> @vnsra_wx_i32_nxv8i32_zext(<vscale x 8 x i64> %va, i32 %b) {
213; CHECK-LABEL: vnsra_wx_i32_nxv8i32_zext:
214; CHECK:       # %bb.0:
215; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
216; CHECK-NEXT:    vnsra.wx v16, v8, a0
217; CHECK-NEXT:    vmv.v.v v8, v16
218; CHECK-NEXT:    ret
219  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
220  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
221  %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
222  %x = ashr <vscale x 8 x i64> %va, %vb
223  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
224  ret <vscale x 8 x i32> %y
225}
226