1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
3; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
4
5define <vscale x 1 x i32> @vmulhu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
6; CHECK-LABEL: vmulhu_vv_nxv1i32:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
9; CHECK-NEXT:    vmulhu.vv v8, v9, v8
10; CHECK-NEXT:    ret
11  %vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
12  %vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
13  %ve = mul <vscale x 1 x i64> %vc, %vd
14  %head = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
15  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
16  %vf = lshr <vscale x 1 x i64> %ve, %splat
17  %vg = trunc <vscale x 1 x i64> %vf to <vscale x 1 x i32>
18  ret <vscale x 1 x i32> %vg
19}
20
21define <vscale x 1 x i32> @vmulhu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %x) {
22; CHECK-LABEL: vmulhu_vx_nxv1i32:
23; CHECK:       # %bb.0:
24; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
25; CHECK-NEXT:    vmulhu.vx v8, v8, a0
26; CHECK-NEXT:    ret
27  %head1 = insertelement <vscale x 1 x i32> undef, i32 %x, i32 0
28  %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
29  %vb = zext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
30  %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
31  %vd = mul <vscale x 1 x i64> %vb, %vc
32  %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
33  %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
34  %ve = lshr <vscale x 1 x i64> %vd, %splat2
35  %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
36  ret <vscale x 1 x i32> %vf
37}
38
39define <vscale x 1 x i32> @vmulhu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
40; RV32-LABEL: vmulhu_vi_nxv1i32_0:
41; RV32:       # %bb.0:
42; RV32-NEXT:    li a0, -7
43; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
44; RV32-NEXT:    vmulhu.vx v8, v8, a0
45; RV32-NEXT:    ret
46;
47; RV64-LABEL: vmulhu_vi_nxv1i32_0:
48; RV64:       # %bb.0:
49; RV64-NEXT:    li a0, 1
50; RV64-NEXT:    slli a0, a0, 32
51; RV64-NEXT:    addi a0, a0, -7
52; RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
53; RV64-NEXT:    vmulhu.vx v8, v8, a0
54; RV64-NEXT:    ret
55  %head1 = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
56  %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
57  %vb = zext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
58  %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
59  %vd = mul <vscale x 1 x i64> %vb, %vc
60  %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
61  %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
62  %ve = lshr <vscale x 1 x i64> %vd, %splat2
63  %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
64  ret <vscale x 1 x i32> %vf
65}
66
67define <vscale x 1 x i32> @vmulhu_vi_nxv1i32_1(<vscale x 1 x i32> %va) {
68; RV32-LABEL: vmulhu_vi_nxv1i32_1:
69; RV32:       # %bb.0:
70; RV32-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
71; RV32-NEXT:    vsrl.vi v8, v8, 28
72; RV32-NEXT:    ret
73;
74; RV64-LABEL: vmulhu_vi_nxv1i32_1:
75; RV64:       # %bb.0:
76; RV64-NEXT:    li a0, 16
77; RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
78; RV64-NEXT:    vmulhu.vx v8, v8, a0
79; RV64-NEXT:    ret
80  %head1 = insertelement <vscale x 1 x i32> undef, i32 16, i32 0
81  %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
82  %vb = zext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
83  %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
84  %vd = mul <vscale x 1 x i64> %vb, %vc
85  %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
86  %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
87  %ve = lshr <vscale x 1 x i64> %vd, %splat2
88  %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
89  ret <vscale x 1 x i32> %vf
90}
91
92define <vscale x 2 x i32> @vmulhu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
93; CHECK-LABEL: vmulhu_vv_nxv2i32:
94; CHECK:       # %bb.0:
95; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
96; CHECK-NEXT:    vmulhu.vv v8, v9, v8
97; CHECK-NEXT:    ret
98  %vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
99  %vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
100  %ve = mul <vscale x 2 x i64> %vc, %vd
101  %head = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
102  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
103  %vf = lshr <vscale x 2 x i64> %ve, %splat
104  %vg = trunc <vscale x 2 x i64> %vf to <vscale x 2 x i32>
105  ret <vscale x 2 x i32> %vg
106}
107
108define <vscale x 2 x i32> @vmulhu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %x) {
109; CHECK-LABEL: vmulhu_vx_nxv2i32:
110; CHECK:       # %bb.0:
111; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
112; CHECK-NEXT:    vmulhu.vx v8, v8, a0
113; CHECK-NEXT:    ret
114  %head1 = insertelement <vscale x 2 x i32> undef, i32 %x, i32 0
115  %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
116  %vb = zext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
117  %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
118  %vd = mul <vscale x 2 x i64> %vb, %vc
119  %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
120  %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
121  %ve = lshr <vscale x 2 x i64> %vd, %splat2
122  %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
123  ret <vscale x 2 x i32> %vf
124}
125
126define <vscale x 2 x i32> @vmulhu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
127; RV32-LABEL: vmulhu_vi_nxv2i32_0:
128; RV32:       # %bb.0:
129; RV32-NEXT:    li a0, -7
130; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
131; RV32-NEXT:    vmulhu.vx v8, v8, a0
132; RV32-NEXT:    ret
133;
134; RV64-LABEL: vmulhu_vi_nxv2i32_0:
135; RV64:       # %bb.0:
136; RV64-NEXT:    li a0, 1
137; RV64-NEXT:    slli a0, a0, 32
138; RV64-NEXT:    addi a0, a0, -7
139; RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
140; RV64-NEXT:    vmulhu.vx v8, v8, a0
141; RV64-NEXT:    ret
142  %head1 = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
143  %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
144  %vb = zext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
145  %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
146  %vd = mul <vscale x 2 x i64> %vb, %vc
147  %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
148  %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
149  %ve = lshr <vscale x 2 x i64> %vd, %splat2
150  %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
151  ret <vscale x 2 x i32> %vf
152}
153
154define <vscale x 2 x i32> @vmulhu_vi_nxv2i32_1(<vscale x 2 x i32> %va) {
155; RV32-LABEL: vmulhu_vi_nxv2i32_1:
156; RV32:       # %bb.0:
157; RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
158; RV32-NEXT:    vsrl.vi v8, v8, 28
159; RV32-NEXT:    ret
160;
161; RV64-LABEL: vmulhu_vi_nxv2i32_1:
162; RV64:       # %bb.0:
163; RV64-NEXT:    li a0, 16
164; RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
165; RV64-NEXT:    vmulhu.vx v8, v8, a0
166; RV64-NEXT:    ret
167  %head1 = insertelement <vscale x 2 x i32> undef, i32 16, i32 0
168  %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
169  %vb = zext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
170  %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
171  %vd = mul <vscale x 2 x i64> %vb, %vc
172  %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
173  %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
174  %ve = lshr <vscale x 2 x i64> %vd, %splat2
175  %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
176  ret <vscale x 2 x i32> %vf
177}
178
179define <vscale x 4 x i32> @vmulhu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
180; CHECK-LABEL: vmulhu_vv_nxv4i32:
181; CHECK:       # %bb.0:
182; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
183; CHECK-NEXT:    vmulhu.vv v8, v10, v8
184; CHECK-NEXT:    ret
185  %vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
186  %vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
187  %ve = mul <vscale x 4 x i64> %vc, %vd
188  %head = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
189  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
190  %vf = lshr <vscale x 4 x i64> %ve, %splat
191  %vg = trunc <vscale x 4 x i64> %vf to <vscale x 4 x i32>
192  ret <vscale x 4 x i32> %vg
193}
194
195define <vscale x 4 x i32> @vmulhu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %x) {
196; CHECK-LABEL: vmulhu_vx_nxv4i32:
197; CHECK:       # %bb.0:
198; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
199; CHECK-NEXT:    vmulhu.vx v8, v8, a0
200; CHECK-NEXT:    ret
201  %head1 = insertelement <vscale x 4 x i32> undef, i32 %x, i32 0
202  %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
203  %vb = zext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
204  %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
205  %vd = mul <vscale x 4 x i64> %vb, %vc
206  %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
207  %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
208  %ve = lshr <vscale x 4 x i64> %vd, %splat2
209  %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
210  ret <vscale x 4 x i32> %vf
211}
212
213define <vscale x 4 x i32> @vmulhu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
214; RV32-LABEL: vmulhu_vi_nxv4i32_0:
215; RV32:       # %bb.0:
216; RV32-NEXT:    li a0, -7
217; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
218; RV32-NEXT:    vmulhu.vx v8, v8, a0
219; RV32-NEXT:    ret
220;
221; RV64-LABEL: vmulhu_vi_nxv4i32_0:
222; RV64:       # %bb.0:
223; RV64-NEXT:    li a0, 1
224; RV64-NEXT:    slli a0, a0, 32
225; RV64-NEXT:    addi a0, a0, -7
226; RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
227; RV64-NEXT:    vmulhu.vx v8, v8, a0
228; RV64-NEXT:    ret
229  %head1 = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
230  %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
231  %vb = zext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
232  %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
233  %vd = mul <vscale x 4 x i64> %vb, %vc
234  %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
235  %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
236  %ve = lshr <vscale x 4 x i64> %vd, %splat2
237  %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
238  ret <vscale x 4 x i32> %vf
239}
240
241define <vscale x 4 x i32> @vmulhu_vi_nxv4i32_1(<vscale x 4 x i32> %va) {
242; RV32-LABEL: vmulhu_vi_nxv4i32_1:
243; RV32:       # %bb.0:
244; RV32-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
245; RV32-NEXT:    vsrl.vi v8, v8, 28
246; RV32-NEXT:    ret
247;
248; RV64-LABEL: vmulhu_vi_nxv4i32_1:
249; RV64:       # %bb.0:
250; RV64-NEXT:    li a0, 16
251; RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
252; RV64-NEXT:    vmulhu.vx v8, v8, a0
253; RV64-NEXT:    ret
254  %head1 = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
255  %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
256  %vb = zext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
257  %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
258  %vd = mul <vscale x 4 x i64> %vb, %vc
259  %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
260  %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
261  %ve = lshr <vscale x 4 x i64> %vd, %splat2
262  %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
263  ret <vscale x 4 x i32> %vf
264}
265
266define <vscale x 8 x i32> @vmulhu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
267; CHECK-LABEL: vmulhu_vv_nxv8i32:
268; CHECK:       # %bb.0:
269; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
270; CHECK-NEXT:    vmulhu.vv v8, v12, v8
271; CHECK-NEXT:    ret
272  %vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
273  %vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
274  %ve = mul <vscale x 8 x i64> %vc, %vd
275  %head = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
276  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
277  %vf = lshr <vscale x 8 x i64> %ve, %splat
278  %vg = trunc <vscale x 8 x i64> %vf to <vscale x 8 x i32>
279  ret <vscale x 8 x i32> %vg
280}
281
282define <vscale x 8 x i32> @vmulhu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %x) {
283; CHECK-LABEL: vmulhu_vx_nxv8i32:
284; CHECK:       # %bb.0:
285; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
286; CHECK-NEXT:    vmulhu.vx v8, v8, a0
287; CHECK-NEXT:    ret
288  %head1 = insertelement <vscale x 8 x i32> undef, i32 %x, i32 0
289  %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
290  %vb = zext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
291  %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
292  %vd = mul <vscale x 8 x i64> %vb, %vc
293  %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
294  %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
295  %ve = lshr <vscale x 8 x i64> %vd, %splat2
296  %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
297  ret <vscale x 8 x i32> %vf
298}
299
300define <vscale x 8 x i32> @vmulhu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
301; RV32-LABEL: vmulhu_vi_nxv8i32_0:
302; RV32:       # %bb.0:
303; RV32-NEXT:    li a0, -7
304; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
305; RV32-NEXT:    vmulhu.vx v8, v8, a0
306; RV32-NEXT:    ret
307;
308; RV64-LABEL: vmulhu_vi_nxv8i32_0:
309; RV64:       # %bb.0:
310; RV64-NEXT:    li a0, 1
311; RV64-NEXT:    slli a0, a0, 32
312; RV64-NEXT:    addi a0, a0, -7
313; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
314; RV64-NEXT:    vmulhu.vx v8, v8, a0
315; RV64-NEXT:    ret
316  %head1 = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
317  %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
318  %vb = zext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
319  %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
320  %vd = mul <vscale x 8 x i64> %vb, %vc
321  %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
322  %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
323  %ve = lshr <vscale x 8 x i64> %vd, %splat2
324  %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
325  ret <vscale x 8 x i32> %vf
326}
327
328define <vscale x 8 x i32> @vmulhu_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
329; RV32-LABEL: vmulhu_vi_nxv8i32_1:
330; RV32:       # %bb.0:
331; RV32-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
332; RV32-NEXT:    vsrl.vi v8, v8, 28
333; RV32-NEXT:    ret
334;
335; RV64-LABEL: vmulhu_vi_nxv8i32_1:
336; RV64:       # %bb.0:
337; RV64-NEXT:    li a0, 16
338; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
339; RV64-NEXT:    vmulhu.vx v8, v8, a0
340; RV64-NEXT:    ret
341  %head1 = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
342  %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
343  %vb = zext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
344  %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
345  %vd = mul <vscale x 8 x i64> %vb, %vc
346  %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
347  %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
348  %ve = lshr <vscale x 8 x i64> %vd, %splat2
349  %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
350  ret <vscale x 8 x i32> %vf
351}
352