1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
3; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
4
5; Test that the prepareSREMEqFold optimization doesn't crash on scalable
6; vector types.
7define <vscale x 4 x i1> @srem_eq_fold_nxv4i8(<vscale x 4 x i8> %va) {
8; CHECK-LABEL: srem_eq_fold_nxv4i8:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    addi a0, zero, 42
11; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
12; CHECK-NEXT:    vmv.v.x v9, a0
13; CHECK-NEXT:    addi a1, zero, -85
14; CHECK-NEXT:    vmacc.vx v9, a1, v8
15; CHECK-NEXT:    vsll.vi v8, v9, 7
16; CHECK-NEXT:    vsrl.vi v9, v9, 1
17; CHECK-NEXT:    vor.vv v8, v9, v8
18; CHECK-NEXT:    vmsleu.vx v0, v8, a0
19; CHECK-NEXT:    ret
20  %head_six = insertelement <vscale x 4 x i8> undef, i8 6, i32 0
21  %splat_six = shufflevector <vscale x 4 x i8> %head_six, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
22  %rem = srem <vscale x 4 x i8> %va, %splat_six
23
24  %cc = icmp eq <vscale x 4 x i8> %rem, zeroinitializer
25  ret <vscale x 4 x i1> %cc
26}
27
28define <vscale x 1 x i32> @vmulh_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
29; CHECK-LABEL: vmulh_vv_nxv1i32:
30; CHECK:       # %bb.0:
31; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
32; CHECK-NEXT:    vmulh.vv v8, v9, v8
33; CHECK-NEXT:    ret
34  %vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
35  %vd = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
36  %ve = mul <vscale x 1 x i64> %vc, %vd
37  %head = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
38  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
39  %vf = lshr <vscale x 1 x i64> %ve, %splat
40  %vg = trunc <vscale x 1 x i64> %vf to <vscale x 1 x i32>
41  ret <vscale x 1 x i32> %vg
42}
43
44define <vscale x 1 x i32> @vmulh_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %x) {
45; CHECK-LABEL: vmulh_vx_nxv1i32:
46; CHECK:       # %bb.0:
47; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
48; CHECK-NEXT:    vmulh.vx v8, v8, a0
49; CHECK-NEXT:    ret
50  %head1 = insertelement <vscale x 1 x i32> undef, i32 %x, i32 0
51  %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
52  %vb = sext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
53  %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
54  %vd = mul <vscale x 1 x i64> %vb, %vc
55  %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
56  %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
57  %ve = lshr <vscale x 1 x i64> %vd, %splat2
58  %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
59  ret <vscale x 1 x i32> %vf
60}
61
62define <vscale x 1 x i32> @vmulh_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
63; CHECK-LABEL: vmulh_vi_nxv1i32_0:
64; CHECK:       # %bb.0:
65; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
66; CHECK-NEXT:    vsext.vf2 v9, v8
67; CHECK-NEXT:    addi a0, zero, -7
68; CHECK-NEXT:    vmul.vx v8, v9, a0
69; CHECK-NEXT:    addi a0, zero, 32
70; CHECK-NEXT:    vsrl.vx v8, v8, a0
71; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
72; CHECK-NEXT:    vnsrl.wi v8, v8, 0
73; CHECK-NEXT:    ret
74  %head1 = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
75  %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
76  %vb = sext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
77  %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
78  %vd = mul <vscale x 1 x i64> %vb, %vc
79  %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
80  %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
81  %ve = lshr <vscale x 1 x i64> %vd, %splat2
82  %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
83  ret <vscale x 1 x i32> %vf
84}
85
86define <vscale x 1 x i32> @vmulh_vi_nxv1i32_1(<vscale x 1 x i32> %va) {
87; CHECK-LABEL: vmulh_vi_nxv1i32_1:
88; CHECK:       # %bb.0:
89; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
90; CHECK-NEXT:    vsext.vf2 v9, v8
91; CHECK-NEXT:    vsll.vi v8, v9, 4
92; CHECK-NEXT:    addi a0, zero, 32
93; CHECK-NEXT:    vsrl.vx v8, v8, a0
94; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
95; CHECK-NEXT:    vnsrl.wi v8, v8, 0
96; CHECK-NEXT:    ret
97  %head1 = insertelement <vscale x 1 x i32> undef, i32 16, i32 0
98  %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
99  %vb = sext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
100  %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
101  %vd = mul <vscale x 1 x i64> %vb, %vc
102  %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
103  %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
104  %ve = lshr <vscale x 1 x i64> %vd, %splat2
105  %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
106  ret <vscale x 1 x i32> %vf
107}
108
109define <vscale x 2 x i32> @vmulh_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
110; CHECK-LABEL: vmulh_vv_nxv2i32:
111; CHECK:       # %bb.0:
112; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
113; CHECK-NEXT:    vmulh.vv v8, v9, v8
114; CHECK-NEXT:    ret
115  %vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
116  %vd = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
117  %ve = mul <vscale x 2 x i64> %vc, %vd
118  %head = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
119  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
120  %vf = lshr <vscale x 2 x i64> %ve, %splat
121  %vg = trunc <vscale x 2 x i64> %vf to <vscale x 2 x i32>
122  ret <vscale x 2 x i32> %vg
123}
124
125define <vscale x 2 x i32> @vmulh_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %x) {
126; CHECK-LABEL: vmulh_vx_nxv2i32:
127; CHECK:       # %bb.0:
128; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
129; CHECK-NEXT:    vmulh.vx v8, v8, a0
130; CHECK-NEXT:    ret
131  %head1 = insertelement <vscale x 2 x i32> undef, i32 %x, i32 0
132  %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
133  %vb = sext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
134  %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
135  %vd = mul <vscale x 2 x i64> %vb, %vc
136  %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
137  %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
138  %ve = lshr <vscale x 2 x i64> %vd, %splat2
139  %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
140  ret <vscale x 2 x i32> %vf
141}
142
143define <vscale x 2 x i32> @vmulh_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
144; CHECK-LABEL: vmulh_vi_nxv2i32_0:
145; CHECK:       # %bb.0:
146; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
147; CHECK-NEXT:    vsext.vf2 v10, v8
148; CHECK-NEXT:    addi a0, zero, -7
149; CHECK-NEXT:    vmul.vx v8, v10, a0
150; CHECK-NEXT:    addi a0, zero, 32
151; CHECK-NEXT:    vsrl.vx v10, v8, a0
152; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
153; CHECK-NEXT:    vnsrl.wi v8, v10, 0
154; CHECK-NEXT:    ret
155  %head1 = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
156  %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
157  %vb = sext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
158  %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
159  %vd = mul <vscale x 2 x i64> %vb, %vc
160  %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
161  %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
162  %ve = lshr <vscale x 2 x i64> %vd, %splat2
163  %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
164  ret <vscale x 2 x i32> %vf
165}
166
167define <vscale x 2 x i32> @vmulh_vi_nxv2i32_1(<vscale x 2 x i32> %va) {
168; CHECK-LABEL: vmulh_vi_nxv2i32_1:
169; CHECK:       # %bb.0:
170; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
171; CHECK-NEXT:    vsext.vf2 v10, v8
172; CHECK-NEXT:    vsll.vi v8, v10, 4
173; CHECK-NEXT:    addi a0, zero, 32
174; CHECK-NEXT:    vsrl.vx v10, v8, a0
175; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
176; CHECK-NEXT:    vnsrl.wi v8, v10, 0
177; CHECK-NEXT:    ret
178  %head1 = insertelement <vscale x 2 x i32> undef, i32 16, i32 0
179  %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
180  %vb = sext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
181  %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
182  %vd = mul <vscale x 2 x i64> %vb, %vc
183  %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
184  %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
185  %ve = lshr <vscale x 2 x i64> %vd, %splat2
186  %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
187  ret <vscale x 2 x i32> %vf
188}
189
190define <vscale x 4 x i32> @vmulh_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
191; CHECK-LABEL: vmulh_vv_nxv4i32:
192; CHECK:       # %bb.0:
193; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
194; CHECK-NEXT:    vmulh.vv v8, v10, v8
195; CHECK-NEXT:    ret
196  %vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
197  %vd = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
198  %ve = mul <vscale x 4 x i64> %vc, %vd
199  %head = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
200  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
201  %vf = lshr <vscale x 4 x i64> %ve, %splat
202  %vg = trunc <vscale x 4 x i64> %vf to <vscale x 4 x i32>
203  ret <vscale x 4 x i32> %vg
204}
205
206define <vscale x 4 x i32> @vmulh_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %x) {
207; CHECK-LABEL: vmulh_vx_nxv4i32:
208; CHECK:       # %bb.0:
209; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
210; CHECK-NEXT:    vmulh.vx v8, v8, a0
211; CHECK-NEXT:    ret
212  %head1 = insertelement <vscale x 4 x i32> undef, i32 %x, i32 0
213  %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
214  %vb = sext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
215  %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
216  %vd = mul <vscale x 4 x i64> %vb, %vc
217  %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
218  %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
219  %ve = lshr <vscale x 4 x i64> %vd, %splat2
220  %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
221  ret <vscale x 4 x i32> %vf
222}
223
224define <vscale x 4 x i32> @vmulh_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
225; CHECK-LABEL: vmulh_vi_nxv4i32_0:
226; CHECK:       # %bb.0:
227; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
228; CHECK-NEXT:    vsext.vf2 v12, v8
229; CHECK-NEXT:    addi a0, zero, -7
230; CHECK-NEXT:    vmul.vx v8, v12, a0
231; CHECK-NEXT:    addi a0, zero, 32
232; CHECK-NEXT:    vsrl.vx v12, v8, a0
233; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
234; CHECK-NEXT:    vnsrl.wi v8, v12, 0
235; CHECK-NEXT:    ret
236  %head1 = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
237  %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
238  %vb = sext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
239  %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
240  %vd = mul <vscale x 4 x i64> %vb, %vc
241  %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
242  %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
243  %ve = lshr <vscale x 4 x i64> %vd, %splat2
244  %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
245  ret <vscale x 4 x i32> %vf
246}
247
248define <vscale x 4 x i32> @vmulh_vi_nxv4i32_1(<vscale x 4 x i32> %va) {
249; CHECK-LABEL: vmulh_vi_nxv4i32_1:
250; CHECK:       # %bb.0:
251; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
252; CHECK-NEXT:    vsext.vf2 v12, v8
253; CHECK-NEXT:    vsll.vi v8, v12, 4
254; CHECK-NEXT:    addi a0, zero, 32
255; CHECK-NEXT:    vsrl.vx v12, v8, a0
256; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
257; CHECK-NEXT:    vnsrl.wi v8, v12, 0
258; CHECK-NEXT:    ret
259  %head1 = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
260  %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
261  %vb = sext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
262  %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
263  %vd = mul <vscale x 4 x i64> %vb, %vc
264  %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
265  %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
266  %ve = lshr <vscale x 4 x i64> %vd, %splat2
267  %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
268  ret <vscale x 4 x i32> %vf
269}
270
271define <vscale x 8 x i32> @vmulh_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
272; CHECK-LABEL: vmulh_vv_nxv8i32:
273; CHECK:       # %bb.0:
274; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
275; CHECK-NEXT:    vmulh.vv v8, v12, v8
276; CHECK-NEXT:    ret
277  %vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
278  %vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
279  %ve = mul <vscale x 8 x i64> %vc, %vd
280  %head = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
281  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
282  %vf = lshr <vscale x 8 x i64> %ve, %splat
283  %vg = trunc <vscale x 8 x i64> %vf to <vscale x 8 x i32>
284  ret <vscale x 8 x i32> %vg
285}
286
287define <vscale x 8 x i32> @vmulh_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %x) {
288; CHECK-LABEL: vmulh_vx_nxv8i32:
289; CHECK:       # %bb.0:
290; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
291; CHECK-NEXT:    vmulh.vx v8, v8, a0
292; CHECK-NEXT:    ret
293  %head1 = insertelement <vscale x 8 x i32> undef, i32 %x, i32 0
294  %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
295  %vb = sext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
296  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
297  %vd = mul <vscale x 8 x i64> %vb, %vc
298  %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
299  %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
300  %ve = lshr <vscale x 8 x i64> %vd, %splat2
301  %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
302  ret <vscale x 8 x i32> %vf
303}
304
305define <vscale x 8 x i32> @vmulh_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
306; CHECK-LABEL: vmulh_vi_nxv8i32_0:
307; CHECK:       # %bb.0:
308; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
309; CHECK-NEXT:    vsext.vf2 v16, v8
310; CHECK-NEXT:    addi a0, zero, -7
311; CHECK-NEXT:    vmul.vx v8, v16, a0
312; CHECK-NEXT:    addi a0, zero, 32
313; CHECK-NEXT:    vsrl.vx v16, v8, a0
314; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
315; CHECK-NEXT:    vnsrl.wi v8, v16, 0
316; CHECK-NEXT:    ret
317  %head1 = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
318  %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
319  %vb = sext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
320  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
321  %vd = mul <vscale x 8 x i64> %vb, %vc
322  %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
323  %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
324  %ve = lshr <vscale x 8 x i64> %vd, %splat2
325  %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
326  ret <vscale x 8 x i32> %vf
327}
328
329define <vscale x 8 x i32> @vmulh_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
330; CHECK-LABEL: vmulh_vi_nxv8i32_1:
331; CHECK:       # %bb.0:
332; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
333; CHECK-NEXT:    vsext.vf2 v16, v8
334; CHECK-NEXT:    vsll.vi v8, v16, 4
335; CHECK-NEXT:    addi a0, zero, 32
336; CHECK-NEXT:    vsrl.vx v16, v8, a0
337; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
338; CHECK-NEXT:    vnsrl.wi v8, v16, 0
339; CHECK-NEXT:    ret
340  %head1 = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
341  %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
342  %vb = sext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
343  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
344  %vd = mul <vscale x 8 x i64> %vb, %vc
345  %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
346  %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
347  %ve = lshr <vscale x 8 x i64> %vd, %splat2
348  %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
349  ret <vscale x 8 x i32> %vf
350}
351