1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
4
5define <vscale x 1 x i1> @vmand_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {
6; CHECK-LABEL: vmand_vv_nxv1i1:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
9; CHECK-NEXT:    vmand.mm v0, v0, v8
10; CHECK-NEXT:    ret
11  %vc = and <vscale x 1 x i1> %va, %vb
12  ret <vscale x 1 x i1> %vc
13}
14
15define <vscale x 2 x i1> @vmand_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {
16; CHECK-LABEL: vmand_vv_nxv2i1:
17; CHECK:       # %bb.0:
18; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
19; CHECK-NEXT:    vmand.mm v0, v0, v8
20; CHECK-NEXT:    ret
21  %vc = and <vscale x 2 x i1> %va, %vb
22  ret <vscale x 2 x i1> %vc
23}
24
25define <vscale x 4 x i1> @vmand_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {
26; CHECK-LABEL: vmand_vv_nxv4i1:
27; CHECK:       # %bb.0:
28; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
29; CHECK-NEXT:    vmand.mm v0, v0, v8
30; CHECK-NEXT:    ret
31  %vc = and <vscale x 4 x i1> %va, %vb
32  ret <vscale x 4 x i1> %vc
33}
34
35define <vscale x 8 x i1> @vmand_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {
36; CHECK-LABEL: vmand_vv_nxv8i1:
37; CHECK:       # %bb.0:
38; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
39; CHECK-NEXT:    vmand.mm v0, v0, v8
40; CHECK-NEXT:    ret
41  %vc = and <vscale x 8 x i1> %va, %vb
42  ret <vscale x 8 x i1> %vc
43}
44
45define <vscale x 16 x i1> @vmand_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {
46; CHECK-LABEL: vmand_vv_nxv16i1:
47; CHECK:       # %bb.0:
48; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
49; CHECK-NEXT:    vmand.mm v0, v0, v8
50; CHECK-NEXT:    ret
51  %vc = and <vscale x 16 x i1> %va, %vb
52  ret <vscale x 16 x i1> %vc
53}
54
55define <vscale x 1 x i1> @vmor_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {
56; CHECK-LABEL: vmor_vv_nxv1i1:
57; CHECK:       # %bb.0:
58; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
59; CHECK-NEXT:    vmor.mm v0, v0, v8
60; CHECK-NEXT:    ret
61  %vc = or <vscale x 1 x i1> %va, %vb
62  ret <vscale x 1 x i1> %vc
63}
64
65define <vscale x 2 x i1> @vmor_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {
66; CHECK-LABEL: vmor_vv_nxv2i1:
67; CHECK:       # %bb.0:
68; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
69; CHECK-NEXT:    vmor.mm v0, v0, v8
70; CHECK-NEXT:    ret
71  %vc = or <vscale x 2 x i1> %va, %vb
72  ret <vscale x 2 x i1> %vc
73}
74
75define <vscale x 4 x i1> @vmor_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {
76; CHECK-LABEL: vmor_vv_nxv4i1:
77; CHECK:       # %bb.0:
78; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
79; CHECK-NEXT:    vmor.mm v0, v0, v8
80; CHECK-NEXT:    ret
81  %vc = or <vscale x 4 x i1> %va, %vb
82  ret <vscale x 4 x i1> %vc
83}
84
85define <vscale x 8 x i1> @vmor_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {
86; CHECK-LABEL: vmor_vv_nxv8i1:
87; CHECK:       # %bb.0:
88; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
89; CHECK-NEXT:    vmor.mm v0, v0, v8
90; CHECK-NEXT:    ret
91  %vc = or <vscale x 8 x i1> %va, %vb
92  ret <vscale x 8 x i1> %vc
93}
94
95define <vscale x 16 x i1> @vmor_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {
96; CHECK-LABEL: vmor_vv_nxv16i1:
97; CHECK:       # %bb.0:
98; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
99; CHECK-NEXT:    vmor.mm v0, v0, v8
100; CHECK-NEXT:    ret
101  %vc = or <vscale x 16 x i1> %va, %vb
102  ret <vscale x 16 x i1> %vc
103}
104
105define <vscale x 1 x i1> @vmxor_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {
106; CHECK-LABEL: vmxor_vv_nxv1i1:
107; CHECK:       # %bb.0:
108; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
109; CHECK-NEXT:    vmxor.mm v0, v0, v8
110; CHECK-NEXT:    ret
111  %vc = xor <vscale x 1 x i1> %va, %vb
112  ret <vscale x 1 x i1> %vc
113}
114
115define <vscale x 2 x i1> @vmxor_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {
116; CHECK-LABEL: vmxor_vv_nxv2i1:
117; CHECK:       # %bb.0:
118; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
119; CHECK-NEXT:    vmxor.mm v0, v0, v8
120; CHECK-NEXT:    ret
121  %vc = xor <vscale x 2 x i1> %va, %vb
122  ret <vscale x 2 x i1> %vc
123}
124
125define <vscale x 4 x i1> @vmxor_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {
126; CHECK-LABEL: vmxor_vv_nxv4i1:
127; CHECK:       # %bb.0:
128; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
129; CHECK-NEXT:    vmxor.mm v0, v0, v8
130; CHECK-NEXT:    ret
131  %vc = xor <vscale x 4 x i1> %va, %vb
132  ret <vscale x 4 x i1> %vc
133}
134
135define <vscale x 8 x i1> @vmxor_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {
136; CHECK-LABEL: vmxor_vv_nxv8i1:
137; CHECK:       # %bb.0:
138; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
139; CHECK-NEXT:    vmxor.mm v0, v0, v8
140; CHECK-NEXT:    ret
141  %vc = xor <vscale x 8 x i1> %va, %vb
142  ret <vscale x 8 x i1> %vc
143}
144
145define <vscale x 16 x i1> @vmxor_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {
146; CHECK-LABEL: vmxor_vv_nxv16i1:
147; CHECK:       # %bb.0:
148; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
149; CHECK-NEXT:    vmxor.mm v0, v0, v8
150; CHECK-NEXT:    ret
151  %vc = xor <vscale x 16 x i1> %va, %vb
152  ret <vscale x 16 x i1> %vc
153}
154
155define <vscale x 1 x i1> @vmnand_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {
156; CHECK-LABEL: vmnand_vv_nxv1i1:
157; CHECK:       # %bb.0:
158; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
159; CHECK-NEXT:    vmnand.mm v0, v0, v8
160; CHECK-NEXT:    ret
161  %vc = and <vscale x 1 x i1> %va, %vb
162  %head = insertelement <vscale x 1 x i1> undef, i1 1, i32 0
163  %splat = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> undef, <vscale x 1 x i32> zeroinitializer
164  %not = xor <vscale x 1 x i1> %vc, %splat
165  ret <vscale x 1 x i1> %not
166}
167
168define <vscale x 2 x i1> @vmnand_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {
169; CHECK-LABEL: vmnand_vv_nxv2i1:
170; CHECK:       # %bb.0:
171; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
172; CHECK-NEXT:    vmnand.mm v0, v0, v8
173; CHECK-NEXT:    ret
174  %vc = and <vscale x 2 x i1> %va, %vb
175  %head = insertelement <vscale x 2 x i1> undef, i1 1, i32 0
176  %splat = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
177  %not = xor <vscale x 2 x i1> %vc, %splat
178  ret <vscale x 2 x i1> %not
179}
180
181define <vscale x 4 x i1> @vmnand_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {
182; CHECK-LABEL: vmnand_vv_nxv4i1:
183; CHECK:       # %bb.0:
184; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
185; CHECK-NEXT:    vmnand.mm v0, v0, v8
186; CHECK-NEXT:    ret
187  %vc = and <vscale x 4 x i1> %va, %vb
188  %head = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
189  %splat = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
190  %not = xor <vscale x 4 x i1> %vc, %splat
191  ret <vscale x 4 x i1> %not
192}
193
194define <vscale x 8 x i1> @vmnand_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {
195; CHECK-LABEL: vmnand_vv_nxv8i1:
196; CHECK:       # %bb.0:
197; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
198; CHECK-NEXT:    vmnand.mm v0, v0, v8
199; CHECK-NEXT:    ret
200  %vc = and <vscale x 8 x i1> %va, %vb
201  %head = insertelement <vscale x 8 x i1> undef, i1 1, i32 0
202  %splat = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
203  %not = xor <vscale x 8 x i1> %vc, %splat
204  ret <vscale x 8 x i1> %not
205}
206
207define <vscale x 16 x i1> @vmnand_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {
208; CHECK-LABEL: vmnand_vv_nxv16i1:
209; CHECK:       # %bb.0:
210; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
211; CHECK-NEXT:    vmnand.mm v0, v0, v8
212; CHECK-NEXT:    ret
213  %vc = and <vscale x 16 x i1> %va, %vb
214  %head = insertelement <vscale x 16 x i1> undef, i1 1, i32 0
215  %splat = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer
216  %not = xor <vscale x 16 x i1> %vc, %splat
217  ret <vscale x 16 x i1> %not
218}
219
220define <vscale x 1 x i1> @vmnor_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {
221; CHECK-LABEL: vmnor_vv_nxv1i1:
222; CHECK:       # %bb.0:
223; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
224; CHECK-NEXT:    vmnor.mm v0, v0, v8
225; CHECK-NEXT:    ret
226  %vc = or <vscale x 1 x i1> %va, %vb
227  %head = insertelement <vscale x 1 x i1> undef, i1 1, i32 0
228  %splat = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> undef, <vscale x 1 x i32> zeroinitializer
229  %not = xor <vscale x 1 x i1> %vc, %splat
230  ret <vscale x 1 x i1> %not
231}
232
233define <vscale x 2 x i1> @vmnor_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {
234; CHECK-LABEL: vmnor_vv_nxv2i1:
235; CHECK:       # %bb.0:
236; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
237; CHECK-NEXT:    vmnor.mm v0, v0, v8
238; CHECK-NEXT:    ret
239  %vc = or <vscale x 2 x i1> %va, %vb
240  %head = insertelement <vscale x 2 x i1> undef, i1 1, i32 0
241  %splat = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
242  %not = xor <vscale x 2 x i1> %vc, %splat
243  ret <vscale x 2 x i1> %not
244}
245
246define <vscale x 4 x i1> @vmnor_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {
247; CHECK-LABEL: vmnor_vv_nxv4i1:
248; CHECK:       # %bb.0:
249; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
250; CHECK-NEXT:    vmnor.mm v0, v0, v8
251; CHECK-NEXT:    ret
252  %vc = or <vscale x 4 x i1> %va, %vb
253  %head = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
254  %splat = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
255  %not = xor <vscale x 4 x i1> %vc, %splat
256  ret <vscale x 4 x i1> %not
257}
258
259define <vscale x 8 x i1> @vmnor_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {
260; CHECK-LABEL: vmnor_vv_nxv8i1:
261; CHECK:       # %bb.0:
262; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
263; CHECK-NEXT:    vmnor.mm v0, v0, v8
264; CHECK-NEXT:    ret
265  %vc = or <vscale x 8 x i1> %va, %vb
266  %head = insertelement <vscale x 8 x i1> undef, i1 1, i32 0
267  %splat = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
268  %not = xor <vscale x 8 x i1> %vc, %splat
269  ret <vscale x 8 x i1> %not
270}
271
272define <vscale x 16 x i1> @vmnor_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {
273; CHECK-LABEL: vmnor_vv_nxv16i1:
274; CHECK:       # %bb.0:
275; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
276; CHECK-NEXT:    vmnor.mm v0, v0, v8
277; CHECK-NEXT:    ret
278  %vc = or <vscale x 16 x i1> %va, %vb
279  %head = insertelement <vscale x 16 x i1> undef, i1 1, i32 0
280  %splat = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer
281  %not = xor <vscale x 16 x i1> %vc, %splat
282  ret <vscale x 16 x i1> %not
283}
284
285define <vscale x 1 x i1> @vmxnor_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {
286; CHECK-LABEL: vmxnor_vv_nxv1i1:
287; CHECK:       # %bb.0:
288; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
289; CHECK-NEXT:    vmxnor.mm v0, v0, v8
290; CHECK-NEXT:    ret
291  %vc = xor <vscale x 1 x i1> %va, %vb
292  %head = insertelement <vscale x 1 x i1> undef, i1 1, i32 0
293  %splat = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> undef, <vscale x 1 x i32> zeroinitializer
294  %not = xor <vscale x 1 x i1> %vc, %splat
295  ret <vscale x 1 x i1> %not
296}
297
298define <vscale x 2 x i1> @vmxnor_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {
299; CHECK-LABEL: vmxnor_vv_nxv2i1:
300; CHECK:       # %bb.0:
301; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
302; CHECK-NEXT:    vmxnor.mm v0, v0, v8
303; CHECK-NEXT:    ret
304  %vc = xor <vscale x 2 x i1> %va, %vb
305  %head = insertelement <vscale x 2 x i1> undef, i1 1, i32 0
306  %splat = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
307  %not = xor <vscale x 2 x i1> %vc, %splat
308  ret <vscale x 2 x i1> %not
309}
310
311define <vscale x 4 x i1> @vmxnor_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {
312; CHECK-LABEL: vmxnor_vv_nxv4i1:
313; CHECK:       # %bb.0:
314; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
315; CHECK-NEXT:    vmxnor.mm v0, v0, v8
316; CHECK-NEXT:    ret
317  %vc = xor <vscale x 4 x i1> %va, %vb
318  %head = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
319  %splat = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
320  %not = xor <vscale x 4 x i1> %vc, %splat
321  ret <vscale x 4 x i1> %not
322}
323
324define <vscale x 8 x i1> @vmxnor_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {
325; CHECK-LABEL: vmxnor_vv_nxv8i1:
326; CHECK:       # %bb.0:
327; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
328; CHECK-NEXT:    vmxnor.mm v0, v0, v8
329; CHECK-NEXT:    ret
330  %vc = xor <vscale x 8 x i1> %va, %vb
331  %head = insertelement <vscale x 8 x i1> undef, i1 1, i32 0
332  %splat = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
333  %not = xor <vscale x 8 x i1> %vc, %splat
334  ret <vscale x 8 x i1> %not
335}
336
337define <vscale x 16 x i1> @vmxnor_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {
338; CHECK-LABEL: vmxnor_vv_nxv16i1:
339; CHECK:       # %bb.0:
340; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
341; CHECK-NEXT:    vmxnor.mm v0, v0, v8
342; CHECK-NEXT:    ret
343  %vc = xor <vscale x 16 x i1> %va, %vb
344  %head = insertelement <vscale x 16 x i1> undef, i1 1, i32 0
345  %splat = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer
346  %not = xor <vscale x 16 x i1> %vc, %splat
347  ret <vscale x 16 x i1> %not
348}
349
350define <vscale x 1 x i1> @vmandn_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {
351; CHECK-LABEL: vmandn_vv_nxv1i1:
352; CHECK:       # %bb.0:
353; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
354; CHECK-NEXT:    vmandn.mm v0, v0, v8
355; CHECK-NEXT:    ret
356  %head = insertelement <vscale x 1 x i1> undef, i1 1, i32 0
357  %splat = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> undef, <vscale x 1 x i32> zeroinitializer
358  %not = xor <vscale x 1 x i1> %vb, %splat
359  %vc = and <vscale x 1 x i1> %va, %not
360  ret <vscale x 1 x i1> %vc
361}
362
363define <vscale x 2 x i1> @vmandn_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {
364; CHECK-LABEL: vmandn_vv_nxv2i1:
365; CHECK:       # %bb.0:
366; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
367; CHECK-NEXT:    vmandn.mm v0, v0, v8
368; CHECK-NEXT:    ret
369  %head = insertelement <vscale x 2 x i1> undef, i1 1, i32 0
370  %splat = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
371  %not = xor <vscale x 2 x i1> %vb, %splat
372  %vc = and <vscale x 2 x i1> %va, %not
373  ret <vscale x 2 x i1> %vc
374}
375
376define <vscale x 4 x i1> @vmandn_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {
377; CHECK-LABEL: vmandn_vv_nxv4i1:
378; CHECK:       # %bb.0:
379; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
380; CHECK-NEXT:    vmandn.mm v0, v0, v8
381; CHECK-NEXT:    ret
382  %head = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
383  %splat = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
384  %not = xor <vscale x 4 x i1> %vb, %splat
385  %vc = and <vscale x 4 x i1> %va, %not
386  ret <vscale x 4 x i1> %vc
387}
388
389define <vscale x 8 x i1> @vmandn_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {
390; CHECK-LABEL: vmandn_vv_nxv8i1:
391; CHECK:       # %bb.0:
392; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
393; CHECK-NEXT:    vmandn.mm v0, v0, v8
394; CHECK-NEXT:    ret
395  %head = insertelement <vscale x 8 x i1> undef, i1 1, i32 0
396  %splat = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
397  %not = xor <vscale x 8 x i1> %vb, %splat
398  %vc = and <vscale x 8 x i1> %va, %not
399  ret <vscale x 8 x i1> %vc
400}
401
402define <vscale x 16 x i1> @vmandn_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {
403; CHECK-LABEL: vmandn_vv_nxv16i1:
404; CHECK:       # %bb.0:
405; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
406; CHECK-NEXT:    vmandn.mm v0, v0, v8
407; CHECK-NEXT:    ret
408  %head = insertelement <vscale x 16 x i1> undef, i1 1, i32 0
409  %splat = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer
410  %not = xor <vscale x 16 x i1> %vb, %splat
411  %vc = and <vscale x 16 x i1> %va, %not
412  ret <vscale x 16 x i1> %vc
413}
414
415define <vscale x 1 x i1> @vmorn_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {
416; CHECK-LABEL: vmorn_vv_nxv1i1:
417; CHECK:       # %bb.0:
418; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
419; CHECK-NEXT:    vmorn.mm v0, v0, v8
420; CHECK-NEXT:    ret
421  %head = insertelement <vscale x 1 x i1> undef, i1 1, i32 0
422  %splat = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> undef, <vscale x 1 x i32> zeroinitializer
423  %not = xor <vscale x 1 x i1> %vb, %splat
424  %vc = or <vscale x 1 x i1> %va, %not
425  ret <vscale x 1 x i1> %vc
426}
427
428define <vscale x 2 x i1> @vmorn_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {
429; CHECK-LABEL: vmorn_vv_nxv2i1:
430; CHECK:       # %bb.0:
431; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
432; CHECK-NEXT:    vmorn.mm v0, v0, v8
433; CHECK-NEXT:    ret
434  %head = insertelement <vscale x 2 x i1> undef, i1 1, i32 0
435  %splat = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
436  %not = xor <vscale x 2 x i1> %vb, %splat
437  %vc = or <vscale x 2 x i1> %va, %not
438  ret <vscale x 2 x i1> %vc
439}
440
441define <vscale x 4 x i1> @vmorn_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {
442; CHECK-LABEL: vmorn_vv_nxv4i1:
443; CHECK:       # %bb.0:
444; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
445; CHECK-NEXT:    vmorn.mm v0, v0, v8
446; CHECK-NEXT:    ret
447  %head = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
448  %splat = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
449  %not = xor <vscale x 4 x i1> %vb, %splat
450  %vc = or <vscale x 4 x i1> %va, %not
451  ret <vscale x 4 x i1> %vc
452}
453
454define <vscale x 8 x i1> @vmorn_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {
455; CHECK-LABEL: vmorn_vv_nxv8i1:
456; CHECK:       # %bb.0:
457; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
458; CHECK-NEXT:    vmorn.mm v0, v0, v8
459; CHECK-NEXT:    ret
460  %head = insertelement <vscale x 8 x i1> undef, i1 1, i32 0
461  %splat = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
462  %not = xor <vscale x 8 x i1> %vb, %splat
463  %vc = or <vscale x 8 x i1> %va, %not
464  ret <vscale x 8 x i1> %vc
465}
466
467define <vscale x 16 x i1> @vmorn_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {
468; CHECK-LABEL: vmorn_vv_nxv16i1:
469; CHECK:       # %bb.0:
470; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
471; CHECK-NEXT:    vmorn.mm v0, v0, v8
472; CHECK-NEXT:    ret
473  %head = insertelement <vscale x 16 x i1> undef, i1 1, i32 0
474  %splat = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer
475  %not = xor <vscale x 16 x i1> %vb, %splat
476  %vc = or <vscale x 16 x i1> %va, %not
477  ret <vscale x 16 x i1> %vc
478}
479
480