1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
5; RUN:     -verify-machineinstrs < %s | FileCheck %s
6
7define <vscale x 1 x half> @select_nxv1f16(i1 zeroext %c, <vscale x 1 x half> %a, <vscale x 1 x half> %b) {
8; CHECK-LABEL: select_nxv1f16:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
11; CHECK-NEXT:    vmv.v.x v10, a0
12; CHECK-NEXT:    vmsne.vi v0, v10, 0
13; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
14; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
15; CHECK-NEXT:    ret
16  %v = select i1 %c, <vscale x 1 x half> %a, <vscale x 1 x half> %b
17  ret <vscale x 1 x half> %v
18}
19
20define <vscale x 1 x half> @selectcc_nxv1f16(half %a, half %b, <vscale x 1 x half> %c, <vscale x 1 x half> %d) {
21; CHECK-LABEL: selectcc_nxv1f16:
22; CHECK:       # %bb.0:
23; CHECK-NEXT:    feq.h a0, fa0, fa1
24; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
25; CHECK-NEXT:    vmv.v.x v10, a0
26; CHECK-NEXT:    vmsne.vi v0, v10, 0
27; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
28; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
29; CHECK-NEXT:    ret
30  %cmp = fcmp oeq half %a, %b
31  %v = select i1 %cmp, <vscale x 1 x half> %c, <vscale x 1 x half> %d
32  ret <vscale x 1 x half> %v
33}
34
35define <vscale x 2 x half> @select_nxv2f16(i1 zeroext %c, <vscale x 2 x half> %a, <vscale x 2 x half> %b) {
36; CHECK-LABEL: select_nxv2f16:
37; CHECK:       # %bb.0:
38; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
39; CHECK-NEXT:    vmv.v.x v10, a0
40; CHECK-NEXT:    vmsne.vi v0, v10, 0
41; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
42; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
43; CHECK-NEXT:    ret
44  %v = select i1 %c, <vscale x 2 x half> %a, <vscale x 2 x half> %b
45  ret <vscale x 2 x half> %v
46}
47
48define <vscale x 2 x half> @selectcc_nxv2f16(half %a, half %b, <vscale x 2 x half> %c, <vscale x 2 x half> %d) {
49; CHECK-LABEL: selectcc_nxv2f16:
50; CHECK:       # %bb.0:
51; CHECK-NEXT:    feq.h a0, fa0, fa1
52; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
53; CHECK-NEXT:    vmv.v.x v10, a0
54; CHECK-NEXT:    vmsne.vi v0, v10, 0
55; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
56; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
57; CHECK-NEXT:    ret
58  %cmp = fcmp oeq half %a, %b
59  %v = select i1 %cmp, <vscale x 2 x half> %c, <vscale x 2 x half> %d
60  ret <vscale x 2 x half> %v
61}
62
63define <vscale x 4 x half> @select_nxv4f16(i1 zeroext %c, <vscale x 4 x half> %a, <vscale x 4 x half> %b) {
64; CHECK-LABEL: select_nxv4f16:
65; CHECK:       # %bb.0:
66; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
67; CHECK-NEXT:    vmv.v.x v10, a0
68; CHECK-NEXT:    vmsne.vi v0, v10, 0
69; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
70; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
71; CHECK-NEXT:    ret
72  %v = select i1 %c, <vscale x 4 x half> %a, <vscale x 4 x half> %b
73  ret <vscale x 4 x half> %v
74}
75
76define <vscale x 4 x half> @selectcc_nxv4f16(half %a, half %b, <vscale x 4 x half> %c, <vscale x 4 x half> %d) {
77; CHECK-LABEL: selectcc_nxv4f16:
78; CHECK:       # %bb.0:
79; CHECK-NEXT:    feq.h a0, fa0, fa1
80; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
81; CHECK-NEXT:    vmv.v.x v10, a0
82; CHECK-NEXT:    vmsne.vi v0, v10, 0
83; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
84; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
85; CHECK-NEXT:    ret
86  %cmp = fcmp oeq half %a, %b
87  %v = select i1 %cmp, <vscale x 4 x half> %c, <vscale x 4 x half> %d
88  ret <vscale x 4 x half> %v
89}
90
91define <vscale x 8 x half> @select_nxv8f16(i1 zeroext %c, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
92; CHECK-LABEL: select_nxv8f16:
93; CHECK:       # %bb.0:
94; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
95; CHECK-NEXT:    vmv.v.x v12, a0
96; CHECK-NEXT:    vmsne.vi v0, v12, 0
97; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
98; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
99; CHECK-NEXT:    ret
100  %v = select i1 %c, <vscale x 8 x half> %a, <vscale x 8 x half> %b
101  ret <vscale x 8 x half> %v
102}
103
104define <vscale x 8 x half> @selectcc_nxv8f16(half %a, half %b, <vscale x 8 x half> %c, <vscale x 8 x half> %d) {
105; CHECK-LABEL: selectcc_nxv8f16:
106; CHECK:       # %bb.0:
107; CHECK-NEXT:    feq.h a0, fa0, fa1
108; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
109; CHECK-NEXT:    vmv.v.x v12, a0
110; CHECK-NEXT:    vmsne.vi v0, v12, 0
111; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
112; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
113; CHECK-NEXT:    ret
114  %cmp = fcmp oeq half %a, %b
115  %v = select i1 %cmp, <vscale x 8 x half> %c, <vscale x 8 x half> %d
116  ret <vscale x 8 x half> %v
117}
118
119define <vscale x 16 x half> @select_nxv16f16(i1 zeroext %c, <vscale x 16 x half> %a, <vscale x 16 x half> %b) {
120; CHECK-LABEL: select_nxv16f16:
121; CHECK:       # %bb.0:
122; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
123; CHECK-NEXT:    vmv.v.x v16, a0
124; CHECK-NEXT:    vmsne.vi v0, v16, 0
125; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
126; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
127; CHECK-NEXT:    ret
128  %v = select i1 %c, <vscale x 16 x half> %a, <vscale x 16 x half> %b
129  ret <vscale x 16 x half> %v
130}
131
132define <vscale x 16 x half> @selectcc_nxv16f16(half %a, half %b, <vscale x 16 x half> %c, <vscale x 16 x half> %d) {
133; CHECK-LABEL: selectcc_nxv16f16:
134; CHECK:       # %bb.0:
135; CHECK-NEXT:    feq.h a0, fa0, fa1
136; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
137; CHECK-NEXT:    vmv.v.x v16, a0
138; CHECK-NEXT:    vmsne.vi v0, v16, 0
139; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
140; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
141; CHECK-NEXT:    ret
142  %cmp = fcmp oeq half %a, %b
143  %v = select i1 %cmp, <vscale x 16 x half> %c, <vscale x 16 x half> %d
144  ret <vscale x 16 x half> %v
145}
146
147define <vscale x 32 x half> @select_nxv32f16(i1 zeroext %c, <vscale x 32 x half> %a, <vscale x 32 x half> %b) {
148; CHECK-LABEL: select_nxv32f16:
149; CHECK:       # %bb.0:
150; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
151; CHECK-NEXT:    vmv.v.x v24, a0
152; CHECK-NEXT:    vmsne.vi v0, v24, 0
153; CHECK-NEXT:    vsetvli zero, zero, e16, m8, ta, mu
154; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
155; CHECK-NEXT:    ret
156  %v = select i1 %c, <vscale x 32 x half> %a, <vscale x 32 x half> %b
157  ret <vscale x 32 x half> %v
158}
159
160define <vscale x 32 x half> @selectcc_nxv32f16(half %a, half %b, <vscale x 32 x half> %c, <vscale x 32 x half> %d) {
161; CHECK-LABEL: selectcc_nxv32f16:
162; CHECK:       # %bb.0:
163; CHECK-NEXT:    feq.h a0, fa0, fa1
164; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
165; CHECK-NEXT:    vmv.v.x v24, a0
166; CHECK-NEXT:    vmsne.vi v0, v24, 0
167; CHECK-NEXT:    vsetvli zero, zero, e16, m8, ta, mu
168; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
169; CHECK-NEXT:    ret
170  %cmp = fcmp oeq half %a, %b
171  %v = select i1 %cmp, <vscale x 32 x half> %c, <vscale x 32 x half> %d
172  ret <vscale x 32 x half> %v
173}
174
175define <vscale x 1 x float> @select_nxv1f32(i1 zeroext %c, <vscale x 1 x float> %a, <vscale x 1 x float> %b) {
176; CHECK-LABEL: select_nxv1f32:
177; CHECK:       # %bb.0:
178; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
179; CHECK-NEXT:    vmv.v.x v10, a0
180; CHECK-NEXT:    vmsne.vi v0, v10, 0
181; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
182; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
183; CHECK-NEXT:    ret
184  %v = select i1 %c, <vscale x 1 x float> %a, <vscale x 1 x float> %b
185  ret <vscale x 1 x float> %v
186}
187
188define <vscale x 1 x float> @selectcc_nxv1f32(float %a, float %b, <vscale x 1 x float> %c, <vscale x 1 x float> %d) {
189; CHECK-LABEL: selectcc_nxv1f32:
190; CHECK:       # %bb.0:
191; CHECK-NEXT:    feq.s a0, fa0, fa1
192; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
193; CHECK-NEXT:    vmv.v.x v10, a0
194; CHECK-NEXT:    vmsne.vi v0, v10, 0
195; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
196; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
197; CHECK-NEXT:    ret
198  %cmp = fcmp oeq float %a, %b
199  %v = select i1 %cmp, <vscale x 1 x float> %c, <vscale x 1 x float> %d
200  ret <vscale x 1 x float> %v
201}
202
203define <vscale x 2 x float> @select_nxv2f32(i1 zeroext %c, <vscale x 2 x float> %a, <vscale x 2 x float> %b) {
204; CHECK-LABEL: select_nxv2f32:
205; CHECK:       # %bb.0:
206; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
207; CHECK-NEXT:    vmv.v.x v10, a0
208; CHECK-NEXT:    vmsne.vi v0, v10, 0
209; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
210; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
211; CHECK-NEXT:    ret
212  %v = select i1 %c, <vscale x 2 x float> %a, <vscale x 2 x float> %b
213  ret <vscale x 2 x float> %v
214}
215
216define <vscale x 2 x float> @selectcc_nxv2f32(float %a, float %b, <vscale x 2 x float> %c, <vscale x 2 x float> %d) {
217; CHECK-LABEL: selectcc_nxv2f32:
218; CHECK:       # %bb.0:
219; CHECK-NEXT:    feq.s a0, fa0, fa1
220; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
221; CHECK-NEXT:    vmv.v.x v10, a0
222; CHECK-NEXT:    vmsne.vi v0, v10, 0
223; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
224; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
225; CHECK-NEXT:    ret
226  %cmp = fcmp oeq float %a, %b
227  %v = select i1 %cmp, <vscale x 2 x float> %c, <vscale x 2 x float> %d
228  ret <vscale x 2 x float> %v
229}
230
231define <vscale x 4 x float> @select_nxv4f32(i1 zeroext %c, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
232; CHECK-LABEL: select_nxv4f32:
233; CHECK:       # %bb.0:
234; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
235; CHECK-NEXT:    vmv.v.x v12, a0
236; CHECK-NEXT:    vmsne.vi v0, v12, 0
237; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
238; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
239; CHECK-NEXT:    ret
240  %v = select i1 %c, <vscale x 4 x float> %a, <vscale x 4 x float> %b
241  ret <vscale x 4 x float> %v
242}
243
244define <vscale x 4 x float> @selectcc_nxv4f32(float %a, float %b, <vscale x 4 x float> %c, <vscale x 4 x float> %d) {
245; CHECK-LABEL: selectcc_nxv4f32:
246; CHECK:       # %bb.0:
247; CHECK-NEXT:    feq.s a0, fa0, fa1
248; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
249; CHECK-NEXT:    vmv.v.x v12, a0
250; CHECK-NEXT:    vmsne.vi v0, v12, 0
251; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
252; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
253; CHECK-NEXT:    ret
254  %cmp = fcmp oeq float %a, %b
255  %v = select i1 %cmp, <vscale x 4 x float> %c, <vscale x 4 x float> %d
256  ret <vscale x 4 x float> %v
257}
258
259define <vscale x 8 x float> @select_nxv8f32(i1 zeroext %c, <vscale x 8 x float> %a, <vscale x 8 x float> %b) {
260; CHECK-LABEL: select_nxv8f32:
261; CHECK:       # %bb.0:
262; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
263; CHECK-NEXT:    vmv.v.x v16, a0
264; CHECK-NEXT:    vmsne.vi v0, v16, 0
265; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
266; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
267; CHECK-NEXT:    ret
268  %v = select i1 %c, <vscale x 8 x float> %a, <vscale x 8 x float> %b
269  ret <vscale x 8 x float> %v
270}
271
272define <vscale x 8 x float> @selectcc_nxv8f32(float %a, float %b, <vscale x 8 x float> %c, <vscale x 8 x float> %d) {
273; CHECK-LABEL: selectcc_nxv8f32:
274; CHECK:       # %bb.0:
275; CHECK-NEXT:    feq.s a0, fa0, fa1
276; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
277; CHECK-NEXT:    vmv.v.x v16, a0
278; CHECK-NEXT:    vmsne.vi v0, v16, 0
279; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
280; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
281; CHECK-NEXT:    ret
282  %cmp = fcmp oeq float %a, %b
283  %v = select i1 %cmp, <vscale x 8 x float> %c, <vscale x 8 x float> %d
284  ret <vscale x 8 x float> %v
285}
286
287define <vscale x 16 x float> @select_nxv16f32(i1 zeroext %c, <vscale x 16 x float> %a, <vscale x 16 x float> %b) {
288; CHECK-LABEL: select_nxv16f32:
289; CHECK:       # %bb.0:
290; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
291; CHECK-NEXT:    vmv.v.x v24, a0
292; CHECK-NEXT:    vmsne.vi v0, v24, 0
293; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
294; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
295; CHECK-NEXT:    ret
296  %v = select i1 %c, <vscale x 16 x float> %a, <vscale x 16 x float> %b
297  ret <vscale x 16 x float> %v
298}
299
300define <vscale x 16 x float> @selectcc_nxv16f32(float %a, float %b, <vscale x 16 x float> %c, <vscale x 16 x float> %d) {
301; CHECK-LABEL: selectcc_nxv16f32:
302; CHECK:       # %bb.0:
303; CHECK-NEXT:    feq.s a0, fa0, fa1
304; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
305; CHECK-NEXT:    vmv.v.x v24, a0
306; CHECK-NEXT:    vmsne.vi v0, v24, 0
307; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
308; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
309; CHECK-NEXT:    ret
310  %cmp = fcmp oeq float %a, %b
311  %v = select i1 %cmp, <vscale x 16 x float> %c, <vscale x 16 x float> %d
312  ret <vscale x 16 x float> %v
313}
314
315define <vscale x 1 x double> @select_nxv1f64(i1 zeroext %c, <vscale x 1 x double> %a, <vscale x 1 x double> %b) {
316; CHECK-LABEL: select_nxv1f64:
317; CHECK:       # %bb.0:
318; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
319; CHECK-NEXT:    vmv.v.x v10, a0
320; CHECK-NEXT:    vmsne.vi v0, v10, 0
321; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
322; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
323; CHECK-NEXT:    ret
324  %v = select i1 %c, <vscale x 1 x double> %a, <vscale x 1 x double> %b
325  ret <vscale x 1 x double> %v
326}
327
328define <vscale x 1 x double> @selectcc_nxv1f64(double %a, double %b, <vscale x 1 x double> %c, <vscale x 1 x double> %d) {
329; CHECK-LABEL: selectcc_nxv1f64:
330; CHECK:       # %bb.0:
331; CHECK-NEXT:    feq.d a0, fa0, fa1
332; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
333; CHECK-NEXT:    vmv.v.x v10, a0
334; CHECK-NEXT:    vmsne.vi v0, v10, 0
335; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
336; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
337; CHECK-NEXT:    ret
338  %cmp = fcmp oeq double %a, %b
339  %v = select i1 %cmp, <vscale x 1 x double> %c, <vscale x 1 x double> %d
340  ret <vscale x 1 x double> %v
341}
342
343define <vscale x 2 x double> @select_nxv2f64(i1 zeroext %c, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
344; CHECK-LABEL: select_nxv2f64:
345; CHECK:       # %bb.0:
346; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
347; CHECK-NEXT:    vmv.v.x v12, a0
348; CHECK-NEXT:    vmsne.vi v0, v12, 0
349; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, mu
350; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
351; CHECK-NEXT:    ret
352  %v = select i1 %c, <vscale x 2 x double> %a, <vscale x 2 x double> %b
353  ret <vscale x 2 x double> %v
354}
355
356define <vscale x 2 x double> @selectcc_nxv2f64(double %a, double %b, <vscale x 2 x double> %c, <vscale x 2 x double> %d) {
357; CHECK-LABEL: selectcc_nxv2f64:
358; CHECK:       # %bb.0:
359; CHECK-NEXT:    feq.d a0, fa0, fa1
360; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
361; CHECK-NEXT:    vmv.v.x v12, a0
362; CHECK-NEXT:    vmsne.vi v0, v12, 0
363; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, mu
364; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
365; CHECK-NEXT:    ret
366  %cmp = fcmp oeq double %a, %b
367  %v = select i1 %cmp, <vscale x 2 x double> %c, <vscale x 2 x double> %d
368  ret <vscale x 2 x double> %v
369}
370
371define <vscale x 4 x double> @select_nxv4f64(i1 zeroext %c, <vscale x 4 x double> %a, <vscale x 4 x double> %b) {
372; CHECK-LABEL: select_nxv4f64:
373; CHECK:       # %bb.0:
374; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
375; CHECK-NEXT:    vmv.v.x v16, a0
376; CHECK-NEXT:    vmsne.vi v0, v16, 0
377; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, mu
378; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
379; CHECK-NEXT:    ret
380  %v = select i1 %c, <vscale x 4 x double> %a, <vscale x 4 x double> %b
381  ret <vscale x 4 x double> %v
382}
383
384define <vscale x 4 x double> @selectcc_nxv4f64(double %a, double %b, <vscale x 4 x double> %c, <vscale x 4 x double> %d) {
385; CHECK-LABEL: selectcc_nxv4f64:
386; CHECK:       # %bb.0:
387; CHECK-NEXT:    feq.d a0, fa0, fa1
388; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
389; CHECK-NEXT:    vmv.v.x v16, a0
390; CHECK-NEXT:    vmsne.vi v0, v16, 0
391; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, mu
392; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
393; CHECK-NEXT:    ret
394  %cmp = fcmp oeq double %a, %b
395  %v = select i1 %cmp, <vscale x 4 x double> %c, <vscale x 4 x double> %d
396  ret <vscale x 4 x double> %v
397}
398
399define <vscale x 8 x double> @select_nxv8f64(i1 zeroext %c, <vscale x 8 x double> %a, <vscale x 8 x double> %b) {
400; CHECK-LABEL: select_nxv8f64:
401; CHECK:       # %bb.0:
402; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
403; CHECK-NEXT:    vmv.v.x v24, a0
404; CHECK-NEXT:    vmsne.vi v0, v24, 0
405; CHECK-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
406; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
407; CHECK-NEXT:    ret
408  %v = select i1 %c, <vscale x 8 x double> %a, <vscale x 8 x double> %b
409  ret <vscale x 8 x double> %v
410}
411
412define <vscale x 8 x double> @selectcc_nxv8f64(double %a, double %b, <vscale x 8 x double> %c, <vscale x 8 x double> %d) {
413; CHECK-LABEL: selectcc_nxv8f64:
414; CHECK:       # %bb.0:
415; CHECK-NEXT:    feq.d a0, fa0, fa1
416; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
417; CHECK-NEXT:    vmv.v.x v24, a0
418; CHECK-NEXT:    vmsne.vi v0, v24, 0
419; CHECK-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
420; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
421; CHECK-NEXT:    ret
422  %cmp = fcmp oeq double %a, %b
423  %v = select i1 %cmp, <vscale x 8 x double> %c, <vscale x 8 x double> %d
424  ret <vscale x 8 x double> %v
425}
426