1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -O2 < %s \
3; RUN:   | FileCheck %s -check-prefix=RV64IV
4
5declare <vscale x 64 x i8> @llvm.riscv.vmacc.nxv64i8.nxv64i8(
6  <vscale x 64 x i8>,
7  <vscale x 64 x i8>,
8  <vscale x 64 x i8>,
9  i64);
10
11define <vscale x 64 x i8> @callee(<vscale x 64 x i8> %arg0, <vscale x 64 x i8> %arg1, <vscale x 64 x i8> %arg2) {
12; RV64IV-LABEL: callee:
13; RV64IV:       # %bb.0:
14; RV64IV-NEXT:    vl8r.v v24, (a0)
15; RV64IV-NEXT:    addi a0, zero, 1024
16; RV64IV-NEXT:    vsetvli a0, a0, e8,m8,tu,mu
17; RV64IV-NEXT:    vmacc.vv v8, v16, v24
18; RV64IV-NEXT:    ret
19  %ret = call <vscale x 64 x i8> @llvm.riscv.vmacc.nxv64i8.nxv64i8(
20                                  <vscale x 64 x i8> %arg0,
21                                  <vscale x 64 x i8> %arg1,
22                                  <vscale x 64 x i8> %arg2, i64 1024)
23  ret <vscale x 64 x i8> %ret
24}
25
26define <vscale x 64 x i8> @caller() {
27; RV64IV-LABEL: caller:
28; RV64IV:       # %bb.0:
29; RV64IV-NEXT:    addi sp, sp, -64
30; RV64IV-NEXT:    .cfi_def_cfa_offset 64
31; RV64IV-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
32; RV64IV-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
33; RV64IV-NEXT:    .cfi_offset ra, -8
34; RV64IV-NEXT:    .cfi_offset s0, -16
35; RV64IV-NEXT:    addi s0, sp, 64
36; RV64IV-NEXT:    .cfi_def_cfa s0, 0
37; RV64IV-NEXT:    andi sp, sp, -64
38; RV64IV-NEXT:    csrr a0, vlenb
39; RV64IV-NEXT:    slli a0, a0, 5
40; RV64IV-NEXT:    sub sp, sp, a0
41; RV64IV-NEXT:    csrr a0, vlenb
42; RV64IV-NEXT:    addi a1, zero, 24
43; RV64IV-NEXT:    mul a0, a0, a1
44; RV64IV-NEXT:    add a0, sp, a0
45; RV64IV-NEXT:    vl8r.v v8, (a0)
46; RV64IV-NEXT:    csrr a0, vlenb
47; RV64IV-NEXT:    slli a0, a0, 4
48; RV64IV-NEXT:    add a0, sp, a0
49; RV64IV-NEXT:    vl8r.v v16, (a0)
50; RV64IV-NEXT:    csrr a0, vlenb
51; RV64IV-NEXT:    slli a0, a0, 3
52; RV64IV-NEXT:    add a0, sp, a0
53; RV64IV-NEXT:    vl8r.v v24, (a0)
54; RV64IV-NEXT:    mv a0, sp
55; RV64IV-NEXT:    vs8r.v v24, (sp)
56; RV64IV-NEXT:    call callee@plt
57; RV64IV-NEXT:    addi sp, s0, -64
58; RV64IV-NEXT:    ld s0, 48(sp) # 8-byte Folded Reload
59; RV64IV-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
60; RV64IV-NEXT:    addi sp, sp, 64
61; RV64IV-NEXT:    ret
62  %local0 = alloca <vscale x 64 x i8>
63  %local1 = alloca <vscale x 64 x i8>
64  %local2 = alloca <vscale x 64 x i8>
65  %arg0 = load volatile <vscale x 64 x i8>, <vscale x 64 x i8>* %local0
66  %arg1 = load volatile <vscale x 64 x i8>, <vscale x 64 x i8>* %local1
67  %arg2 = load volatile <vscale x 64 x i8>, <vscale x 64 x i8>* %local2
68  %ret = call <vscale x 64 x i8> @callee(<vscale x 64 x i8> %arg0,
69                                         <vscale x 64 x i8> %arg1,
70                                         <vscale x 64 x i8> %arg2)
71  ret <vscale x 64 x i8> %ret
72}
73