1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple riscv32 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -mtriple riscv64 -mattr=+m,+d,+zfh,+experimental-zvfh,+v -verify-machineinstrs < %s | FileCheck %s
4
5define <vscale x 4 x i32> @extract_nxv8i32_nxv4i32_0(<vscale x 8 x i32> %vec) {
6; CHECK-LABEL: extract_nxv8i32_nxv4i32_0:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m4
9; CHECK-NEXT:    ret
10  %c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 0)
11  ret <vscale x 4 x i32> %c
12}
13
14define <vscale x 4 x i32> @extract_nxv8i32_nxv4i32_4(<vscale x 8 x i32> %vec) {
15; CHECK-LABEL: extract_nxv8i32_nxv4i32_4:
16; CHECK:       # %bb.0:
17; CHECK-NEXT:    vmv2r.v v8, v10
18; CHECK-NEXT:    ret
19  %c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 4)
20  ret <vscale x 4 x i32> %c
21}
22
23define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_0(<vscale x 8 x i32> %vec) {
24; CHECK-LABEL: extract_nxv8i32_nxv2i32_0:
25; CHECK:       # %bb.0:
26; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8m4
27; CHECK-NEXT:    ret
28  %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 0)
29  ret <vscale x 2 x i32> %c
30}
31
32define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_2(<vscale x 8 x i32> %vec) {
33; CHECK-LABEL: extract_nxv8i32_nxv2i32_2:
34; CHECK:       # %bb.0:
35; CHECK-NEXT:    vmv1r.v v8, v9
36; CHECK-NEXT:    ret
37  %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 2)
38  ret <vscale x 2 x i32> %c
39}
40
41define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_4(<vscale x 8 x i32> %vec) {
42; CHECK-LABEL: extract_nxv8i32_nxv2i32_4:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    vmv1r.v v8, v10
45; CHECK-NEXT:    ret
46  %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 4)
47  ret <vscale x 2 x i32> %c
48}
49
50define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_6(<vscale x 8 x i32> %vec) {
51; CHECK-LABEL: extract_nxv8i32_nxv2i32_6:
52; CHECK:       # %bb.0:
53; CHECK-NEXT:    vmv1r.v v8, v11
54; CHECK-NEXT:    ret
55  %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 6)
56  ret <vscale x 2 x i32> %c
57}
58
59define <vscale x 8 x i32> @extract_nxv16i32_nxv8i32_0(<vscale x 16 x i32> %vec) {
60; CHECK-LABEL: extract_nxv16i32_nxv8i32_0:
61; CHECK:       # %bb.0:
62; CHECK-NEXT:    # kill: def $v8m4 killed $v8m4 killed $v8m8
63; CHECK-NEXT:    ret
64  %c = call <vscale x 8 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)
65  ret <vscale x 8 x i32> %c
66}
67
68define <vscale x 8 x i32> @extract_nxv16i32_nxv8i32_8(<vscale x 16 x i32> %vec) {
69; CHECK-LABEL: extract_nxv16i32_nxv8i32_8:
70; CHECK:       # %bb.0:
71; CHECK-NEXT:    vmv4r.v v8, v12
72; CHECK-NEXT:    ret
73  %c = call <vscale x 8 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8)
74  ret <vscale x 8 x i32> %c
75}
76
77define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_0(<vscale x 16 x i32> %vec) {
78; CHECK-LABEL: extract_nxv16i32_nxv4i32_0:
79; CHECK:       # %bb.0:
80; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m8
81; CHECK-NEXT:    ret
82  %c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)
83  ret <vscale x 4 x i32> %c
84}
85
86define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_4(<vscale x 16 x i32> %vec) {
87; CHECK-LABEL: extract_nxv16i32_nxv4i32_4:
88; CHECK:       # %bb.0:
89; CHECK-NEXT:    vmv2r.v v8, v10
90; CHECK-NEXT:    ret
91  %c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 4)
92  ret <vscale x 4 x i32> %c
93}
94
95define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_8(<vscale x 16 x i32> %vec) {
96; CHECK-LABEL: extract_nxv16i32_nxv4i32_8:
97; CHECK:       # %bb.0:
98; CHECK-NEXT:    vmv2r.v v8, v12
99; CHECK-NEXT:    ret
100  %c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8)
101  ret <vscale x 4 x i32> %c
102}
103
104define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_12(<vscale x 16 x i32> %vec) {
105; CHECK-LABEL: extract_nxv16i32_nxv4i32_12:
106; CHECK:       # %bb.0:
107; CHECK-NEXT:    vmv2r.v v8, v14
108; CHECK-NEXT:    ret
109  %c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 12)
110  ret <vscale x 4 x i32> %c
111}
112
113define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_0(<vscale x 16 x i32> %vec) {
114; CHECK-LABEL: extract_nxv16i32_nxv2i32_0:
115; CHECK:       # %bb.0:
116; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8m8
117; CHECK-NEXT:    ret
118  %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)
119  ret <vscale x 2 x i32> %c
120}
121
122define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_2(<vscale x 16 x i32> %vec) {
123; CHECK-LABEL: extract_nxv16i32_nxv2i32_2:
124; CHECK:       # %bb.0:
125; CHECK-NEXT:    vmv1r.v v8, v9
126; CHECK-NEXT:    ret
127  %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 2)
128  ret <vscale x 2 x i32> %c
129}
130
131define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_4(<vscale x 16 x i32> %vec) {
132; CHECK-LABEL: extract_nxv16i32_nxv2i32_4:
133; CHECK:       # %bb.0:
134; CHECK-NEXT:    vmv1r.v v8, v10
135; CHECK-NEXT:    ret
136  %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 4)
137  ret <vscale x 2 x i32> %c
138}
139
140define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_6(<vscale x 16 x i32> %vec) {
141; CHECK-LABEL: extract_nxv16i32_nxv2i32_6:
142; CHECK:       # %bb.0:
143; CHECK-NEXT:    vmv1r.v v8, v11
144; CHECK-NEXT:    ret
145  %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 6)
146  ret <vscale x 2 x i32> %c
147}
148
149define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_8(<vscale x 16 x i32> %vec) {
150; CHECK-LABEL: extract_nxv16i32_nxv2i32_8:
151; CHECK:       # %bb.0:
152; CHECK-NEXT:    vmv1r.v v8, v12
153; CHECK-NEXT:    ret
154  %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8)
155  ret <vscale x 2 x i32> %c
156}
157
158define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_10(<vscale x 16 x i32> %vec) {
159; CHECK-LABEL: extract_nxv16i32_nxv2i32_10:
160; CHECK:       # %bb.0:
161; CHECK-NEXT:    vmv1r.v v8, v13
162; CHECK-NEXT:    ret
163  %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 10)
164  ret <vscale x 2 x i32> %c
165}
166
167define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_12(<vscale x 16 x i32> %vec) {
168; CHECK-LABEL: extract_nxv16i32_nxv2i32_12:
169; CHECK:       # %bb.0:
170; CHECK-NEXT:    vmv1r.v v8, v14
171; CHECK-NEXT:    ret
172  %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 12)
173  ret <vscale x 2 x i32> %c
174}
175
176define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_14(<vscale x 16 x i32> %vec) {
177; CHECK-LABEL: extract_nxv16i32_nxv2i32_14:
178; CHECK:       # %bb.0:
179; CHECK-NEXT:    vmv1r.v v8, v15
180; CHECK-NEXT:    ret
181  %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 14)
182  ret <vscale x 2 x i32> %c
183}
184
185define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_0(<vscale x 16 x i32> %vec) {
186; CHECK-LABEL: extract_nxv16i32_nxv1i32_0:
187; CHECK:       # %bb.0:
188; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8m8
189; CHECK-NEXT:    ret
190  %c = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)
191  ret <vscale x 1 x i32> %c
192}
193
194define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_1(<vscale x 16 x i32> %vec) {
195; CHECK-LABEL: extract_nxv16i32_nxv1i32_1:
196; CHECK:       # %bb.0:
197; CHECK-NEXT:    csrr a0, vlenb
198; CHECK-NEXT:    srli a0, a0, 3
199; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
200; CHECK-NEXT:    vslidedown.vx v8, v8, a0
201; CHECK-NEXT:    ret
202  %c = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 1)
203  ret <vscale x 1 x i32> %c
204}
205
206define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_3(<vscale x 16 x i32> %vec) {
207; CHECK-LABEL: extract_nxv16i32_nxv1i32_3:
208; CHECK:       # %bb.0:
209; CHECK-NEXT:    csrr a0, vlenb
210; CHECK-NEXT:    srli a0, a0, 3
211; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
212; CHECK-NEXT:    vslidedown.vx v8, v9, a0
213; CHECK-NEXT:    ret
214  %c = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 3)
215  ret <vscale x 1 x i32> %c
216}
217
218define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_15(<vscale x 16 x i32> %vec) {
219; CHECK-LABEL: extract_nxv16i32_nxv1i32_15:
220; CHECK:       # %bb.0:
221; CHECK-NEXT:    csrr a0, vlenb
222; CHECK-NEXT:    srli a0, a0, 3
223; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
224; CHECK-NEXT:    vslidedown.vx v8, v15, a0
225; CHECK-NEXT:    ret
226  %c = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 15)
227  ret <vscale x 1 x i32> %c
228}
229
230define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_2(<vscale x 16 x i32> %vec) {
231; CHECK-LABEL: extract_nxv16i32_nxv1i32_2:
232; CHECK:       # %bb.0:
233; CHECK-NEXT:    vmv1r.v v8, v9
234; CHECK-NEXT:    ret
235  %c = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 2)
236  ret <vscale x 1 x i32> %c
237}
238
239define <vscale x 1 x i32> @extract_nxv2i32_nxv1i32_0(<vscale x 2 x i32> %vec) {
240; CHECK-LABEL: extract_nxv2i32_nxv1i32_0:
241; CHECK:       # %bb.0:
242; CHECK-NEXT:    ret
243  %c = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> %vec, i64 0)
244  ret <vscale x 1 x i32> %c
245}
246
247define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_0(<vscale x 32 x i8> %vec) {
248; CHECK-LABEL: extract_nxv32i8_nxv2i8_0:
249; CHECK:       # %bb.0:
250; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8m4
251; CHECK-NEXT:    ret
252  %c = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 0)
253  ret <vscale x 2 x i8> %c
254}
255
256define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_2(<vscale x 32 x i8> %vec) {
257; CHECK-LABEL: extract_nxv32i8_nxv2i8_2:
258; CHECK:       # %bb.0:
259; CHECK-NEXT:    csrr a0, vlenb
260; CHECK-NEXT:    srli a0, a0, 2
261; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
262; CHECK-NEXT:    vslidedown.vx v8, v8, a0
263; CHECK-NEXT:    ret
264  %c = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 2)
265  ret <vscale x 2 x i8> %c
266}
267
268define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_4(<vscale x 32 x i8> %vec) {
269; CHECK-LABEL: extract_nxv32i8_nxv2i8_4:
270; CHECK:       # %bb.0:
271; CHECK-NEXT:    csrr a0, vlenb
272; CHECK-NEXT:    srli a0, a0, 1
273; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
274; CHECK-NEXT:    vslidedown.vx v8, v8, a0
275; CHECK-NEXT:    ret
276  %c = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 4)
277  ret <vscale x 2 x i8> %c
278}
279
280define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_6(<vscale x 32 x i8> %vec) {
281; CHECK-LABEL: extract_nxv32i8_nxv2i8_6:
282; CHECK:       # %bb.0:
283; CHECK-NEXT:    csrr a0, vlenb
284; CHECK-NEXT:    srli a0, a0, 3
285; CHECK-NEXT:    li a1, 6
286; CHECK-NEXT:    mul a0, a0, a1
287; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
288; CHECK-NEXT:    vslidedown.vx v8, v8, a0
289; CHECK-NEXT:    ret
290  %c = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 6)
291  ret <vscale x 2 x i8> %c
292}
293
294define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_8(<vscale x 32 x i8> %vec) {
295; CHECK-LABEL: extract_nxv32i8_nxv2i8_8:
296; CHECK:       # %bb.0:
297; CHECK-NEXT:    vmv1r.v v8, v9
298; CHECK-NEXT:    ret
299  %c = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 8)
300  ret <vscale x 2 x i8> %c
301}
302
303define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_22(<vscale x 32 x i8> %vec) {
304; CHECK-LABEL: extract_nxv32i8_nxv2i8_22:
305; CHECK:       # %bb.0:
306; CHECK-NEXT:    csrr a0, vlenb
307; CHECK-NEXT:    srli a0, a0, 3
308; CHECK-NEXT:    li a1, 6
309; CHECK-NEXT:    mul a0, a0, a1
310; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
311; CHECK-NEXT:    vslidedown.vx v8, v10, a0
312; CHECK-NEXT:    ret
313  %c = call <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 22)
314  ret <vscale x 2 x i8> %c
315}
316
317define <vscale x 1 x i8> @extract_nxv8i8_nxv1i8_7(<vscale x 8 x i8> %vec) {
318; CHECK-LABEL: extract_nxv8i8_nxv1i8_7:
319; CHECK:       # %bb.0:
320; CHECK-NEXT:    csrr a0, vlenb
321; CHECK-NEXT:    srli a0, a0, 3
322; CHECK-NEXT:    slli a1, a0, 3
323; CHECK-NEXT:    sub a0, a1, a0
324; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
325; CHECK-NEXT:    vslidedown.vx v8, v8, a0
326; CHECK-NEXT:    ret
327  %c = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv8i8(<vscale x 8 x i8> %vec, i64 7)
328  ret <vscale x 1 x i8> %c
329}
330
331define <vscale x 1 x i8> @extract_nxv4i8_nxv1i8_3(<vscale x 4 x i8> %vec) {
332; CHECK-LABEL: extract_nxv4i8_nxv1i8_3:
333; CHECK:       # %bb.0:
334; CHECK-NEXT:    csrr a0, vlenb
335; CHECK-NEXT:    srli a0, a0, 3
336; CHECK-NEXT:    slli a1, a0, 1
337; CHECK-NEXT:    add a0, a1, a0
338; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
339; CHECK-NEXT:    vslidedown.vx v8, v8, a0
340; CHECK-NEXT:    ret
341  %c = call <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, i64 3)
342  ret <vscale x 1 x i8> %c
343}
344
345define <vscale x 2 x half> @extract_nxv2f16_nxv16f16_0(<vscale x 16 x half> %vec) {
346; CHECK-LABEL: extract_nxv2f16_nxv16f16_0:
347; CHECK:       # %bb.0:
348; CHECK-NEXT:    # kill: def $v8 killed $v8 killed $v8m4
349; CHECK-NEXT:    ret
350  %c = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %vec, i64 0)
351  ret <vscale x 2 x half> %c
352}
353
354define <vscale x 2 x half> @extract_nxv2f16_nxv16f16_2(<vscale x 16 x half> %vec) {
355; CHECK-LABEL: extract_nxv2f16_nxv16f16_2:
356; CHECK:       # %bb.0:
357; CHECK-NEXT:    csrr a0, vlenb
358; CHECK-NEXT:    srli a0, a0, 2
359; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
360; CHECK-NEXT:    vslidedown.vx v8, v8, a0
361; CHECK-NEXT:    ret
362  %c = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %vec, i64 2)
363  ret <vscale x 2 x half> %c
364}
365
366define <vscale x 2 x half> @extract_nxv2f16_nxv16f16_4(<vscale x 16 x half> %vec) {
367; CHECK-LABEL: extract_nxv2f16_nxv16f16_4:
368; CHECK:       # %bb.0:
369; CHECK-NEXT:    vmv1r.v v8, v9
370; CHECK-NEXT:    ret
371  %c = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %vec, i64 4)
372  ret <vscale x 2 x half> %c
373}
374
375define <vscale x 8 x i1> @extract_nxv64i1_nxv8i1_0(<vscale x 64 x i1> %mask) {
376; CHECK-LABEL: extract_nxv64i1_nxv8i1_0:
377; CHECK:       # %bb.0:
378; CHECK-NEXT:    ret
379  %c = call <vscale x 8 x i1> @llvm.experimental.vector.extract.nxv8i1(<vscale x 64 x i1> %mask, i64 0)
380  ret <vscale x 8 x i1> %c
381}
382
383define <vscale x 8 x i1> @extract_nxv64i1_nxv8i1_8(<vscale x 64 x i1> %mask) {
384; CHECK-LABEL: extract_nxv64i1_nxv8i1_8:
385; CHECK:       # %bb.0:
386; CHECK-NEXT:    csrr a0, vlenb
387; CHECK-NEXT:    srli a0, a0, 3
388; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
389; CHECK-NEXT:    vslidedown.vx v0, v0, a0
390; CHECK-NEXT:    ret
391  %c = call <vscale x 8 x i1> @llvm.experimental.vector.extract.nxv8i1(<vscale x 64 x i1> %mask, i64 8)
392  ret <vscale x 8 x i1> %c
393}
394
395define <vscale x 2 x i1> @extract_nxv64i1_nxv2i1_0(<vscale x 64 x i1> %mask) {
396; CHECK-LABEL: extract_nxv64i1_nxv2i1_0:
397; CHECK:       # %bb.0:
398; CHECK-NEXT:    ret
399  %c = call <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1(<vscale x 64 x i1> %mask, i64 0)
400  ret <vscale x 2 x i1> %c
401}
402
403define <vscale x 2 x i1> @extract_nxv64i1_nxv2i1_2(<vscale x 64 x i1> %mask) {
404; CHECK-LABEL: extract_nxv64i1_nxv2i1_2:
405; CHECK:       # %bb.0:
406; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
407; CHECK-NEXT:    vmv.v.i v8, 0
408; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
409; CHECK-NEXT:    csrr a0, vlenb
410; CHECK-NEXT:    srli a0, a0, 2
411; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
412; CHECK-NEXT:    vslidedown.vx v8, v8, a0
413; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
414; CHECK-NEXT:    vmsne.vi v0, v8, 0
415; CHECK-NEXT:    ret
416  %c = call <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1(<vscale x 64 x i1> %mask, i64 2)
417  ret <vscale x 2 x i1> %c
418}
419
420define <vscale x 4 x i1> @extract_nxv4i1_nxv32i1_0(<vscale x 32 x i1> %x) {
421; CHECK-LABEL: extract_nxv4i1_nxv32i1_0:
422; CHECK:       # %bb.0:
423; CHECK-NEXT:    ret
424  %c = call <vscale x 4 x i1> @llvm.experimental.vector.extract.nxv4i1(<vscale x 32 x i1> %x, i64 0)
425  ret <vscale x 4 x i1> %c
426}
427
428define <vscale x 4 x i1> @extract_nxv4i1_nxv32i1_4(<vscale x 32 x i1> %x) {
429; CHECK-LABEL: extract_nxv4i1_nxv32i1_4:
430; CHECK:       # %bb.0:
431; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
432; CHECK-NEXT:    vmv.v.i v8, 0
433; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
434; CHECK-NEXT:    csrr a0, vlenb
435; CHECK-NEXT:    srli a0, a0, 1
436; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
437; CHECK-NEXT:    vslidedown.vx v8, v8, a0
438; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
439; CHECK-NEXT:    vmsne.vi v0, v8, 0
440; CHECK-NEXT:    ret
441  %c = call <vscale x 4 x i1> @llvm.experimental.vector.extract.nxv4i1(<vscale x 32 x i1> %x, i64 4)
442  ret <vscale x 4 x i1> %c
443}
444
445define <vscale x 16 x i1> @extract_nxv16i1_nxv32i1_0(<vscale x 32 x i1> %x) {
446; CHECK-LABEL: extract_nxv16i1_nxv32i1_0:
447; CHECK:       # %bb.0:
448; CHECK-NEXT:    ret
449  %c = call <vscale x 16 x i1> @llvm.experimental.vector.extract.nxv16i1(<vscale x 32 x i1> %x, i64 0)
450  ret <vscale x 16 x i1> %c
451}
452
453define <vscale x 16 x i1> @extract_nxv16i1_nxv32i1_16(<vscale x 32 x i1> %x) {
454; CHECK-LABEL: extract_nxv16i1_nxv32i1_16:
455; CHECK:       # %bb.0:
456; CHECK-NEXT:    csrr a0, vlenb
457; CHECK-NEXT:    srli a0, a0, 2
458; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
459; CHECK-NEXT:    vslidedown.vx v0, v0, a0
460; CHECK-NEXT:    ret
461  %c = call <vscale x 16 x i1> @llvm.experimental.vector.extract.nxv16i1(<vscale x 32 x i1> %x, i64 16)
462  ret <vscale x 16 x i1> %c
463}
464
465;
466; Extract f16 vector that needs widening from one that needs widening.
467;
468define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_0(<vscale x 12 x half> %in) {
469; CHECK-LABEL: extract_nxv6f16_nxv12f16_0:
470; CHECK:       # %bb.0:
471; CHECK-NEXT:    # kill: def $v8m2 killed $v8m2 killed $v8m4
472; CHECK-NEXT:    ret
473  %res = call <vscale x 6 x half> @llvm.experimental.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 0)
474  ret <vscale x 6 x half> %res
475}
476
477define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_6(<vscale x 12 x half> %in) {
478; CHECK-LABEL: extract_nxv6f16_nxv12f16_6:
479; CHECK:       # %bb.0:
480; CHECK-NEXT:    csrr a0, vlenb
481; CHECK-NEXT:    srli a0, a0, 2
482; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
483; CHECK-NEXT:    vslidedown.vx v14, v10, a0
484; CHECK-NEXT:    vslidedown.vx v12, v9, a0
485; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, mu
486; CHECK-NEXT:    vslideup.vi v13, v14, 0
487; CHECK-NEXT:    add a1, a0, a0
488; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, mu
489; CHECK-NEXT:    vslideup.vx v12, v10, a0
490; CHECK-NEXT:    vmv2r.v v8, v12
491; CHECK-NEXT:    ret
492  %res = call <vscale x 6 x half> @llvm.experimental.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 6)
493  ret <vscale x 6 x half> %res
494}
495
496declare <vscale x 6 x half> @llvm.experimental.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half>, i64)
497
498declare <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, i64 %idx)
499declare <vscale x 1 x i8> @llvm.experimental.vector.extract.nxv1i8.nxv8i8(<vscale x 8 x i8> %vec, i64 %idx)
500
501declare <vscale x 2 x i8> @llvm.experimental.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 %idx)
502
503declare <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> %vec, i64 %idx)
504
505declare <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 %idx)
506declare <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 %idx)
507
508declare <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx)
509declare <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx)
510declare <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx)
511declare <vscale x 8 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx)
512
513declare <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %vec, i64 %idx)
514
515declare <vscale x 4 x i1> @llvm.experimental.vector.extract.nxv4i1(<vscale x 32 x i1> %vec, i64 %idx)
516declare <vscale x 16 x i1> @llvm.experimental.vector.extract.nxv16i1(<vscale x 32 x i1> %vec, i64 %idx)
517
518declare <vscale x 2 x i1> @llvm.experimental.vector.extract.nxv2i1(<vscale x 64 x i1> %vec, i64 %idx)
519declare <vscale x 8 x i1> @llvm.experimental.vector.extract.nxv8i1(<vscale x 64 x i1> %vec, i64 %idx)
520