1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+experimental-zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32I
3; RUN: llc -mtriple=riscv64 -mattr=+experimental-zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64I
4; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32D
5; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64D
6
7define <vscale x 1 x i8> @cttz_nxv1i8(<vscale x 1 x i8> %va) {
8; RV32I-LABEL: cttz_nxv1i8:
9; RV32I:       # %bb.0:
10; RV32I-NEXT:    li a0, 1
11; RV32I-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
12; RV32I-NEXT:    vsub.vx v9, v8, a0
13; RV32I-NEXT:    vxor.vi v8, v8, -1
14; RV32I-NEXT:    vand.vv v8, v8, v9
15; RV32I-NEXT:    vsrl.vi v9, v8, 1
16; RV32I-NEXT:    li a0, 85
17; RV32I-NEXT:    vand.vx v9, v9, a0
18; RV32I-NEXT:    vsub.vv v8, v8, v9
19; RV32I-NEXT:    li a0, 51
20; RV32I-NEXT:    vand.vx v9, v8, a0
21; RV32I-NEXT:    vsrl.vi v8, v8, 2
22; RV32I-NEXT:    vand.vx v8, v8, a0
23; RV32I-NEXT:    vadd.vv v8, v9, v8
24; RV32I-NEXT:    vsrl.vi v9, v8, 4
25; RV32I-NEXT:    vadd.vv v8, v8, v9
26; RV32I-NEXT:    vand.vi v8, v8, 15
27; RV32I-NEXT:    ret
28;
29; RV64I-LABEL: cttz_nxv1i8:
30; RV64I:       # %bb.0:
31; RV64I-NEXT:    li a0, 1
32; RV64I-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
33; RV64I-NEXT:    vsub.vx v9, v8, a0
34; RV64I-NEXT:    vxor.vi v8, v8, -1
35; RV64I-NEXT:    vand.vv v8, v8, v9
36; RV64I-NEXT:    vsrl.vi v9, v8, 1
37; RV64I-NEXT:    li a0, 85
38; RV64I-NEXT:    vand.vx v9, v9, a0
39; RV64I-NEXT:    vsub.vv v8, v8, v9
40; RV64I-NEXT:    li a0, 51
41; RV64I-NEXT:    vand.vx v9, v8, a0
42; RV64I-NEXT:    vsrl.vi v8, v8, 2
43; RV64I-NEXT:    vand.vx v8, v8, a0
44; RV64I-NEXT:    vadd.vv v8, v9, v8
45; RV64I-NEXT:    vsrl.vi v9, v8, 4
46; RV64I-NEXT:    vadd.vv v8, v8, v9
47; RV64I-NEXT:    vand.vi v8, v8, 15
48; RV64I-NEXT:    ret
49;
50; RV32D-LABEL: cttz_nxv1i8:
51; RV32D:       # %bb.0:
52; RV32D-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
53; RV32D-NEXT:    vmv.v.i v9, 0
54; RV32D-NEXT:    vmseq.vv v0, v9, v8
55; RV32D-NEXT:    vrsub.vi v9, v8, 0
56; RV32D-NEXT:    vand.vv v8, v8, v9
57; RV32D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
58; RV32D-NEXT:    vzext.vf4 v9, v8
59; RV32D-NEXT:    vfcvt.f.xu.v v8, v9
60; RV32D-NEXT:    vsrl.vi v8, v8, 23
61; RV32D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
62; RV32D-NEXT:    vnsrl.wi v8, v8, 0
63; RV32D-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
64; RV32D-NEXT:    vnsrl.wi v8, v8, 0
65; RV32D-NEXT:    li a0, 127
66; RV32D-NEXT:    vsub.vx v8, v8, a0
67; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
68; RV32D-NEXT:    ret
69;
70; RV64D-LABEL: cttz_nxv1i8:
71; RV64D:       # %bb.0:
72; RV64D-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
73; RV64D-NEXT:    vmv.v.i v9, 0
74; RV64D-NEXT:    vmseq.vv v0, v9, v8
75; RV64D-NEXT:    vrsub.vi v9, v8, 0
76; RV64D-NEXT:    vand.vv v8, v8, v9
77; RV64D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
78; RV64D-NEXT:    vzext.vf4 v9, v8
79; RV64D-NEXT:    vfcvt.f.xu.v v8, v9
80; RV64D-NEXT:    vsrl.vi v8, v8, 23
81; RV64D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
82; RV64D-NEXT:    vnsrl.wi v8, v8, 0
83; RV64D-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
84; RV64D-NEXT:    vnsrl.wi v8, v8, 0
85; RV64D-NEXT:    li a0, 127
86; RV64D-NEXT:    vsub.vx v8, v8, a0
87; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
88; RV64D-NEXT:    ret
89  %a = call <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 false)
90  ret <vscale x 1 x i8> %a
91}
92declare <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8>, i1)
93
94define <vscale x 2 x i8> @cttz_nxv2i8(<vscale x 2 x i8> %va) {
95; RV32I-LABEL: cttz_nxv2i8:
96; RV32I:       # %bb.0:
97; RV32I-NEXT:    li a0, 1
98; RV32I-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
99; RV32I-NEXT:    vsub.vx v9, v8, a0
100; RV32I-NEXT:    vxor.vi v8, v8, -1
101; RV32I-NEXT:    vand.vv v8, v8, v9
102; RV32I-NEXT:    vsrl.vi v9, v8, 1
103; RV32I-NEXT:    li a0, 85
104; RV32I-NEXT:    vand.vx v9, v9, a0
105; RV32I-NEXT:    vsub.vv v8, v8, v9
106; RV32I-NEXT:    li a0, 51
107; RV32I-NEXT:    vand.vx v9, v8, a0
108; RV32I-NEXT:    vsrl.vi v8, v8, 2
109; RV32I-NEXT:    vand.vx v8, v8, a0
110; RV32I-NEXT:    vadd.vv v8, v9, v8
111; RV32I-NEXT:    vsrl.vi v9, v8, 4
112; RV32I-NEXT:    vadd.vv v8, v8, v9
113; RV32I-NEXT:    vand.vi v8, v8, 15
114; RV32I-NEXT:    ret
115;
116; RV64I-LABEL: cttz_nxv2i8:
117; RV64I:       # %bb.0:
118; RV64I-NEXT:    li a0, 1
119; RV64I-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
120; RV64I-NEXT:    vsub.vx v9, v8, a0
121; RV64I-NEXT:    vxor.vi v8, v8, -1
122; RV64I-NEXT:    vand.vv v8, v8, v9
123; RV64I-NEXT:    vsrl.vi v9, v8, 1
124; RV64I-NEXT:    li a0, 85
125; RV64I-NEXT:    vand.vx v9, v9, a0
126; RV64I-NEXT:    vsub.vv v8, v8, v9
127; RV64I-NEXT:    li a0, 51
128; RV64I-NEXT:    vand.vx v9, v8, a0
129; RV64I-NEXT:    vsrl.vi v8, v8, 2
130; RV64I-NEXT:    vand.vx v8, v8, a0
131; RV64I-NEXT:    vadd.vv v8, v9, v8
132; RV64I-NEXT:    vsrl.vi v9, v8, 4
133; RV64I-NEXT:    vadd.vv v8, v8, v9
134; RV64I-NEXT:    vand.vi v8, v8, 15
135; RV64I-NEXT:    ret
136;
137; RV32D-LABEL: cttz_nxv2i8:
138; RV32D:       # %bb.0:
139; RV32D-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
140; RV32D-NEXT:    vmv.v.i v9, 0
141; RV32D-NEXT:    vmseq.vv v0, v9, v8
142; RV32D-NEXT:    vrsub.vi v9, v8, 0
143; RV32D-NEXT:    vand.vv v8, v8, v9
144; RV32D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
145; RV32D-NEXT:    vzext.vf4 v9, v8
146; RV32D-NEXT:    vfcvt.f.xu.v v8, v9
147; RV32D-NEXT:    vsrl.vi v8, v8, 23
148; RV32D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
149; RV32D-NEXT:    vnsrl.wi v8, v8, 0
150; RV32D-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
151; RV32D-NEXT:    vnsrl.wi v8, v8, 0
152; RV32D-NEXT:    li a0, 127
153; RV32D-NEXT:    vsub.vx v8, v8, a0
154; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
155; RV32D-NEXT:    ret
156;
157; RV64D-LABEL: cttz_nxv2i8:
158; RV64D:       # %bb.0:
159; RV64D-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
160; RV64D-NEXT:    vmv.v.i v9, 0
161; RV64D-NEXT:    vmseq.vv v0, v9, v8
162; RV64D-NEXT:    vrsub.vi v9, v8, 0
163; RV64D-NEXT:    vand.vv v8, v8, v9
164; RV64D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
165; RV64D-NEXT:    vzext.vf4 v9, v8
166; RV64D-NEXT:    vfcvt.f.xu.v v8, v9
167; RV64D-NEXT:    vsrl.vi v8, v8, 23
168; RV64D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
169; RV64D-NEXT:    vnsrl.wi v8, v8, 0
170; RV64D-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
171; RV64D-NEXT:    vnsrl.wi v8, v8, 0
172; RV64D-NEXT:    li a0, 127
173; RV64D-NEXT:    vsub.vx v8, v8, a0
174; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
175; RV64D-NEXT:    ret
176  %a = call <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 false)
177  ret <vscale x 2 x i8> %a
178}
179declare <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8>, i1)
180
181define <vscale x 4 x i8> @cttz_nxv4i8(<vscale x 4 x i8> %va) {
182; RV32I-LABEL: cttz_nxv4i8:
183; RV32I:       # %bb.0:
184; RV32I-NEXT:    li a0, 1
185; RV32I-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
186; RV32I-NEXT:    vsub.vx v9, v8, a0
187; RV32I-NEXT:    vxor.vi v8, v8, -1
188; RV32I-NEXT:    vand.vv v8, v8, v9
189; RV32I-NEXT:    vsrl.vi v9, v8, 1
190; RV32I-NEXT:    li a0, 85
191; RV32I-NEXT:    vand.vx v9, v9, a0
192; RV32I-NEXT:    vsub.vv v8, v8, v9
193; RV32I-NEXT:    li a0, 51
194; RV32I-NEXT:    vand.vx v9, v8, a0
195; RV32I-NEXT:    vsrl.vi v8, v8, 2
196; RV32I-NEXT:    vand.vx v8, v8, a0
197; RV32I-NEXT:    vadd.vv v8, v9, v8
198; RV32I-NEXT:    vsrl.vi v9, v8, 4
199; RV32I-NEXT:    vadd.vv v8, v8, v9
200; RV32I-NEXT:    vand.vi v8, v8, 15
201; RV32I-NEXT:    ret
202;
203; RV64I-LABEL: cttz_nxv4i8:
204; RV64I:       # %bb.0:
205; RV64I-NEXT:    li a0, 1
206; RV64I-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
207; RV64I-NEXT:    vsub.vx v9, v8, a0
208; RV64I-NEXT:    vxor.vi v8, v8, -1
209; RV64I-NEXT:    vand.vv v8, v8, v9
210; RV64I-NEXT:    vsrl.vi v9, v8, 1
211; RV64I-NEXT:    li a0, 85
212; RV64I-NEXT:    vand.vx v9, v9, a0
213; RV64I-NEXT:    vsub.vv v8, v8, v9
214; RV64I-NEXT:    li a0, 51
215; RV64I-NEXT:    vand.vx v9, v8, a0
216; RV64I-NEXT:    vsrl.vi v8, v8, 2
217; RV64I-NEXT:    vand.vx v8, v8, a0
218; RV64I-NEXT:    vadd.vv v8, v9, v8
219; RV64I-NEXT:    vsrl.vi v9, v8, 4
220; RV64I-NEXT:    vadd.vv v8, v8, v9
221; RV64I-NEXT:    vand.vi v8, v8, 15
222; RV64I-NEXT:    ret
223;
224; RV32D-LABEL: cttz_nxv4i8:
225; RV32D:       # %bb.0:
226; RV32D-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
227; RV32D-NEXT:    vmv.v.i v9, 0
228; RV32D-NEXT:    vmseq.vv v0, v9, v8
229; RV32D-NEXT:    vrsub.vi v9, v8, 0
230; RV32D-NEXT:    vand.vv v8, v8, v9
231; RV32D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
232; RV32D-NEXT:    vzext.vf4 v10, v8
233; RV32D-NEXT:    vfcvt.f.xu.v v8, v10
234; RV32D-NEXT:    vsrl.vi v8, v8, 23
235; RV32D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
236; RV32D-NEXT:    vnsrl.wi v10, v8, 0
237; RV32D-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
238; RV32D-NEXT:    vnsrl.wi v8, v10, 0
239; RV32D-NEXT:    li a0, 127
240; RV32D-NEXT:    vsub.vx v8, v8, a0
241; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
242; RV32D-NEXT:    ret
243;
244; RV64D-LABEL: cttz_nxv4i8:
245; RV64D:       # %bb.0:
246; RV64D-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
247; RV64D-NEXT:    vmv.v.i v9, 0
248; RV64D-NEXT:    vmseq.vv v0, v9, v8
249; RV64D-NEXT:    vrsub.vi v9, v8, 0
250; RV64D-NEXT:    vand.vv v8, v8, v9
251; RV64D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
252; RV64D-NEXT:    vzext.vf4 v10, v8
253; RV64D-NEXT:    vfcvt.f.xu.v v8, v10
254; RV64D-NEXT:    vsrl.vi v8, v8, 23
255; RV64D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
256; RV64D-NEXT:    vnsrl.wi v10, v8, 0
257; RV64D-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
258; RV64D-NEXT:    vnsrl.wi v8, v10, 0
259; RV64D-NEXT:    li a0, 127
260; RV64D-NEXT:    vsub.vx v8, v8, a0
261; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
262; RV64D-NEXT:    ret
263  %a = call <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 false)
264  ret <vscale x 4 x i8> %a
265}
266declare <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8>, i1)
267
268define <vscale x 8 x i8> @cttz_nxv8i8(<vscale x 8 x i8> %va) {
269; RV32I-LABEL: cttz_nxv8i8:
270; RV32I:       # %bb.0:
271; RV32I-NEXT:    li a0, 1
272; RV32I-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
273; RV32I-NEXT:    vsub.vx v9, v8, a0
274; RV32I-NEXT:    vxor.vi v8, v8, -1
275; RV32I-NEXT:    vand.vv v8, v8, v9
276; RV32I-NEXT:    vsrl.vi v9, v8, 1
277; RV32I-NEXT:    li a0, 85
278; RV32I-NEXT:    vand.vx v9, v9, a0
279; RV32I-NEXT:    vsub.vv v8, v8, v9
280; RV32I-NEXT:    li a0, 51
281; RV32I-NEXT:    vand.vx v9, v8, a0
282; RV32I-NEXT:    vsrl.vi v8, v8, 2
283; RV32I-NEXT:    vand.vx v8, v8, a0
284; RV32I-NEXT:    vadd.vv v8, v9, v8
285; RV32I-NEXT:    vsrl.vi v9, v8, 4
286; RV32I-NEXT:    vadd.vv v8, v8, v9
287; RV32I-NEXT:    vand.vi v8, v8, 15
288; RV32I-NEXT:    ret
289;
290; RV64I-LABEL: cttz_nxv8i8:
291; RV64I:       # %bb.0:
292; RV64I-NEXT:    li a0, 1
293; RV64I-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
294; RV64I-NEXT:    vsub.vx v9, v8, a0
295; RV64I-NEXT:    vxor.vi v8, v8, -1
296; RV64I-NEXT:    vand.vv v8, v8, v9
297; RV64I-NEXT:    vsrl.vi v9, v8, 1
298; RV64I-NEXT:    li a0, 85
299; RV64I-NEXT:    vand.vx v9, v9, a0
300; RV64I-NEXT:    vsub.vv v8, v8, v9
301; RV64I-NEXT:    li a0, 51
302; RV64I-NEXT:    vand.vx v9, v8, a0
303; RV64I-NEXT:    vsrl.vi v8, v8, 2
304; RV64I-NEXT:    vand.vx v8, v8, a0
305; RV64I-NEXT:    vadd.vv v8, v9, v8
306; RV64I-NEXT:    vsrl.vi v9, v8, 4
307; RV64I-NEXT:    vadd.vv v8, v8, v9
308; RV64I-NEXT:    vand.vi v8, v8, 15
309; RV64I-NEXT:    ret
310;
311; RV32D-LABEL: cttz_nxv8i8:
312; RV32D:       # %bb.0:
313; RV32D-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
314; RV32D-NEXT:    vmv.v.i v9, 0
315; RV32D-NEXT:    vmseq.vv v0, v9, v8
316; RV32D-NEXT:    vrsub.vi v9, v8, 0
317; RV32D-NEXT:    vand.vv v8, v8, v9
318; RV32D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
319; RV32D-NEXT:    vzext.vf4 v12, v8
320; RV32D-NEXT:    vfcvt.f.xu.v v8, v12
321; RV32D-NEXT:    vsrl.vi v8, v8, 23
322; RV32D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
323; RV32D-NEXT:    vnsrl.wi v12, v8, 0
324; RV32D-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
325; RV32D-NEXT:    vnsrl.wi v8, v12, 0
326; RV32D-NEXT:    li a0, 127
327; RV32D-NEXT:    vsub.vx v8, v8, a0
328; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
329; RV32D-NEXT:    ret
330;
331; RV64D-LABEL: cttz_nxv8i8:
332; RV64D:       # %bb.0:
333; RV64D-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
334; RV64D-NEXT:    vmv.v.i v9, 0
335; RV64D-NEXT:    vmseq.vv v0, v9, v8
336; RV64D-NEXT:    vrsub.vi v9, v8, 0
337; RV64D-NEXT:    vand.vv v8, v8, v9
338; RV64D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
339; RV64D-NEXT:    vzext.vf4 v12, v8
340; RV64D-NEXT:    vfcvt.f.xu.v v8, v12
341; RV64D-NEXT:    vsrl.vi v8, v8, 23
342; RV64D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
343; RV64D-NEXT:    vnsrl.wi v12, v8, 0
344; RV64D-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
345; RV64D-NEXT:    vnsrl.wi v8, v12, 0
346; RV64D-NEXT:    li a0, 127
347; RV64D-NEXT:    vsub.vx v8, v8, a0
348; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
349; RV64D-NEXT:    ret
350  %a = call <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 false)
351  ret <vscale x 8 x i8> %a
352}
353declare <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8>, i1)
354
355define <vscale x 16 x i8> @cttz_nxv16i8(<vscale x 16 x i8> %va) {
356; RV32I-LABEL: cttz_nxv16i8:
357; RV32I:       # %bb.0:
358; RV32I-NEXT:    li a0, 1
359; RV32I-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
360; RV32I-NEXT:    vsub.vx v10, v8, a0
361; RV32I-NEXT:    vxor.vi v8, v8, -1
362; RV32I-NEXT:    vand.vv v8, v8, v10
363; RV32I-NEXT:    vsrl.vi v10, v8, 1
364; RV32I-NEXT:    li a0, 85
365; RV32I-NEXT:    vand.vx v10, v10, a0
366; RV32I-NEXT:    vsub.vv v8, v8, v10
367; RV32I-NEXT:    li a0, 51
368; RV32I-NEXT:    vand.vx v10, v8, a0
369; RV32I-NEXT:    vsrl.vi v8, v8, 2
370; RV32I-NEXT:    vand.vx v8, v8, a0
371; RV32I-NEXT:    vadd.vv v8, v10, v8
372; RV32I-NEXT:    vsrl.vi v10, v8, 4
373; RV32I-NEXT:    vadd.vv v8, v8, v10
374; RV32I-NEXT:    vand.vi v8, v8, 15
375; RV32I-NEXT:    ret
376;
377; RV64I-LABEL: cttz_nxv16i8:
378; RV64I:       # %bb.0:
379; RV64I-NEXT:    li a0, 1
380; RV64I-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
381; RV64I-NEXT:    vsub.vx v10, v8, a0
382; RV64I-NEXT:    vxor.vi v8, v8, -1
383; RV64I-NEXT:    vand.vv v8, v8, v10
384; RV64I-NEXT:    vsrl.vi v10, v8, 1
385; RV64I-NEXT:    li a0, 85
386; RV64I-NEXT:    vand.vx v10, v10, a0
387; RV64I-NEXT:    vsub.vv v8, v8, v10
388; RV64I-NEXT:    li a0, 51
389; RV64I-NEXT:    vand.vx v10, v8, a0
390; RV64I-NEXT:    vsrl.vi v8, v8, 2
391; RV64I-NEXT:    vand.vx v8, v8, a0
392; RV64I-NEXT:    vadd.vv v8, v10, v8
393; RV64I-NEXT:    vsrl.vi v10, v8, 4
394; RV64I-NEXT:    vadd.vv v8, v8, v10
395; RV64I-NEXT:    vand.vi v8, v8, 15
396; RV64I-NEXT:    ret
397;
398; RV32D-LABEL: cttz_nxv16i8:
399; RV32D:       # %bb.0:
400; RV32D-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
401; RV32D-NEXT:    vmv.v.i v10, 0
402; RV32D-NEXT:    vmseq.vv v0, v10, v8
403; RV32D-NEXT:    vrsub.vi v10, v8, 0
404; RV32D-NEXT:    vand.vv v8, v8, v10
405; RV32D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
406; RV32D-NEXT:    vzext.vf4 v16, v8
407; RV32D-NEXT:    vfcvt.f.xu.v v8, v16
408; RV32D-NEXT:    vsrl.vi v8, v8, 23
409; RV32D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
410; RV32D-NEXT:    vnsrl.wi v16, v8, 0
411; RV32D-NEXT:    vsetvli zero, zero, e8, m2, ta, mu
412; RV32D-NEXT:    vnsrl.wi v8, v16, 0
413; RV32D-NEXT:    li a0, 127
414; RV32D-NEXT:    vsub.vx v8, v8, a0
415; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
416; RV32D-NEXT:    ret
417;
418; RV64D-LABEL: cttz_nxv16i8:
419; RV64D:       # %bb.0:
420; RV64D-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
421; RV64D-NEXT:    vmv.v.i v10, 0
422; RV64D-NEXT:    vmseq.vv v0, v10, v8
423; RV64D-NEXT:    vrsub.vi v10, v8, 0
424; RV64D-NEXT:    vand.vv v8, v8, v10
425; RV64D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
426; RV64D-NEXT:    vzext.vf4 v16, v8
427; RV64D-NEXT:    vfcvt.f.xu.v v8, v16
428; RV64D-NEXT:    vsrl.vi v8, v8, 23
429; RV64D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
430; RV64D-NEXT:    vnsrl.wi v16, v8, 0
431; RV64D-NEXT:    vsetvli zero, zero, e8, m2, ta, mu
432; RV64D-NEXT:    vnsrl.wi v8, v16, 0
433; RV64D-NEXT:    li a0, 127
434; RV64D-NEXT:    vsub.vx v8, v8, a0
435; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
436; RV64D-NEXT:    ret
437  %a = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 false)
438  ret <vscale x 16 x i8> %a
439}
440declare <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8>, i1)
441
442define <vscale x 32 x i8> @cttz_nxv32i8(<vscale x 32 x i8> %va) {
443; CHECK-LABEL: cttz_nxv32i8:
444; CHECK:       # %bb.0:
445; CHECK-NEXT:    li a0, 1
446; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
447; CHECK-NEXT:    vsub.vx v12, v8, a0
448; CHECK-NEXT:    vxor.vi v8, v8, -1
449; CHECK-NEXT:    vand.vv v8, v8, v12
450; CHECK-NEXT:    vsrl.vi v12, v8, 1
451; CHECK-NEXT:    li a0, 85
452; CHECK-NEXT:    vand.vx v12, v12, a0
453; CHECK-NEXT:    vsub.vv v8, v8, v12
454; CHECK-NEXT:    li a0, 51
455; CHECK-NEXT:    vand.vx v12, v8, a0
456; CHECK-NEXT:    vsrl.vi v8, v8, 2
457; CHECK-NEXT:    vand.vx v8, v8, a0
458; CHECK-NEXT:    vadd.vv v8, v12, v8
459; CHECK-NEXT:    vsrl.vi v12, v8, 4
460; CHECK-NEXT:    vadd.vv v8, v8, v12
461; CHECK-NEXT:    vand.vi v8, v8, 15
462; CHECK-NEXT:    ret
463  %a = call <vscale x 32 x i8> @llvm.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 false)
464  ret <vscale x 32 x i8> %a
465}
466declare <vscale x 32 x i8> @llvm.cttz.nxv32i8(<vscale x 32 x i8>, i1)
467
468define <vscale x 64 x i8> @cttz_nxv64i8(<vscale x 64 x i8> %va) {
469; CHECK-LABEL: cttz_nxv64i8:
470; CHECK:       # %bb.0:
471; CHECK-NEXT:    li a0, 1
472; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
473; CHECK-NEXT:    vsub.vx v16, v8, a0
474; CHECK-NEXT:    vxor.vi v8, v8, -1
475; CHECK-NEXT:    vand.vv v8, v8, v16
476; CHECK-NEXT:    vsrl.vi v16, v8, 1
477; CHECK-NEXT:    li a0, 85
478; CHECK-NEXT:    vand.vx v16, v16, a0
479; CHECK-NEXT:    vsub.vv v8, v8, v16
480; CHECK-NEXT:    li a0, 51
481; CHECK-NEXT:    vand.vx v16, v8, a0
482; CHECK-NEXT:    vsrl.vi v8, v8, 2
483; CHECK-NEXT:    vand.vx v8, v8, a0
484; CHECK-NEXT:    vadd.vv v8, v16, v8
485; CHECK-NEXT:    vsrl.vi v16, v8, 4
486; CHECK-NEXT:    vadd.vv v8, v8, v16
487; CHECK-NEXT:    vand.vi v8, v8, 15
488; CHECK-NEXT:    ret
489  %a = call <vscale x 64 x i8> @llvm.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 false)
490  ret <vscale x 64 x i8> %a
491}
492declare <vscale x 64 x i8> @llvm.cttz.nxv64i8(<vscale x 64 x i8>, i1)
493
494define <vscale x 1 x i16> @cttz_nxv1i16(<vscale x 1 x i16> %va) {
495; RV32I-LABEL: cttz_nxv1i16:
496; RV32I:       # %bb.0:
497; RV32I-NEXT:    li a0, 1
498; RV32I-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
499; RV32I-NEXT:    vsub.vx v9, v8, a0
500; RV32I-NEXT:    vxor.vi v8, v8, -1
501; RV32I-NEXT:    vand.vv v8, v8, v9
502; RV32I-NEXT:    vsrl.vi v9, v8, 1
503; RV32I-NEXT:    lui a0, 5
504; RV32I-NEXT:    addi a0, a0, 1365
505; RV32I-NEXT:    vand.vx v9, v9, a0
506; RV32I-NEXT:    vsub.vv v8, v8, v9
507; RV32I-NEXT:    lui a0, 3
508; RV32I-NEXT:    addi a0, a0, 819
509; RV32I-NEXT:    vand.vx v9, v8, a0
510; RV32I-NEXT:    vsrl.vi v8, v8, 2
511; RV32I-NEXT:    vand.vx v8, v8, a0
512; RV32I-NEXT:    vadd.vv v8, v9, v8
513; RV32I-NEXT:    vsrl.vi v9, v8, 4
514; RV32I-NEXT:    vadd.vv v8, v8, v9
515; RV32I-NEXT:    lui a0, 1
516; RV32I-NEXT:    addi a0, a0, -241
517; RV32I-NEXT:    vand.vx v8, v8, a0
518; RV32I-NEXT:    li a0, 257
519; RV32I-NEXT:    vmul.vx v8, v8, a0
520; RV32I-NEXT:    vsrl.vi v8, v8, 8
521; RV32I-NEXT:    ret
522;
523; RV64I-LABEL: cttz_nxv1i16:
524; RV64I:       # %bb.0:
525; RV64I-NEXT:    li a0, 1
526; RV64I-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
527; RV64I-NEXT:    vsub.vx v9, v8, a0
528; RV64I-NEXT:    vxor.vi v8, v8, -1
529; RV64I-NEXT:    vand.vv v8, v8, v9
530; RV64I-NEXT:    vsrl.vi v9, v8, 1
531; RV64I-NEXT:    lui a0, 5
532; RV64I-NEXT:    addiw a0, a0, 1365
533; RV64I-NEXT:    vand.vx v9, v9, a0
534; RV64I-NEXT:    vsub.vv v8, v8, v9
535; RV64I-NEXT:    lui a0, 3
536; RV64I-NEXT:    addiw a0, a0, 819
537; RV64I-NEXT:    vand.vx v9, v8, a0
538; RV64I-NEXT:    vsrl.vi v8, v8, 2
539; RV64I-NEXT:    vand.vx v8, v8, a0
540; RV64I-NEXT:    vadd.vv v8, v9, v8
541; RV64I-NEXT:    vsrl.vi v9, v8, 4
542; RV64I-NEXT:    vadd.vv v8, v8, v9
543; RV64I-NEXT:    lui a0, 1
544; RV64I-NEXT:    addiw a0, a0, -241
545; RV64I-NEXT:    vand.vx v8, v8, a0
546; RV64I-NEXT:    li a0, 257
547; RV64I-NEXT:    vmul.vx v8, v8, a0
548; RV64I-NEXT:    vsrl.vi v8, v8, 8
549; RV64I-NEXT:    ret
550;
551; RV32D-LABEL: cttz_nxv1i16:
552; RV32D:       # %bb.0:
553; RV32D-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
554; RV32D-NEXT:    vmv.v.i v9, 0
555; RV32D-NEXT:    vmseq.vv v0, v9, v8
556; RV32D-NEXT:    vrsub.vi v9, v8, 0
557; RV32D-NEXT:    vand.vv v8, v8, v9
558; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
559; RV32D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
560; RV32D-NEXT:    vsrl.vi v8, v9, 23
561; RV32D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
562; RV32D-NEXT:    vnsrl.wi v8, v8, 0
563; RV32D-NEXT:    li a0, 127
564; RV32D-NEXT:    vsub.vx v8, v8, a0
565; RV32D-NEXT:    li a0, 16
566; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
567; RV32D-NEXT:    ret
568;
569; RV64D-LABEL: cttz_nxv1i16:
570; RV64D:       # %bb.0:
571; RV64D-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
572; RV64D-NEXT:    vmv.v.i v9, 0
573; RV64D-NEXT:    vmseq.vv v0, v9, v8
574; RV64D-NEXT:    vrsub.vi v9, v8, 0
575; RV64D-NEXT:    vand.vv v8, v8, v9
576; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
577; RV64D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
578; RV64D-NEXT:    vsrl.vi v8, v9, 23
579; RV64D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
580; RV64D-NEXT:    vnsrl.wi v8, v8, 0
581; RV64D-NEXT:    li a0, 127
582; RV64D-NEXT:    vsub.vx v8, v8, a0
583; RV64D-NEXT:    li a0, 16
584; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
585; RV64D-NEXT:    ret
586  %a = call <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 false)
587  ret <vscale x 1 x i16> %a
588}
589declare <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16>, i1)
590
591define <vscale x 2 x i16> @cttz_nxv2i16(<vscale x 2 x i16> %va) {
592; RV32I-LABEL: cttz_nxv2i16:
593; RV32I:       # %bb.0:
594; RV32I-NEXT:    li a0, 1
595; RV32I-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
596; RV32I-NEXT:    vsub.vx v9, v8, a0
597; RV32I-NEXT:    vxor.vi v8, v8, -1
598; RV32I-NEXT:    vand.vv v8, v8, v9
599; RV32I-NEXT:    vsrl.vi v9, v8, 1
600; RV32I-NEXT:    lui a0, 5
601; RV32I-NEXT:    addi a0, a0, 1365
602; RV32I-NEXT:    vand.vx v9, v9, a0
603; RV32I-NEXT:    vsub.vv v8, v8, v9
604; RV32I-NEXT:    lui a0, 3
605; RV32I-NEXT:    addi a0, a0, 819
606; RV32I-NEXT:    vand.vx v9, v8, a0
607; RV32I-NEXT:    vsrl.vi v8, v8, 2
608; RV32I-NEXT:    vand.vx v8, v8, a0
609; RV32I-NEXT:    vadd.vv v8, v9, v8
610; RV32I-NEXT:    vsrl.vi v9, v8, 4
611; RV32I-NEXT:    vadd.vv v8, v8, v9
612; RV32I-NEXT:    lui a0, 1
613; RV32I-NEXT:    addi a0, a0, -241
614; RV32I-NEXT:    vand.vx v8, v8, a0
615; RV32I-NEXT:    li a0, 257
616; RV32I-NEXT:    vmul.vx v8, v8, a0
617; RV32I-NEXT:    vsrl.vi v8, v8, 8
618; RV32I-NEXT:    ret
619;
620; RV64I-LABEL: cttz_nxv2i16:
621; RV64I:       # %bb.0:
622; RV64I-NEXT:    li a0, 1
623; RV64I-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
624; RV64I-NEXT:    vsub.vx v9, v8, a0
625; RV64I-NEXT:    vxor.vi v8, v8, -1
626; RV64I-NEXT:    vand.vv v8, v8, v9
627; RV64I-NEXT:    vsrl.vi v9, v8, 1
628; RV64I-NEXT:    lui a0, 5
629; RV64I-NEXT:    addiw a0, a0, 1365
630; RV64I-NEXT:    vand.vx v9, v9, a0
631; RV64I-NEXT:    vsub.vv v8, v8, v9
632; RV64I-NEXT:    lui a0, 3
633; RV64I-NEXT:    addiw a0, a0, 819
634; RV64I-NEXT:    vand.vx v9, v8, a0
635; RV64I-NEXT:    vsrl.vi v8, v8, 2
636; RV64I-NEXT:    vand.vx v8, v8, a0
637; RV64I-NEXT:    vadd.vv v8, v9, v8
638; RV64I-NEXT:    vsrl.vi v9, v8, 4
639; RV64I-NEXT:    vadd.vv v8, v8, v9
640; RV64I-NEXT:    lui a0, 1
641; RV64I-NEXT:    addiw a0, a0, -241
642; RV64I-NEXT:    vand.vx v8, v8, a0
643; RV64I-NEXT:    li a0, 257
644; RV64I-NEXT:    vmul.vx v8, v8, a0
645; RV64I-NEXT:    vsrl.vi v8, v8, 8
646; RV64I-NEXT:    ret
647;
648; RV32D-LABEL: cttz_nxv2i16:
649; RV32D:       # %bb.0:
650; RV32D-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
651; RV32D-NEXT:    vmv.v.i v9, 0
652; RV32D-NEXT:    vmseq.vv v0, v9, v8
653; RV32D-NEXT:    vrsub.vi v9, v8, 0
654; RV32D-NEXT:    vand.vv v8, v8, v9
655; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
656; RV32D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
657; RV32D-NEXT:    vsrl.vi v8, v9, 23
658; RV32D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
659; RV32D-NEXT:    vnsrl.wi v8, v8, 0
660; RV32D-NEXT:    li a0, 127
661; RV32D-NEXT:    vsub.vx v8, v8, a0
662; RV32D-NEXT:    li a0, 16
663; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
664; RV32D-NEXT:    ret
665;
666; RV64D-LABEL: cttz_nxv2i16:
667; RV64D:       # %bb.0:
668; RV64D-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
669; RV64D-NEXT:    vmv.v.i v9, 0
670; RV64D-NEXT:    vmseq.vv v0, v9, v8
671; RV64D-NEXT:    vrsub.vi v9, v8, 0
672; RV64D-NEXT:    vand.vv v8, v8, v9
673; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
674; RV64D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
675; RV64D-NEXT:    vsrl.vi v8, v9, 23
676; RV64D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
677; RV64D-NEXT:    vnsrl.wi v8, v8, 0
678; RV64D-NEXT:    li a0, 127
679; RV64D-NEXT:    vsub.vx v8, v8, a0
680; RV64D-NEXT:    li a0, 16
681; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
682; RV64D-NEXT:    ret
683  %a = call <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 false)
684  ret <vscale x 2 x i16> %a
685}
686declare <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16>, i1)
687
688define <vscale x 4 x i16> @cttz_nxv4i16(<vscale x 4 x i16> %va) {
689; RV32I-LABEL: cttz_nxv4i16:
690; RV32I:       # %bb.0:
691; RV32I-NEXT:    li a0, 1
692; RV32I-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
693; RV32I-NEXT:    vsub.vx v9, v8, a0
694; RV32I-NEXT:    vxor.vi v8, v8, -1
695; RV32I-NEXT:    vand.vv v8, v8, v9
696; RV32I-NEXT:    vsrl.vi v9, v8, 1
697; RV32I-NEXT:    lui a0, 5
698; RV32I-NEXT:    addi a0, a0, 1365
699; RV32I-NEXT:    vand.vx v9, v9, a0
700; RV32I-NEXT:    vsub.vv v8, v8, v9
701; RV32I-NEXT:    lui a0, 3
702; RV32I-NEXT:    addi a0, a0, 819
703; RV32I-NEXT:    vand.vx v9, v8, a0
704; RV32I-NEXT:    vsrl.vi v8, v8, 2
705; RV32I-NEXT:    vand.vx v8, v8, a0
706; RV32I-NEXT:    vadd.vv v8, v9, v8
707; RV32I-NEXT:    vsrl.vi v9, v8, 4
708; RV32I-NEXT:    vadd.vv v8, v8, v9
709; RV32I-NEXT:    lui a0, 1
710; RV32I-NEXT:    addi a0, a0, -241
711; RV32I-NEXT:    vand.vx v8, v8, a0
712; RV32I-NEXT:    li a0, 257
713; RV32I-NEXT:    vmul.vx v8, v8, a0
714; RV32I-NEXT:    vsrl.vi v8, v8, 8
715; RV32I-NEXT:    ret
716;
717; RV64I-LABEL: cttz_nxv4i16:
718; RV64I:       # %bb.0:
719; RV64I-NEXT:    li a0, 1
720; RV64I-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
721; RV64I-NEXT:    vsub.vx v9, v8, a0
722; RV64I-NEXT:    vxor.vi v8, v8, -1
723; RV64I-NEXT:    vand.vv v8, v8, v9
724; RV64I-NEXT:    vsrl.vi v9, v8, 1
725; RV64I-NEXT:    lui a0, 5
726; RV64I-NEXT:    addiw a0, a0, 1365
727; RV64I-NEXT:    vand.vx v9, v9, a0
728; RV64I-NEXT:    vsub.vv v8, v8, v9
729; RV64I-NEXT:    lui a0, 3
730; RV64I-NEXT:    addiw a0, a0, 819
731; RV64I-NEXT:    vand.vx v9, v8, a0
732; RV64I-NEXT:    vsrl.vi v8, v8, 2
733; RV64I-NEXT:    vand.vx v8, v8, a0
734; RV64I-NEXT:    vadd.vv v8, v9, v8
735; RV64I-NEXT:    vsrl.vi v9, v8, 4
736; RV64I-NEXT:    vadd.vv v8, v8, v9
737; RV64I-NEXT:    lui a0, 1
738; RV64I-NEXT:    addiw a0, a0, -241
739; RV64I-NEXT:    vand.vx v8, v8, a0
740; RV64I-NEXT:    li a0, 257
741; RV64I-NEXT:    vmul.vx v8, v8, a0
742; RV64I-NEXT:    vsrl.vi v8, v8, 8
743; RV64I-NEXT:    ret
744;
745; RV32D-LABEL: cttz_nxv4i16:
746; RV32D:       # %bb.0:
747; RV32D-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
748; RV32D-NEXT:    vmv.v.i v9, 0
749; RV32D-NEXT:    vmseq.vv v0, v9, v8
750; RV32D-NEXT:    vrsub.vi v9, v8, 0
751; RV32D-NEXT:    vand.vv v8, v8, v9
752; RV32D-NEXT:    vfwcvt.f.xu.v v10, v8
753; RV32D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
754; RV32D-NEXT:    vsrl.vi v8, v10, 23
755; RV32D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
756; RV32D-NEXT:    vnsrl.wi v10, v8, 0
757; RV32D-NEXT:    li a0, 127
758; RV32D-NEXT:    vsub.vx v8, v10, a0
759; RV32D-NEXT:    li a0, 16
760; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
761; RV32D-NEXT:    ret
762;
763; RV64D-LABEL: cttz_nxv4i16:
764; RV64D:       # %bb.0:
765; RV64D-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
766; RV64D-NEXT:    vmv.v.i v9, 0
767; RV64D-NEXT:    vmseq.vv v0, v9, v8
768; RV64D-NEXT:    vrsub.vi v9, v8, 0
769; RV64D-NEXT:    vand.vv v8, v8, v9
770; RV64D-NEXT:    vfwcvt.f.xu.v v10, v8
771; RV64D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
772; RV64D-NEXT:    vsrl.vi v8, v10, 23
773; RV64D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
774; RV64D-NEXT:    vnsrl.wi v10, v8, 0
775; RV64D-NEXT:    li a0, 127
776; RV64D-NEXT:    vsub.vx v8, v10, a0
777; RV64D-NEXT:    li a0, 16
778; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
779; RV64D-NEXT:    ret
780  %a = call <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 false)
781  ret <vscale x 4 x i16> %a
782}
783declare <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16>, i1)
784
785define <vscale x 8 x i16> @cttz_nxv8i16(<vscale x 8 x i16> %va) {
786; RV32I-LABEL: cttz_nxv8i16:
787; RV32I:       # %bb.0:
788; RV32I-NEXT:    li a0, 1
789; RV32I-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
790; RV32I-NEXT:    vsub.vx v10, v8, a0
791; RV32I-NEXT:    vxor.vi v8, v8, -1
792; RV32I-NEXT:    vand.vv v8, v8, v10
793; RV32I-NEXT:    vsrl.vi v10, v8, 1
794; RV32I-NEXT:    lui a0, 5
795; RV32I-NEXT:    addi a0, a0, 1365
796; RV32I-NEXT:    vand.vx v10, v10, a0
797; RV32I-NEXT:    vsub.vv v8, v8, v10
798; RV32I-NEXT:    lui a0, 3
799; RV32I-NEXT:    addi a0, a0, 819
800; RV32I-NEXT:    vand.vx v10, v8, a0
801; RV32I-NEXT:    vsrl.vi v8, v8, 2
802; RV32I-NEXT:    vand.vx v8, v8, a0
803; RV32I-NEXT:    vadd.vv v8, v10, v8
804; RV32I-NEXT:    vsrl.vi v10, v8, 4
805; RV32I-NEXT:    vadd.vv v8, v8, v10
806; RV32I-NEXT:    lui a0, 1
807; RV32I-NEXT:    addi a0, a0, -241
808; RV32I-NEXT:    vand.vx v8, v8, a0
809; RV32I-NEXT:    li a0, 257
810; RV32I-NEXT:    vmul.vx v8, v8, a0
811; RV32I-NEXT:    vsrl.vi v8, v8, 8
812; RV32I-NEXT:    ret
813;
814; RV64I-LABEL: cttz_nxv8i16:
815; RV64I:       # %bb.0:
816; RV64I-NEXT:    li a0, 1
817; RV64I-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
818; RV64I-NEXT:    vsub.vx v10, v8, a0
819; RV64I-NEXT:    vxor.vi v8, v8, -1
820; RV64I-NEXT:    vand.vv v8, v8, v10
821; RV64I-NEXT:    vsrl.vi v10, v8, 1
822; RV64I-NEXT:    lui a0, 5
823; RV64I-NEXT:    addiw a0, a0, 1365
824; RV64I-NEXT:    vand.vx v10, v10, a0
825; RV64I-NEXT:    vsub.vv v8, v8, v10
826; RV64I-NEXT:    lui a0, 3
827; RV64I-NEXT:    addiw a0, a0, 819
828; RV64I-NEXT:    vand.vx v10, v8, a0
829; RV64I-NEXT:    vsrl.vi v8, v8, 2
830; RV64I-NEXT:    vand.vx v8, v8, a0
831; RV64I-NEXT:    vadd.vv v8, v10, v8
832; RV64I-NEXT:    vsrl.vi v10, v8, 4
833; RV64I-NEXT:    vadd.vv v8, v8, v10
834; RV64I-NEXT:    lui a0, 1
835; RV64I-NEXT:    addiw a0, a0, -241
836; RV64I-NEXT:    vand.vx v8, v8, a0
837; RV64I-NEXT:    li a0, 257
838; RV64I-NEXT:    vmul.vx v8, v8, a0
839; RV64I-NEXT:    vsrl.vi v8, v8, 8
840; RV64I-NEXT:    ret
841;
842; RV32D-LABEL: cttz_nxv8i16:
843; RV32D:       # %bb.0:
844; RV32D-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
845; RV32D-NEXT:    vmv.v.i v10, 0
846; RV32D-NEXT:    vmseq.vv v0, v10, v8
847; RV32D-NEXT:    vrsub.vi v10, v8, 0
848; RV32D-NEXT:    vand.vv v8, v8, v10
849; RV32D-NEXT:    vfwcvt.f.xu.v v12, v8
850; RV32D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
851; RV32D-NEXT:    vsrl.vi v8, v12, 23
852; RV32D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
853; RV32D-NEXT:    vnsrl.wi v12, v8, 0
854; RV32D-NEXT:    li a0, 127
855; RV32D-NEXT:    vsub.vx v8, v12, a0
856; RV32D-NEXT:    li a0, 16
857; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
858; RV32D-NEXT:    ret
859;
860; RV64D-LABEL: cttz_nxv8i16:
861; RV64D:       # %bb.0:
862; RV64D-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
863; RV64D-NEXT:    vmv.v.i v10, 0
864; RV64D-NEXT:    vmseq.vv v0, v10, v8
865; RV64D-NEXT:    vrsub.vi v10, v8, 0
866; RV64D-NEXT:    vand.vv v8, v8, v10
867; RV64D-NEXT:    vfwcvt.f.xu.v v12, v8
868; RV64D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
869; RV64D-NEXT:    vsrl.vi v8, v12, 23
870; RV64D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
871; RV64D-NEXT:    vnsrl.wi v12, v8, 0
872; RV64D-NEXT:    li a0, 127
873; RV64D-NEXT:    vsub.vx v8, v12, a0
874; RV64D-NEXT:    li a0, 16
875; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
876; RV64D-NEXT:    ret
877  %a = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 false)
878  ret <vscale x 8 x i16> %a
879}
880declare <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16>, i1)
881
882define <vscale x 16 x i16> @cttz_nxv16i16(<vscale x 16 x i16> %va) {
883; RV32I-LABEL: cttz_nxv16i16:
884; RV32I:       # %bb.0:
885; RV32I-NEXT:    li a0, 1
886; RV32I-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
887; RV32I-NEXT:    vsub.vx v12, v8, a0
888; RV32I-NEXT:    vxor.vi v8, v8, -1
889; RV32I-NEXT:    vand.vv v8, v8, v12
890; RV32I-NEXT:    vsrl.vi v12, v8, 1
891; RV32I-NEXT:    lui a0, 5
892; RV32I-NEXT:    addi a0, a0, 1365
893; RV32I-NEXT:    vand.vx v12, v12, a0
894; RV32I-NEXT:    vsub.vv v8, v8, v12
895; RV32I-NEXT:    lui a0, 3
896; RV32I-NEXT:    addi a0, a0, 819
897; RV32I-NEXT:    vand.vx v12, v8, a0
898; RV32I-NEXT:    vsrl.vi v8, v8, 2
899; RV32I-NEXT:    vand.vx v8, v8, a0
900; RV32I-NEXT:    vadd.vv v8, v12, v8
901; RV32I-NEXT:    vsrl.vi v12, v8, 4
902; RV32I-NEXT:    vadd.vv v8, v8, v12
903; RV32I-NEXT:    lui a0, 1
904; RV32I-NEXT:    addi a0, a0, -241
905; RV32I-NEXT:    vand.vx v8, v8, a0
906; RV32I-NEXT:    li a0, 257
907; RV32I-NEXT:    vmul.vx v8, v8, a0
908; RV32I-NEXT:    vsrl.vi v8, v8, 8
909; RV32I-NEXT:    ret
910;
911; RV64I-LABEL: cttz_nxv16i16:
912; RV64I:       # %bb.0:
913; RV64I-NEXT:    li a0, 1
914; RV64I-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
915; RV64I-NEXT:    vsub.vx v12, v8, a0
916; RV64I-NEXT:    vxor.vi v8, v8, -1
917; RV64I-NEXT:    vand.vv v8, v8, v12
918; RV64I-NEXT:    vsrl.vi v12, v8, 1
919; RV64I-NEXT:    lui a0, 5
920; RV64I-NEXT:    addiw a0, a0, 1365
921; RV64I-NEXT:    vand.vx v12, v12, a0
922; RV64I-NEXT:    vsub.vv v8, v8, v12
923; RV64I-NEXT:    lui a0, 3
924; RV64I-NEXT:    addiw a0, a0, 819
925; RV64I-NEXT:    vand.vx v12, v8, a0
926; RV64I-NEXT:    vsrl.vi v8, v8, 2
927; RV64I-NEXT:    vand.vx v8, v8, a0
928; RV64I-NEXT:    vadd.vv v8, v12, v8
929; RV64I-NEXT:    vsrl.vi v12, v8, 4
930; RV64I-NEXT:    vadd.vv v8, v8, v12
931; RV64I-NEXT:    lui a0, 1
932; RV64I-NEXT:    addiw a0, a0, -241
933; RV64I-NEXT:    vand.vx v8, v8, a0
934; RV64I-NEXT:    li a0, 257
935; RV64I-NEXT:    vmul.vx v8, v8, a0
936; RV64I-NEXT:    vsrl.vi v8, v8, 8
937; RV64I-NEXT:    ret
938;
939; RV32D-LABEL: cttz_nxv16i16:
940; RV32D:       # %bb.0:
941; RV32D-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
942; RV32D-NEXT:    vmv.v.i v12, 0
943; RV32D-NEXT:    vmseq.vv v0, v12, v8
944; RV32D-NEXT:    vrsub.vi v12, v8, 0
945; RV32D-NEXT:    vand.vv v8, v8, v12
946; RV32D-NEXT:    vfwcvt.f.xu.v v16, v8
947; RV32D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
948; RV32D-NEXT:    vsrl.vi v8, v16, 23
949; RV32D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
950; RV32D-NEXT:    vnsrl.wi v16, v8, 0
951; RV32D-NEXT:    li a0, 127
952; RV32D-NEXT:    vsub.vx v8, v16, a0
953; RV32D-NEXT:    li a0, 16
954; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
955; RV32D-NEXT:    ret
956;
957; RV64D-LABEL: cttz_nxv16i16:
958; RV64D:       # %bb.0:
959; RV64D-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
960; RV64D-NEXT:    vmv.v.i v12, 0
961; RV64D-NEXT:    vmseq.vv v0, v12, v8
962; RV64D-NEXT:    vrsub.vi v12, v8, 0
963; RV64D-NEXT:    vand.vv v8, v8, v12
964; RV64D-NEXT:    vfwcvt.f.xu.v v16, v8
965; RV64D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
966; RV64D-NEXT:    vsrl.vi v8, v16, 23
967; RV64D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
968; RV64D-NEXT:    vnsrl.wi v16, v8, 0
969; RV64D-NEXT:    li a0, 127
970; RV64D-NEXT:    vsub.vx v8, v16, a0
971; RV64D-NEXT:    li a0, 16
972; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
973; RV64D-NEXT:    ret
974  %a = call <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 false)
975  ret <vscale x 16 x i16> %a
976}
977declare <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16>, i1)
978
979define <vscale x 32 x i16> @cttz_nxv32i16(<vscale x 32 x i16> %va) {
980; RV32-LABEL: cttz_nxv32i16:
981; RV32:       # %bb.0:
982; RV32-NEXT:    li a0, 1
983; RV32-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
984; RV32-NEXT:    vsub.vx v16, v8, a0
985; RV32-NEXT:    vxor.vi v8, v8, -1
986; RV32-NEXT:    vand.vv v8, v8, v16
987; RV32-NEXT:    vsrl.vi v16, v8, 1
988; RV32-NEXT:    lui a0, 5
989; RV32-NEXT:    addi a0, a0, 1365
990; RV32-NEXT:    vand.vx v16, v16, a0
991; RV32-NEXT:    vsub.vv v8, v8, v16
992; RV32-NEXT:    lui a0, 3
993; RV32-NEXT:    addi a0, a0, 819
994; RV32-NEXT:    vand.vx v16, v8, a0
995; RV32-NEXT:    vsrl.vi v8, v8, 2
996; RV32-NEXT:    vand.vx v8, v8, a0
997; RV32-NEXT:    vadd.vv v8, v16, v8
998; RV32-NEXT:    vsrl.vi v16, v8, 4
999; RV32-NEXT:    vadd.vv v8, v8, v16
1000; RV32-NEXT:    lui a0, 1
1001; RV32-NEXT:    addi a0, a0, -241
1002; RV32-NEXT:    vand.vx v8, v8, a0
1003; RV32-NEXT:    li a0, 257
1004; RV32-NEXT:    vmul.vx v8, v8, a0
1005; RV32-NEXT:    vsrl.vi v8, v8, 8
1006; RV32-NEXT:    ret
1007;
1008; RV64-LABEL: cttz_nxv32i16:
1009; RV64:       # %bb.0:
1010; RV64-NEXT:    li a0, 1
1011; RV64-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
1012; RV64-NEXT:    vsub.vx v16, v8, a0
1013; RV64-NEXT:    vxor.vi v8, v8, -1
1014; RV64-NEXT:    vand.vv v8, v8, v16
1015; RV64-NEXT:    vsrl.vi v16, v8, 1
1016; RV64-NEXT:    lui a0, 5
1017; RV64-NEXT:    addiw a0, a0, 1365
1018; RV64-NEXT:    vand.vx v16, v16, a0
1019; RV64-NEXT:    vsub.vv v8, v8, v16
1020; RV64-NEXT:    lui a0, 3
1021; RV64-NEXT:    addiw a0, a0, 819
1022; RV64-NEXT:    vand.vx v16, v8, a0
1023; RV64-NEXT:    vsrl.vi v8, v8, 2
1024; RV64-NEXT:    vand.vx v8, v8, a0
1025; RV64-NEXT:    vadd.vv v8, v16, v8
1026; RV64-NEXT:    vsrl.vi v16, v8, 4
1027; RV64-NEXT:    vadd.vv v8, v8, v16
1028; RV64-NEXT:    lui a0, 1
1029; RV64-NEXT:    addiw a0, a0, -241
1030; RV64-NEXT:    vand.vx v8, v8, a0
1031; RV64-NEXT:    li a0, 257
1032; RV64-NEXT:    vmul.vx v8, v8, a0
1033; RV64-NEXT:    vsrl.vi v8, v8, 8
1034; RV64-NEXT:    ret
1035  %a = call <vscale x 32 x i16> @llvm.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 false)
1036  ret <vscale x 32 x i16> %a
1037}
1038declare <vscale x 32 x i16> @llvm.cttz.nxv32i16(<vscale x 32 x i16>, i1)
1039
1040define <vscale x 1 x i32> @cttz_nxv1i32(<vscale x 1 x i32> %va) {
1041; RV32I-LABEL: cttz_nxv1i32:
1042; RV32I:       # %bb.0:
1043; RV32I-NEXT:    li a0, 1
1044; RV32I-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
1045; RV32I-NEXT:    vsub.vx v9, v8, a0
1046; RV32I-NEXT:    vxor.vi v8, v8, -1
1047; RV32I-NEXT:    vand.vv v8, v8, v9
1048; RV32I-NEXT:    vsrl.vi v9, v8, 1
1049; RV32I-NEXT:    lui a0, 349525
1050; RV32I-NEXT:    addi a0, a0, 1365
1051; RV32I-NEXT:    vand.vx v9, v9, a0
1052; RV32I-NEXT:    vsub.vv v8, v8, v9
1053; RV32I-NEXT:    lui a0, 209715
1054; RV32I-NEXT:    addi a0, a0, 819
1055; RV32I-NEXT:    vand.vx v9, v8, a0
1056; RV32I-NEXT:    vsrl.vi v8, v8, 2
1057; RV32I-NEXT:    vand.vx v8, v8, a0
1058; RV32I-NEXT:    vadd.vv v8, v9, v8
1059; RV32I-NEXT:    vsrl.vi v9, v8, 4
1060; RV32I-NEXT:    vadd.vv v8, v8, v9
1061; RV32I-NEXT:    lui a0, 61681
1062; RV32I-NEXT:    addi a0, a0, -241
1063; RV32I-NEXT:    vand.vx v8, v8, a0
1064; RV32I-NEXT:    lui a0, 4112
1065; RV32I-NEXT:    addi a0, a0, 257
1066; RV32I-NEXT:    vmul.vx v8, v8, a0
1067; RV32I-NEXT:    vsrl.vi v8, v8, 24
1068; RV32I-NEXT:    ret
1069;
1070; RV64I-LABEL: cttz_nxv1i32:
1071; RV64I:       # %bb.0:
1072; RV64I-NEXT:    li a0, 1
1073; RV64I-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
1074; RV64I-NEXT:    vsub.vx v9, v8, a0
1075; RV64I-NEXT:    vxor.vi v8, v8, -1
1076; RV64I-NEXT:    vand.vv v8, v8, v9
1077; RV64I-NEXT:    vsrl.vi v9, v8, 1
1078; RV64I-NEXT:    lui a0, 349525
1079; RV64I-NEXT:    addiw a0, a0, 1365
1080; RV64I-NEXT:    vand.vx v9, v9, a0
1081; RV64I-NEXT:    vsub.vv v8, v8, v9
1082; RV64I-NEXT:    lui a0, 209715
1083; RV64I-NEXT:    addiw a0, a0, 819
1084; RV64I-NEXT:    vand.vx v9, v8, a0
1085; RV64I-NEXT:    vsrl.vi v8, v8, 2
1086; RV64I-NEXT:    vand.vx v8, v8, a0
1087; RV64I-NEXT:    vadd.vv v8, v9, v8
1088; RV64I-NEXT:    vsrl.vi v9, v8, 4
1089; RV64I-NEXT:    vadd.vv v8, v8, v9
1090; RV64I-NEXT:    lui a0, 61681
1091; RV64I-NEXT:    addiw a0, a0, -241
1092; RV64I-NEXT:    vand.vx v8, v8, a0
1093; RV64I-NEXT:    lui a0, 4112
1094; RV64I-NEXT:    addiw a0, a0, 257
1095; RV64I-NEXT:    vmul.vx v8, v8, a0
1096; RV64I-NEXT:    vsrl.vi v8, v8, 24
1097; RV64I-NEXT:    ret
1098;
1099; RV32D-LABEL: cttz_nxv1i32:
1100; RV32D:       # %bb.0:
1101; RV32D-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
1102; RV32D-NEXT:    vrsub.vi v9, v8, 0
1103; RV32D-NEXT:    vand.vv v9, v8, v9
1104; RV32D-NEXT:    vfwcvt.f.xu.v v10, v9
1105; RV32D-NEXT:    li a0, 52
1106; RV32D-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
1107; RV32D-NEXT:    vsrl.vx v9, v10, a0
1108; RV32D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
1109; RV32D-NEXT:    vnsrl.wi v9, v9, 0
1110; RV32D-NEXT:    li a0, 1023
1111; RV32D-NEXT:    vsub.vx v9, v9, a0
1112; RV32D-NEXT:    vmseq.vi v0, v8, 0
1113; RV32D-NEXT:    li a0, 32
1114; RV32D-NEXT:    vmerge.vxm v8, v9, a0, v0
1115; RV32D-NEXT:    ret
1116;
1117; RV64D-LABEL: cttz_nxv1i32:
1118; RV64D:       # %bb.0:
1119; RV64D-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
1120; RV64D-NEXT:    vmv.v.i v9, 0
1121; RV64D-NEXT:    vmseq.vv v0, v9, v8
1122; RV64D-NEXT:    vrsub.vi v9, v8, 0
1123; RV64D-NEXT:    vand.vv v8, v8, v9
1124; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
1125; RV64D-NEXT:    li a0, 52
1126; RV64D-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
1127; RV64D-NEXT:    vsrl.vx v8, v9, a0
1128; RV64D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
1129; RV64D-NEXT:    vnsrl.wi v8, v8, 0
1130; RV64D-NEXT:    li a0, 1023
1131; RV64D-NEXT:    vsub.vx v8, v8, a0
1132; RV64D-NEXT:    li a0, 32
1133; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
1134; RV64D-NEXT:    ret
1135  %a = call <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 false)
1136  ret <vscale x 1 x i32> %a
1137}
1138declare <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32>, i1)
1139
1140define <vscale x 2 x i32> @cttz_nxv2i32(<vscale x 2 x i32> %va) {
1141; RV32I-LABEL: cttz_nxv2i32:
1142; RV32I:       # %bb.0:
1143; RV32I-NEXT:    li a0, 1
1144; RV32I-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
1145; RV32I-NEXT:    vsub.vx v9, v8, a0
1146; RV32I-NEXT:    vxor.vi v8, v8, -1
1147; RV32I-NEXT:    vand.vv v8, v8, v9
1148; RV32I-NEXT:    vsrl.vi v9, v8, 1
1149; RV32I-NEXT:    lui a0, 349525
1150; RV32I-NEXT:    addi a0, a0, 1365
1151; RV32I-NEXT:    vand.vx v9, v9, a0
1152; RV32I-NEXT:    vsub.vv v8, v8, v9
1153; RV32I-NEXT:    lui a0, 209715
1154; RV32I-NEXT:    addi a0, a0, 819
1155; RV32I-NEXT:    vand.vx v9, v8, a0
1156; RV32I-NEXT:    vsrl.vi v8, v8, 2
1157; RV32I-NEXT:    vand.vx v8, v8, a0
1158; RV32I-NEXT:    vadd.vv v8, v9, v8
1159; RV32I-NEXT:    vsrl.vi v9, v8, 4
1160; RV32I-NEXT:    vadd.vv v8, v8, v9
1161; RV32I-NEXT:    lui a0, 61681
1162; RV32I-NEXT:    addi a0, a0, -241
1163; RV32I-NEXT:    vand.vx v8, v8, a0
1164; RV32I-NEXT:    lui a0, 4112
1165; RV32I-NEXT:    addi a0, a0, 257
1166; RV32I-NEXT:    vmul.vx v8, v8, a0
1167; RV32I-NEXT:    vsrl.vi v8, v8, 24
1168; RV32I-NEXT:    ret
1169;
1170; RV64I-LABEL: cttz_nxv2i32:
1171; RV64I:       # %bb.0:
1172; RV64I-NEXT:    li a0, 1
1173; RV64I-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
1174; RV64I-NEXT:    vsub.vx v9, v8, a0
1175; RV64I-NEXT:    vxor.vi v8, v8, -1
1176; RV64I-NEXT:    vand.vv v8, v8, v9
1177; RV64I-NEXT:    vsrl.vi v9, v8, 1
1178; RV64I-NEXT:    lui a0, 349525
1179; RV64I-NEXT:    addiw a0, a0, 1365
1180; RV64I-NEXT:    vand.vx v9, v9, a0
1181; RV64I-NEXT:    vsub.vv v8, v8, v9
1182; RV64I-NEXT:    lui a0, 209715
1183; RV64I-NEXT:    addiw a0, a0, 819
1184; RV64I-NEXT:    vand.vx v9, v8, a0
1185; RV64I-NEXT:    vsrl.vi v8, v8, 2
1186; RV64I-NEXT:    vand.vx v8, v8, a0
1187; RV64I-NEXT:    vadd.vv v8, v9, v8
1188; RV64I-NEXT:    vsrl.vi v9, v8, 4
1189; RV64I-NEXT:    vadd.vv v8, v8, v9
1190; RV64I-NEXT:    lui a0, 61681
1191; RV64I-NEXT:    addiw a0, a0, -241
1192; RV64I-NEXT:    vand.vx v8, v8, a0
1193; RV64I-NEXT:    lui a0, 4112
1194; RV64I-NEXT:    addiw a0, a0, 257
1195; RV64I-NEXT:    vmul.vx v8, v8, a0
1196; RV64I-NEXT:    vsrl.vi v8, v8, 24
1197; RV64I-NEXT:    ret
1198;
1199; RV32D-LABEL: cttz_nxv2i32:
1200; RV32D:       # %bb.0:
1201; RV32D-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
1202; RV32D-NEXT:    vrsub.vi v9, v8, 0
1203; RV32D-NEXT:    vand.vv v9, v8, v9
1204; RV32D-NEXT:    vfwcvt.f.xu.v v10, v9
1205; RV32D-NEXT:    li a0, 52
1206; RV32D-NEXT:    vsetvli zero, zero, e64, m2, ta, mu
1207; RV32D-NEXT:    vsrl.vx v10, v10, a0
1208; RV32D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
1209; RV32D-NEXT:    vnsrl.wi v9, v10, 0
1210; RV32D-NEXT:    li a0, 1023
1211; RV32D-NEXT:    vsub.vx v9, v9, a0
1212; RV32D-NEXT:    vmseq.vi v0, v8, 0
1213; RV32D-NEXT:    li a0, 32
1214; RV32D-NEXT:    vmerge.vxm v8, v9, a0, v0
1215; RV32D-NEXT:    ret
1216;
1217; RV64D-LABEL: cttz_nxv2i32:
1218; RV64D:       # %bb.0:
1219; RV64D-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
1220; RV64D-NEXT:    vmv.v.i v9, 0
1221; RV64D-NEXT:    vmseq.vv v0, v9, v8
1222; RV64D-NEXT:    vrsub.vi v9, v8, 0
1223; RV64D-NEXT:    vand.vv v8, v8, v9
1224; RV64D-NEXT:    vfwcvt.f.xu.v v10, v8
1225; RV64D-NEXT:    li a0, 52
1226; RV64D-NEXT:    vsetvli zero, zero, e64, m2, ta, mu
1227; RV64D-NEXT:    vsrl.vx v8, v10, a0
1228; RV64D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
1229; RV64D-NEXT:    vnsrl.wi v10, v8, 0
1230; RV64D-NEXT:    li a0, 1023
1231; RV64D-NEXT:    vsub.vx v8, v10, a0
1232; RV64D-NEXT:    li a0, 32
1233; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
1234; RV64D-NEXT:    ret
1235  %a = call <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 false)
1236  ret <vscale x 2 x i32> %a
1237}
1238declare <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32>, i1)
1239
1240define <vscale x 4 x i32> @cttz_nxv4i32(<vscale x 4 x i32> %va) {
1241; RV32I-LABEL: cttz_nxv4i32:
1242; RV32I:       # %bb.0:
1243; RV32I-NEXT:    li a0, 1
1244; RV32I-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
1245; RV32I-NEXT:    vsub.vx v10, v8, a0
1246; RV32I-NEXT:    vxor.vi v8, v8, -1
1247; RV32I-NEXT:    vand.vv v8, v8, v10
1248; RV32I-NEXT:    vsrl.vi v10, v8, 1
1249; RV32I-NEXT:    lui a0, 349525
1250; RV32I-NEXT:    addi a0, a0, 1365
1251; RV32I-NEXT:    vand.vx v10, v10, a0
1252; RV32I-NEXT:    vsub.vv v8, v8, v10
1253; RV32I-NEXT:    lui a0, 209715
1254; RV32I-NEXT:    addi a0, a0, 819
1255; RV32I-NEXT:    vand.vx v10, v8, a0
1256; RV32I-NEXT:    vsrl.vi v8, v8, 2
1257; RV32I-NEXT:    vand.vx v8, v8, a0
1258; RV32I-NEXT:    vadd.vv v8, v10, v8
1259; RV32I-NEXT:    vsrl.vi v10, v8, 4
1260; RV32I-NEXT:    vadd.vv v8, v8, v10
1261; RV32I-NEXT:    lui a0, 61681
1262; RV32I-NEXT:    addi a0, a0, -241
1263; RV32I-NEXT:    vand.vx v8, v8, a0
1264; RV32I-NEXT:    lui a0, 4112
1265; RV32I-NEXT:    addi a0, a0, 257
1266; RV32I-NEXT:    vmul.vx v8, v8, a0
1267; RV32I-NEXT:    vsrl.vi v8, v8, 24
1268; RV32I-NEXT:    ret
1269;
1270; RV64I-LABEL: cttz_nxv4i32:
1271; RV64I:       # %bb.0:
1272; RV64I-NEXT:    li a0, 1
1273; RV64I-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
1274; RV64I-NEXT:    vsub.vx v10, v8, a0
1275; RV64I-NEXT:    vxor.vi v8, v8, -1
1276; RV64I-NEXT:    vand.vv v8, v8, v10
1277; RV64I-NEXT:    vsrl.vi v10, v8, 1
1278; RV64I-NEXT:    lui a0, 349525
1279; RV64I-NEXT:    addiw a0, a0, 1365
1280; RV64I-NEXT:    vand.vx v10, v10, a0
1281; RV64I-NEXT:    vsub.vv v8, v8, v10
1282; RV64I-NEXT:    lui a0, 209715
1283; RV64I-NEXT:    addiw a0, a0, 819
1284; RV64I-NEXT:    vand.vx v10, v8, a0
1285; RV64I-NEXT:    vsrl.vi v8, v8, 2
1286; RV64I-NEXT:    vand.vx v8, v8, a0
1287; RV64I-NEXT:    vadd.vv v8, v10, v8
1288; RV64I-NEXT:    vsrl.vi v10, v8, 4
1289; RV64I-NEXT:    vadd.vv v8, v8, v10
1290; RV64I-NEXT:    lui a0, 61681
1291; RV64I-NEXT:    addiw a0, a0, -241
1292; RV64I-NEXT:    vand.vx v8, v8, a0
1293; RV64I-NEXT:    lui a0, 4112
1294; RV64I-NEXT:    addiw a0, a0, 257
1295; RV64I-NEXT:    vmul.vx v8, v8, a0
1296; RV64I-NEXT:    vsrl.vi v8, v8, 24
1297; RV64I-NEXT:    ret
1298;
1299; RV32D-LABEL: cttz_nxv4i32:
1300; RV32D:       # %bb.0:
1301; RV32D-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
1302; RV32D-NEXT:    vrsub.vi v10, v8, 0
1303; RV32D-NEXT:    vand.vv v10, v8, v10
1304; RV32D-NEXT:    vfwcvt.f.xu.v v12, v10
1305; RV32D-NEXT:    li a0, 52
1306; RV32D-NEXT:    vsetvli zero, zero, e64, m4, ta, mu
1307; RV32D-NEXT:    vsrl.vx v12, v12, a0
1308; RV32D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
1309; RV32D-NEXT:    vnsrl.wi v10, v12, 0
1310; RV32D-NEXT:    li a0, 1023
1311; RV32D-NEXT:    vsub.vx v10, v10, a0
1312; RV32D-NEXT:    vmseq.vi v0, v8, 0
1313; RV32D-NEXT:    li a0, 32
1314; RV32D-NEXT:    vmerge.vxm v8, v10, a0, v0
1315; RV32D-NEXT:    ret
1316;
1317; RV64D-LABEL: cttz_nxv4i32:
1318; RV64D:       # %bb.0:
1319; RV64D-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
1320; RV64D-NEXT:    vmv.v.i v10, 0
1321; RV64D-NEXT:    vmseq.vv v0, v10, v8
1322; RV64D-NEXT:    vrsub.vi v10, v8, 0
1323; RV64D-NEXT:    vand.vv v8, v8, v10
1324; RV64D-NEXT:    vfwcvt.f.xu.v v12, v8
1325; RV64D-NEXT:    li a0, 52
1326; RV64D-NEXT:    vsetvli zero, zero, e64, m4, ta, mu
1327; RV64D-NEXT:    vsrl.vx v8, v12, a0
1328; RV64D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
1329; RV64D-NEXT:    vnsrl.wi v12, v8, 0
1330; RV64D-NEXT:    li a0, 1023
1331; RV64D-NEXT:    vsub.vx v8, v12, a0
1332; RV64D-NEXT:    li a0, 32
1333; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
1334; RV64D-NEXT:    ret
1335  %a = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 false)
1336  ret <vscale x 4 x i32> %a
1337}
1338declare <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32>, i1)
1339
1340define <vscale x 8 x i32> @cttz_nxv8i32(<vscale x 8 x i32> %va) {
1341; RV32I-LABEL: cttz_nxv8i32:
1342; RV32I:       # %bb.0:
1343; RV32I-NEXT:    li a0, 1
1344; RV32I-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1345; RV32I-NEXT:    vsub.vx v12, v8, a0
1346; RV32I-NEXT:    vxor.vi v8, v8, -1
1347; RV32I-NEXT:    vand.vv v8, v8, v12
1348; RV32I-NEXT:    vsrl.vi v12, v8, 1
1349; RV32I-NEXT:    lui a0, 349525
1350; RV32I-NEXT:    addi a0, a0, 1365
1351; RV32I-NEXT:    vand.vx v12, v12, a0
1352; RV32I-NEXT:    vsub.vv v8, v8, v12
1353; RV32I-NEXT:    lui a0, 209715
1354; RV32I-NEXT:    addi a0, a0, 819
1355; RV32I-NEXT:    vand.vx v12, v8, a0
1356; RV32I-NEXT:    vsrl.vi v8, v8, 2
1357; RV32I-NEXT:    vand.vx v8, v8, a0
1358; RV32I-NEXT:    vadd.vv v8, v12, v8
1359; RV32I-NEXT:    vsrl.vi v12, v8, 4
1360; RV32I-NEXT:    vadd.vv v8, v8, v12
1361; RV32I-NEXT:    lui a0, 61681
1362; RV32I-NEXT:    addi a0, a0, -241
1363; RV32I-NEXT:    vand.vx v8, v8, a0
1364; RV32I-NEXT:    lui a0, 4112
1365; RV32I-NEXT:    addi a0, a0, 257
1366; RV32I-NEXT:    vmul.vx v8, v8, a0
1367; RV32I-NEXT:    vsrl.vi v8, v8, 24
1368; RV32I-NEXT:    ret
1369;
1370; RV64I-LABEL: cttz_nxv8i32:
1371; RV64I:       # %bb.0:
1372; RV64I-NEXT:    li a0, 1
1373; RV64I-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1374; RV64I-NEXT:    vsub.vx v12, v8, a0
1375; RV64I-NEXT:    vxor.vi v8, v8, -1
1376; RV64I-NEXT:    vand.vv v8, v8, v12
1377; RV64I-NEXT:    vsrl.vi v12, v8, 1
1378; RV64I-NEXT:    lui a0, 349525
1379; RV64I-NEXT:    addiw a0, a0, 1365
1380; RV64I-NEXT:    vand.vx v12, v12, a0
1381; RV64I-NEXT:    vsub.vv v8, v8, v12
1382; RV64I-NEXT:    lui a0, 209715
1383; RV64I-NEXT:    addiw a0, a0, 819
1384; RV64I-NEXT:    vand.vx v12, v8, a0
1385; RV64I-NEXT:    vsrl.vi v8, v8, 2
1386; RV64I-NEXT:    vand.vx v8, v8, a0
1387; RV64I-NEXT:    vadd.vv v8, v12, v8
1388; RV64I-NEXT:    vsrl.vi v12, v8, 4
1389; RV64I-NEXT:    vadd.vv v8, v8, v12
1390; RV64I-NEXT:    lui a0, 61681
1391; RV64I-NEXT:    addiw a0, a0, -241
1392; RV64I-NEXT:    vand.vx v8, v8, a0
1393; RV64I-NEXT:    lui a0, 4112
1394; RV64I-NEXT:    addiw a0, a0, 257
1395; RV64I-NEXT:    vmul.vx v8, v8, a0
1396; RV64I-NEXT:    vsrl.vi v8, v8, 24
1397; RV64I-NEXT:    ret
1398;
1399; RV32D-LABEL: cttz_nxv8i32:
1400; RV32D:       # %bb.0:
1401; RV32D-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1402; RV32D-NEXT:    vrsub.vi v12, v8, 0
1403; RV32D-NEXT:    vand.vv v12, v8, v12
1404; RV32D-NEXT:    vfwcvt.f.xu.v v16, v12
1405; RV32D-NEXT:    li a0, 52
1406; RV32D-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
1407; RV32D-NEXT:    vsrl.vx v16, v16, a0
1408; RV32D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
1409; RV32D-NEXT:    vnsrl.wi v12, v16, 0
1410; RV32D-NEXT:    li a0, 1023
1411; RV32D-NEXT:    vsub.vx v12, v12, a0
1412; RV32D-NEXT:    vmseq.vi v0, v8, 0
1413; RV32D-NEXT:    li a0, 32
1414; RV32D-NEXT:    vmerge.vxm v8, v12, a0, v0
1415; RV32D-NEXT:    ret
1416;
1417; RV64D-LABEL: cttz_nxv8i32:
1418; RV64D:       # %bb.0:
1419; RV64D-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1420; RV64D-NEXT:    vmv.v.i v12, 0
1421; RV64D-NEXT:    vmseq.vv v0, v12, v8
1422; RV64D-NEXT:    vrsub.vi v12, v8, 0
1423; RV64D-NEXT:    vand.vv v8, v8, v12
1424; RV64D-NEXT:    vfwcvt.f.xu.v v16, v8
1425; RV64D-NEXT:    li a0, 52
1426; RV64D-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
1427; RV64D-NEXT:    vsrl.vx v8, v16, a0
1428; RV64D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
1429; RV64D-NEXT:    vnsrl.wi v16, v8, 0
1430; RV64D-NEXT:    li a0, 1023
1431; RV64D-NEXT:    vsub.vx v8, v16, a0
1432; RV64D-NEXT:    li a0, 32
1433; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
1434; RV64D-NEXT:    ret
1435  %a = call <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 false)
1436  ret <vscale x 8 x i32> %a
1437}
1438declare <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32>, i1)
1439
1440define <vscale x 16 x i32> @cttz_nxv16i32(<vscale x 16 x i32> %va) {
1441; RV32-LABEL: cttz_nxv16i32:
1442; RV32:       # %bb.0:
1443; RV32-NEXT:    li a0, 1
1444; RV32-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
1445; RV32-NEXT:    vsub.vx v16, v8, a0
1446; RV32-NEXT:    vxor.vi v8, v8, -1
1447; RV32-NEXT:    vand.vv v8, v8, v16
1448; RV32-NEXT:    vsrl.vi v16, v8, 1
1449; RV32-NEXT:    lui a0, 349525
1450; RV32-NEXT:    addi a0, a0, 1365
1451; RV32-NEXT:    vand.vx v16, v16, a0
1452; RV32-NEXT:    vsub.vv v8, v8, v16
1453; RV32-NEXT:    lui a0, 209715
1454; RV32-NEXT:    addi a0, a0, 819
1455; RV32-NEXT:    vand.vx v16, v8, a0
1456; RV32-NEXT:    vsrl.vi v8, v8, 2
1457; RV32-NEXT:    vand.vx v8, v8, a0
1458; RV32-NEXT:    vadd.vv v8, v16, v8
1459; RV32-NEXT:    vsrl.vi v16, v8, 4
1460; RV32-NEXT:    vadd.vv v8, v8, v16
1461; RV32-NEXT:    lui a0, 61681
1462; RV32-NEXT:    addi a0, a0, -241
1463; RV32-NEXT:    vand.vx v8, v8, a0
1464; RV32-NEXT:    lui a0, 4112
1465; RV32-NEXT:    addi a0, a0, 257
1466; RV32-NEXT:    vmul.vx v8, v8, a0
1467; RV32-NEXT:    vsrl.vi v8, v8, 24
1468; RV32-NEXT:    ret
1469;
1470; RV64-LABEL: cttz_nxv16i32:
1471; RV64:       # %bb.0:
1472; RV64-NEXT:    li a0, 1
1473; RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
1474; RV64-NEXT:    vsub.vx v16, v8, a0
1475; RV64-NEXT:    vxor.vi v8, v8, -1
1476; RV64-NEXT:    vand.vv v8, v8, v16
1477; RV64-NEXT:    vsrl.vi v16, v8, 1
1478; RV64-NEXT:    lui a0, 349525
1479; RV64-NEXT:    addiw a0, a0, 1365
1480; RV64-NEXT:    vand.vx v16, v16, a0
1481; RV64-NEXT:    vsub.vv v8, v8, v16
1482; RV64-NEXT:    lui a0, 209715
1483; RV64-NEXT:    addiw a0, a0, 819
1484; RV64-NEXT:    vand.vx v16, v8, a0
1485; RV64-NEXT:    vsrl.vi v8, v8, 2
1486; RV64-NEXT:    vand.vx v8, v8, a0
1487; RV64-NEXT:    vadd.vv v8, v16, v8
1488; RV64-NEXT:    vsrl.vi v16, v8, 4
1489; RV64-NEXT:    vadd.vv v8, v8, v16
1490; RV64-NEXT:    lui a0, 61681
1491; RV64-NEXT:    addiw a0, a0, -241
1492; RV64-NEXT:    vand.vx v8, v8, a0
1493; RV64-NEXT:    lui a0, 4112
1494; RV64-NEXT:    addiw a0, a0, 257
1495; RV64-NEXT:    vmul.vx v8, v8, a0
1496; RV64-NEXT:    vsrl.vi v8, v8, 24
1497; RV64-NEXT:    ret
1498  %a = call <vscale x 16 x i32> @llvm.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 false)
1499  ret <vscale x 16 x i32> %a
1500}
1501declare <vscale x 16 x i32> @llvm.cttz.nxv16i32(<vscale x 16 x i32>, i1)
1502
1503define <vscale x 1 x i64> @cttz_nxv1i64(<vscale x 1 x i64> %va) {
1504; RV32-LABEL: cttz_nxv1i64:
1505; RV32:       # %bb.0:
1506; RV32-NEXT:    addi sp, sp, -16
1507; RV32-NEXT:    .cfi_def_cfa_offset 16
1508; RV32-NEXT:    lui a0, 349525
1509; RV32-NEXT:    addi a0, a0, 1365
1510; RV32-NEXT:    sw a0, 12(sp)
1511; RV32-NEXT:    sw a0, 8(sp)
1512; RV32-NEXT:    lui a0, 209715
1513; RV32-NEXT:    addi a0, a0, 819
1514; RV32-NEXT:    sw a0, 12(sp)
1515; RV32-NEXT:    sw a0, 8(sp)
1516; RV32-NEXT:    lui a0, 61681
1517; RV32-NEXT:    addi a0, a0, -241
1518; RV32-NEXT:    sw a0, 12(sp)
1519; RV32-NEXT:    sw a0, 8(sp)
1520; RV32-NEXT:    lui a0, 4112
1521; RV32-NEXT:    addi a0, a0, 257
1522; RV32-NEXT:    sw a0, 12(sp)
1523; RV32-NEXT:    sw a0, 8(sp)
1524; RV32-NEXT:    li a0, 1
1525; RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
1526; RV32-NEXT:    vsub.vx v9, v8, a0
1527; RV32-NEXT:    vxor.vi v8, v8, -1
1528; RV32-NEXT:    addi a0, sp, 8
1529; RV32-NEXT:    vlse64.v v10, (a0), zero
1530; RV32-NEXT:    vand.vv v8, v8, v9
1531; RV32-NEXT:    addi a0, sp, 8
1532; RV32-NEXT:    vlse64.v v9, (a0), zero
1533; RV32-NEXT:    vsrl.vi v11, v8, 1
1534; RV32-NEXT:    vand.vv v10, v11, v10
1535; RV32-NEXT:    vsub.vv v8, v8, v10
1536; RV32-NEXT:    vand.vv v10, v8, v9
1537; RV32-NEXT:    vsrl.vi v8, v8, 2
1538; RV32-NEXT:    vand.vv v8, v8, v9
1539; RV32-NEXT:    vadd.vv v8, v10, v8
1540; RV32-NEXT:    addi a0, sp, 8
1541; RV32-NEXT:    vlse64.v v9, (a0), zero
1542; RV32-NEXT:    addi a0, sp, 8
1543; RV32-NEXT:    vlse64.v v10, (a0), zero
1544; RV32-NEXT:    vsrl.vi v11, v8, 4
1545; RV32-NEXT:    vadd.vv v8, v8, v11
1546; RV32-NEXT:    vand.vv v8, v8, v9
1547; RV32-NEXT:    vmul.vv v8, v8, v10
1548; RV32-NEXT:    li a0, 56
1549; RV32-NEXT:    vsrl.vx v8, v8, a0
1550; RV32-NEXT:    addi sp, sp, 16
1551; RV32-NEXT:    ret
1552;
1553; RV64-LABEL: cttz_nxv1i64:
1554; RV64:       # %bb.0:
1555; RV64-NEXT:    li a0, 1
1556; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
1557; RV64-NEXT:    vsub.vx v9, v8, a0
1558; RV64-NEXT:    vxor.vi v8, v8, -1
1559; RV64-NEXT:    vand.vv v8, v8, v9
1560; RV64-NEXT:    lui a0, %hi(.LCPI18_0)
1561; RV64-NEXT:    ld a0, %lo(.LCPI18_0)(a0)
1562; RV64-NEXT:    lui a1, %hi(.LCPI18_1)
1563; RV64-NEXT:    ld a1, %lo(.LCPI18_1)(a1)
1564; RV64-NEXT:    vsrl.vi v9, v8, 1
1565; RV64-NEXT:    vand.vx v9, v9, a0
1566; RV64-NEXT:    vsub.vv v8, v8, v9
1567; RV64-NEXT:    vand.vx v9, v8, a1
1568; RV64-NEXT:    vsrl.vi v8, v8, 2
1569; RV64-NEXT:    vand.vx v8, v8, a1
1570; RV64-NEXT:    vadd.vv v8, v9, v8
1571; RV64-NEXT:    lui a0, %hi(.LCPI18_2)
1572; RV64-NEXT:    ld a0, %lo(.LCPI18_2)(a0)
1573; RV64-NEXT:    lui a1, %hi(.LCPI18_3)
1574; RV64-NEXT:    ld a1, %lo(.LCPI18_3)(a1)
1575; RV64-NEXT:    vsrl.vi v9, v8, 4
1576; RV64-NEXT:    vadd.vv v8, v8, v9
1577; RV64-NEXT:    vand.vx v8, v8, a0
1578; RV64-NEXT:    vmul.vx v8, v8, a1
1579; RV64-NEXT:    li a0, 56
1580; RV64-NEXT:    vsrl.vx v8, v8, a0
1581; RV64-NEXT:    ret
1582  %a = call <vscale x 1 x i64> @llvm.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 false)
1583  ret <vscale x 1 x i64> %a
1584}
1585declare <vscale x 1 x i64> @llvm.cttz.nxv1i64(<vscale x 1 x i64>, i1)
1586
1587define <vscale x 2 x i64> @cttz_nxv2i64(<vscale x 2 x i64> %va) {
1588; RV32-LABEL: cttz_nxv2i64:
1589; RV32:       # %bb.0:
1590; RV32-NEXT:    addi sp, sp, -16
1591; RV32-NEXT:    .cfi_def_cfa_offset 16
1592; RV32-NEXT:    lui a0, 349525
1593; RV32-NEXT:    addi a0, a0, 1365
1594; RV32-NEXT:    sw a0, 12(sp)
1595; RV32-NEXT:    sw a0, 8(sp)
1596; RV32-NEXT:    lui a0, 209715
1597; RV32-NEXT:    addi a0, a0, 819
1598; RV32-NEXT:    sw a0, 12(sp)
1599; RV32-NEXT:    sw a0, 8(sp)
1600; RV32-NEXT:    lui a0, 61681
1601; RV32-NEXT:    addi a0, a0, -241
1602; RV32-NEXT:    sw a0, 12(sp)
1603; RV32-NEXT:    sw a0, 8(sp)
1604; RV32-NEXT:    lui a0, 4112
1605; RV32-NEXT:    addi a0, a0, 257
1606; RV32-NEXT:    sw a0, 12(sp)
1607; RV32-NEXT:    sw a0, 8(sp)
1608; RV32-NEXT:    li a0, 1
1609; RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
1610; RV32-NEXT:    vsub.vx v10, v8, a0
1611; RV32-NEXT:    vxor.vi v8, v8, -1
1612; RV32-NEXT:    addi a0, sp, 8
1613; RV32-NEXT:    vlse64.v v12, (a0), zero
1614; RV32-NEXT:    vand.vv v8, v8, v10
1615; RV32-NEXT:    addi a0, sp, 8
1616; RV32-NEXT:    vlse64.v v10, (a0), zero
1617; RV32-NEXT:    vsrl.vi v14, v8, 1
1618; RV32-NEXT:    vand.vv v12, v14, v12
1619; RV32-NEXT:    vsub.vv v8, v8, v12
1620; RV32-NEXT:    vand.vv v12, v8, v10
1621; RV32-NEXT:    vsrl.vi v8, v8, 2
1622; RV32-NEXT:    vand.vv v8, v8, v10
1623; RV32-NEXT:    vadd.vv v8, v12, v8
1624; RV32-NEXT:    addi a0, sp, 8
1625; RV32-NEXT:    vlse64.v v10, (a0), zero
1626; RV32-NEXT:    addi a0, sp, 8
1627; RV32-NEXT:    vlse64.v v12, (a0), zero
1628; RV32-NEXT:    vsrl.vi v14, v8, 4
1629; RV32-NEXT:    vadd.vv v8, v8, v14
1630; RV32-NEXT:    vand.vv v8, v8, v10
1631; RV32-NEXT:    vmul.vv v8, v8, v12
1632; RV32-NEXT:    li a0, 56
1633; RV32-NEXT:    vsrl.vx v8, v8, a0
1634; RV32-NEXT:    addi sp, sp, 16
1635; RV32-NEXT:    ret
1636;
1637; RV64-LABEL: cttz_nxv2i64:
1638; RV64:       # %bb.0:
1639; RV64-NEXT:    li a0, 1
1640; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
1641; RV64-NEXT:    vsub.vx v10, v8, a0
1642; RV64-NEXT:    vxor.vi v8, v8, -1
1643; RV64-NEXT:    vand.vv v8, v8, v10
1644; RV64-NEXT:    lui a0, %hi(.LCPI19_0)
1645; RV64-NEXT:    ld a0, %lo(.LCPI19_0)(a0)
1646; RV64-NEXT:    lui a1, %hi(.LCPI19_1)
1647; RV64-NEXT:    ld a1, %lo(.LCPI19_1)(a1)
1648; RV64-NEXT:    vsrl.vi v10, v8, 1
1649; RV64-NEXT:    vand.vx v10, v10, a0
1650; RV64-NEXT:    vsub.vv v8, v8, v10
1651; RV64-NEXT:    vand.vx v10, v8, a1
1652; RV64-NEXT:    vsrl.vi v8, v8, 2
1653; RV64-NEXT:    vand.vx v8, v8, a1
1654; RV64-NEXT:    vadd.vv v8, v10, v8
1655; RV64-NEXT:    lui a0, %hi(.LCPI19_2)
1656; RV64-NEXT:    ld a0, %lo(.LCPI19_2)(a0)
1657; RV64-NEXT:    lui a1, %hi(.LCPI19_3)
1658; RV64-NEXT:    ld a1, %lo(.LCPI19_3)(a1)
1659; RV64-NEXT:    vsrl.vi v10, v8, 4
1660; RV64-NEXT:    vadd.vv v8, v8, v10
1661; RV64-NEXT:    vand.vx v8, v8, a0
1662; RV64-NEXT:    vmul.vx v8, v8, a1
1663; RV64-NEXT:    li a0, 56
1664; RV64-NEXT:    vsrl.vx v8, v8, a0
1665; RV64-NEXT:    ret
1666  %a = call <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 false)
1667  ret <vscale x 2 x i64> %a
1668}
1669declare <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64>, i1)
1670
1671define <vscale x 4 x i64> @cttz_nxv4i64(<vscale x 4 x i64> %va) {
1672; RV32-LABEL: cttz_nxv4i64:
1673; RV32:       # %bb.0:
1674; RV32-NEXT:    addi sp, sp, -16
1675; RV32-NEXT:    .cfi_def_cfa_offset 16
1676; RV32-NEXT:    lui a0, 349525
1677; RV32-NEXT:    addi a0, a0, 1365
1678; RV32-NEXT:    sw a0, 12(sp)
1679; RV32-NEXT:    sw a0, 8(sp)
1680; RV32-NEXT:    lui a0, 209715
1681; RV32-NEXT:    addi a0, a0, 819
1682; RV32-NEXT:    sw a0, 12(sp)
1683; RV32-NEXT:    sw a0, 8(sp)
1684; RV32-NEXT:    lui a0, 61681
1685; RV32-NEXT:    addi a0, a0, -241
1686; RV32-NEXT:    sw a0, 12(sp)
1687; RV32-NEXT:    sw a0, 8(sp)
1688; RV32-NEXT:    lui a0, 4112
1689; RV32-NEXT:    addi a0, a0, 257
1690; RV32-NEXT:    sw a0, 12(sp)
1691; RV32-NEXT:    sw a0, 8(sp)
1692; RV32-NEXT:    li a0, 1
1693; RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1694; RV32-NEXT:    vsub.vx v12, v8, a0
1695; RV32-NEXT:    vxor.vi v8, v8, -1
1696; RV32-NEXT:    addi a0, sp, 8
1697; RV32-NEXT:    vlse64.v v16, (a0), zero
1698; RV32-NEXT:    vand.vv v8, v8, v12
1699; RV32-NEXT:    addi a0, sp, 8
1700; RV32-NEXT:    vlse64.v v12, (a0), zero
1701; RV32-NEXT:    vsrl.vi v20, v8, 1
1702; RV32-NEXT:    vand.vv v16, v20, v16
1703; RV32-NEXT:    vsub.vv v8, v8, v16
1704; RV32-NEXT:    vand.vv v16, v8, v12
1705; RV32-NEXT:    vsrl.vi v8, v8, 2
1706; RV32-NEXT:    vand.vv v8, v8, v12
1707; RV32-NEXT:    vadd.vv v8, v16, v8
1708; RV32-NEXT:    addi a0, sp, 8
1709; RV32-NEXT:    vlse64.v v12, (a0), zero
1710; RV32-NEXT:    addi a0, sp, 8
1711; RV32-NEXT:    vlse64.v v16, (a0), zero
1712; RV32-NEXT:    vsrl.vi v20, v8, 4
1713; RV32-NEXT:    vadd.vv v8, v8, v20
1714; RV32-NEXT:    vand.vv v8, v8, v12
1715; RV32-NEXT:    vmul.vv v8, v8, v16
1716; RV32-NEXT:    li a0, 56
1717; RV32-NEXT:    vsrl.vx v8, v8, a0
1718; RV32-NEXT:    addi sp, sp, 16
1719; RV32-NEXT:    ret
1720;
1721; RV64-LABEL: cttz_nxv4i64:
1722; RV64:       # %bb.0:
1723; RV64-NEXT:    li a0, 1
1724; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1725; RV64-NEXT:    vsub.vx v12, v8, a0
1726; RV64-NEXT:    vxor.vi v8, v8, -1
1727; RV64-NEXT:    vand.vv v8, v8, v12
1728; RV64-NEXT:    lui a0, %hi(.LCPI20_0)
1729; RV64-NEXT:    ld a0, %lo(.LCPI20_0)(a0)
1730; RV64-NEXT:    lui a1, %hi(.LCPI20_1)
1731; RV64-NEXT:    ld a1, %lo(.LCPI20_1)(a1)
1732; RV64-NEXT:    vsrl.vi v12, v8, 1
1733; RV64-NEXT:    vand.vx v12, v12, a0
1734; RV64-NEXT:    vsub.vv v8, v8, v12
1735; RV64-NEXT:    vand.vx v12, v8, a1
1736; RV64-NEXT:    vsrl.vi v8, v8, 2
1737; RV64-NEXT:    vand.vx v8, v8, a1
1738; RV64-NEXT:    vadd.vv v8, v12, v8
1739; RV64-NEXT:    lui a0, %hi(.LCPI20_2)
1740; RV64-NEXT:    ld a0, %lo(.LCPI20_2)(a0)
1741; RV64-NEXT:    lui a1, %hi(.LCPI20_3)
1742; RV64-NEXT:    ld a1, %lo(.LCPI20_3)(a1)
1743; RV64-NEXT:    vsrl.vi v12, v8, 4
1744; RV64-NEXT:    vadd.vv v8, v8, v12
1745; RV64-NEXT:    vand.vx v8, v8, a0
1746; RV64-NEXT:    vmul.vx v8, v8, a1
1747; RV64-NEXT:    li a0, 56
1748; RV64-NEXT:    vsrl.vx v8, v8, a0
1749; RV64-NEXT:    ret
1750  %a = call <vscale x 4 x i64> @llvm.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 false)
1751  ret <vscale x 4 x i64> %a
1752}
1753declare <vscale x 4 x i64> @llvm.cttz.nxv4i64(<vscale x 4 x i64>, i1)
1754
1755define <vscale x 8 x i64> @cttz_nxv8i64(<vscale x 8 x i64> %va) {
1756; RV32-LABEL: cttz_nxv8i64:
1757; RV32:       # %bb.0:
1758; RV32-NEXT:    addi sp, sp, -16
1759; RV32-NEXT:    .cfi_def_cfa_offset 16
1760; RV32-NEXT:    lui a0, 349525
1761; RV32-NEXT:    addi a0, a0, 1365
1762; RV32-NEXT:    sw a0, 12(sp)
1763; RV32-NEXT:    sw a0, 8(sp)
1764; RV32-NEXT:    lui a0, 209715
1765; RV32-NEXT:    addi a0, a0, 819
1766; RV32-NEXT:    sw a0, 12(sp)
1767; RV32-NEXT:    sw a0, 8(sp)
1768; RV32-NEXT:    lui a0, 61681
1769; RV32-NEXT:    addi a0, a0, -241
1770; RV32-NEXT:    sw a0, 12(sp)
1771; RV32-NEXT:    sw a0, 8(sp)
1772; RV32-NEXT:    lui a0, 4112
1773; RV32-NEXT:    addi a0, a0, 257
1774; RV32-NEXT:    sw a0, 12(sp)
1775; RV32-NEXT:    sw a0, 8(sp)
1776; RV32-NEXT:    li a0, 1
1777; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1778; RV32-NEXT:    vsub.vx v16, v8, a0
1779; RV32-NEXT:    vxor.vi v8, v8, -1
1780; RV32-NEXT:    addi a0, sp, 8
1781; RV32-NEXT:    vlse64.v v24, (a0), zero
1782; RV32-NEXT:    vand.vv v8, v8, v16
1783; RV32-NEXT:    addi a0, sp, 8
1784; RV32-NEXT:    vlse64.v v16, (a0), zero
1785; RV32-NEXT:    vsrl.vi v0, v8, 1
1786; RV32-NEXT:    vand.vv v24, v0, v24
1787; RV32-NEXT:    vsub.vv v8, v8, v24
1788; RV32-NEXT:    vand.vv v24, v8, v16
1789; RV32-NEXT:    vsrl.vi v8, v8, 2
1790; RV32-NEXT:    vand.vv v8, v8, v16
1791; RV32-NEXT:    vadd.vv v8, v24, v8
1792; RV32-NEXT:    addi a0, sp, 8
1793; RV32-NEXT:    vlse64.v v16, (a0), zero
1794; RV32-NEXT:    addi a0, sp, 8
1795; RV32-NEXT:    vlse64.v v24, (a0), zero
1796; RV32-NEXT:    vsrl.vi v0, v8, 4
1797; RV32-NEXT:    vadd.vv v8, v8, v0
1798; RV32-NEXT:    vand.vv v8, v8, v16
1799; RV32-NEXT:    vmul.vv v8, v8, v24
1800; RV32-NEXT:    li a0, 56
1801; RV32-NEXT:    vsrl.vx v8, v8, a0
1802; RV32-NEXT:    addi sp, sp, 16
1803; RV32-NEXT:    ret
1804;
1805; RV64-LABEL: cttz_nxv8i64:
1806; RV64:       # %bb.0:
1807; RV64-NEXT:    li a0, 1
1808; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1809; RV64-NEXT:    vsub.vx v16, v8, a0
1810; RV64-NEXT:    vxor.vi v8, v8, -1
1811; RV64-NEXT:    vand.vv v8, v8, v16
1812; RV64-NEXT:    lui a0, %hi(.LCPI21_0)
1813; RV64-NEXT:    ld a0, %lo(.LCPI21_0)(a0)
1814; RV64-NEXT:    lui a1, %hi(.LCPI21_1)
1815; RV64-NEXT:    ld a1, %lo(.LCPI21_1)(a1)
1816; RV64-NEXT:    vsrl.vi v16, v8, 1
1817; RV64-NEXT:    vand.vx v16, v16, a0
1818; RV64-NEXT:    vsub.vv v8, v8, v16
1819; RV64-NEXT:    vand.vx v16, v8, a1
1820; RV64-NEXT:    vsrl.vi v8, v8, 2
1821; RV64-NEXT:    vand.vx v8, v8, a1
1822; RV64-NEXT:    vadd.vv v8, v16, v8
1823; RV64-NEXT:    lui a0, %hi(.LCPI21_2)
1824; RV64-NEXT:    ld a0, %lo(.LCPI21_2)(a0)
1825; RV64-NEXT:    lui a1, %hi(.LCPI21_3)
1826; RV64-NEXT:    ld a1, %lo(.LCPI21_3)(a1)
1827; RV64-NEXT:    vsrl.vi v16, v8, 4
1828; RV64-NEXT:    vadd.vv v8, v8, v16
1829; RV64-NEXT:    vand.vx v8, v8, a0
1830; RV64-NEXT:    vmul.vx v8, v8, a1
1831; RV64-NEXT:    li a0, 56
1832; RV64-NEXT:    vsrl.vx v8, v8, a0
1833; RV64-NEXT:    ret
1834  %a = call <vscale x 8 x i64> @llvm.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 false)
1835  ret <vscale x 8 x i64> %a
1836}
1837declare <vscale x 8 x i64> @llvm.cttz.nxv8i64(<vscale x 8 x i64>, i1)
1838
1839define <vscale x 1 x i8> @cttz_zero_undef_nxv1i8(<vscale x 1 x i8> %va) {
1840; RV32I-LABEL: cttz_zero_undef_nxv1i8:
1841; RV32I:       # %bb.0:
1842; RV32I-NEXT:    li a0, 1
1843; RV32I-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
1844; RV32I-NEXT:    vsub.vx v9, v8, a0
1845; RV32I-NEXT:    vxor.vi v8, v8, -1
1846; RV32I-NEXT:    vand.vv v8, v8, v9
1847; RV32I-NEXT:    vsrl.vi v9, v8, 1
1848; RV32I-NEXT:    li a0, 85
1849; RV32I-NEXT:    vand.vx v9, v9, a0
1850; RV32I-NEXT:    vsub.vv v8, v8, v9
1851; RV32I-NEXT:    li a0, 51
1852; RV32I-NEXT:    vand.vx v9, v8, a0
1853; RV32I-NEXT:    vsrl.vi v8, v8, 2
1854; RV32I-NEXT:    vand.vx v8, v8, a0
1855; RV32I-NEXT:    vadd.vv v8, v9, v8
1856; RV32I-NEXT:    vsrl.vi v9, v8, 4
1857; RV32I-NEXT:    vadd.vv v8, v8, v9
1858; RV32I-NEXT:    vand.vi v8, v8, 15
1859; RV32I-NEXT:    ret
1860;
1861; RV64I-LABEL: cttz_zero_undef_nxv1i8:
1862; RV64I:       # %bb.0:
1863; RV64I-NEXT:    li a0, 1
1864; RV64I-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
1865; RV64I-NEXT:    vsub.vx v9, v8, a0
1866; RV64I-NEXT:    vxor.vi v8, v8, -1
1867; RV64I-NEXT:    vand.vv v8, v8, v9
1868; RV64I-NEXT:    vsrl.vi v9, v8, 1
1869; RV64I-NEXT:    li a0, 85
1870; RV64I-NEXT:    vand.vx v9, v9, a0
1871; RV64I-NEXT:    vsub.vv v8, v8, v9
1872; RV64I-NEXT:    li a0, 51
1873; RV64I-NEXT:    vand.vx v9, v8, a0
1874; RV64I-NEXT:    vsrl.vi v8, v8, 2
1875; RV64I-NEXT:    vand.vx v8, v8, a0
1876; RV64I-NEXT:    vadd.vv v8, v9, v8
1877; RV64I-NEXT:    vsrl.vi v9, v8, 4
1878; RV64I-NEXT:    vadd.vv v8, v8, v9
1879; RV64I-NEXT:    vand.vi v8, v8, 15
1880; RV64I-NEXT:    ret
1881;
1882; RV32D-LABEL: cttz_zero_undef_nxv1i8:
1883; RV32D:       # %bb.0:
1884; RV32D-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
1885; RV32D-NEXT:    vrsub.vi v9, v8, 0
1886; RV32D-NEXT:    vand.vv v8, v8, v9
1887; RV32D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
1888; RV32D-NEXT:    vzext.vf4 v9, v8
1889; RV32D-NEXT:    vfcvt.f.xu.v v8, v9
1890; RV32D-NEXT:    vsrl.vi v8, v8, 23
1891; RV32D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
1892; RV32D-NEXT:    vnsrl.wi v8, v8, 0
1893; RV32D-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
1894; RV32D-NEXT:    vnsrl.wi v8, v8, 0
1895; RV32D-NEXT:    li a0, 127
1896; RV32D-NEXT:    vsub.vx v8, v8, a0
1897; RV32D-NEXT:    ret
1898;
1899; RV64D-LABEL: cttz_zero_undef_nxv1i8:
1900; RV64D:       # %bb.0:
1901; RV64D-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
1902; RV64D-NEXT:    vrsub.vi v9, v8, 0
1903; RV64D-NEXT:    vand.vv v8, v8, v9
1904; RV64D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
1905; RV64D-NEXT:    vzext.vf4 v9, v8
1906; RV64D-NEXT:    vfcvt.f.xu.v v8, v9
1907; RV64D-NEXT:    vsrl.vi v8, v8, 23
1908; RV64D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
1909; RV64D-NEXT:    vnsrl.wi v8, v8, 0
1910; RV64D-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
1911; RV64D-NEXT:    vnsrl.wi v8, v8, 0
1912; RV64D-NEXT:    li a0, 127
1913; RV64D-NEXT:    vsub.vx v8, v8, a0
1914; RV64D-NEXT:    ret
1915  %a = call <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 true)
1916  ret <vscale x 1 x i8> %a
1917}
1918
1919define <vscale x 2 x i8> @cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va) {
1920; RV32I-LABEL: cttz_zero_undef_nxv2i8:
1921; RV32I:       # %bb.0:
1922; RV32I-NEXT:    li a0, 1
1923; RV32I-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
1924; RV32I-NEXT:    vsub.vx v9, v8, a0
1925; RV32I-NEXT:    vxor.vi v8, v8, -1
1926; RV32I-NEXT:    vand.vv v8, v8, v9
1927; RV32I-NEXT:    vsrl.vi v9, v8, 1
1928; RV32I-NEXT:    li a0, 85
1929; RV32I-NEXT:    vand.vx v9, v9, a0
1930; RV32I-NEXT:    vsub.vv v8, v8, v9
1931; RV32I-NEXT:    li a0, 51
1932; RV32I-NEXT:    vand.vx v9, v8, a0
1933; RV32I-NEXT:    vsrl.vi v8, v8, 2
1934; RV32I-NEXT:    vand.vx v8, v8, a0
1935; RV32I-NEXT:    vadd.vv v8, v9, v8
1936; RV32I-NEXT:    vsrl.vi v9, v8, 4
1937; RV32I-NEXT:    vadd.vv v8, v8, v9
1938; RV32I-NEXT:    vand.vi v8, v8, 15
1939; RV32I-NEXT:    ret
1940;
1941; RV64I-LABEL: cttz_zero_undef_nxv2i8:
1942; RV64I:       # %bb.0:
1943; RV64I-NEXT:    li a0, 1
1944; RV64I-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
1945; RV64I-NEXT:    vsub.vx v9, v8, a0
1946; RV64I-NEXT:    vxor.vi v8, v8, -1
1947; RV64I-NEXT:    vand.vv v8, v8, v9
1948; RV64I-NEXT:    vsrl.vi v9, v8, 1
1949; RV64I-NEXT:    li a0, 85
1950; RV64I-NEXT:    vand.vx v9, v9, a0
1951; RV64I-NEXT:    vsub.vv v8, v8, v9
1952; RV64I-NEXT:    li a0, 51
1953; RV64I-NEXT:    vand.vx v9, v8, a0
1954; RV64I-NEXT:    vsrl.vi v8, v8, 2
1955; RV64I-NEXT:    vand.vx v8, v8, a0
1956; RV64I-NEXT:    vadd.vv v8, v9, v8
1957; RV64I-NEXT:    vsrl.vi v9, v8, 4
1958; RV64I-NEXT:    vadd.vv v8, v8, v9
1959; RV64I-NEXT:    vand.vi v8, v8, 15
1960; RV64I-NEXT:    ret
1961;
1962; RV32D-LABEL: cttz_zero_undef_nxv2i8:
1963; RV32D:       # %bb.0:
1964; RV32D-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
1965; RV32D-NEXT:    vrsub.vi v9, v8, 0
1966; RV32D-NEXT:    vand.vv v8, v8, v9
1967; RV32D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
1968; RV32D-NEXT:    vzext.vf4 v9, v8
1969; RV32D-NEXT:    vfcvt.f.xu.v v8, v9
1970; RV32D-NEXT:    vsrl.vi v8, v8, 23
1971; RV32D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
1972; RV32D-NEXT:    vnsrl.wi v8, v8, 0
1973; RV32D-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
1974; RV32D-NEXT:    vnsrl.wi v8, v8, 0
1975; RV32D-NEXT:    li a0, 127
1976; RV32D-NEXT:    vsub.vx v8, v8, a0
1977; RV32D-NEXT:    ret
1978;
1979; RV64D-LABEL: cttz_zero_undef_nxv2i8:
1980; RV64D:       # %bb.0:
1981; RV64D-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
1982; RV64D-NEXT:    vrsub.vi v9, v8, 0
1983; RV64D-NEXT:    vand.vv v8, v8, v9
1984; RV64D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
1985; RV64D-NEXT:    vzext.vf4 v9, v8
1986; RV64D-NEXT:    vfcvt.f.xu.v v8, v9
1987; RV64D-NEXT:    vsrl.vi v8, v8, 23
1988; RV64D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
1989; RV64D-NEXT:    vnsrl.wi v8, v8, 0
1990; RV64D-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
1991; RV64D-NEXT:    vnsrl.wi v8, v8, 0
1992; RV64D-NEXT:    li a0, 127
1993; RV64D-NEXT:    vsub.vx v8, v8, a0
1994; RV64D-NEXT:    ret
1995  %a = call <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 true)
1996  ret <vscale x 2 x i8> %a
1997}
1998
1999define <vscale x 4 x i8> @cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va) {
2000; RV32I-LABEL: cttz_zero_undef_nxv4i8:
2001; RV32I:       # %bb.0:
2002; RV32I-NEXT:    li a0, 1
2003; RV32I-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
2004; RV32I-NEXT:    vsub.vx v9, v8, a0
2005; RV32I-NEXT:    vxor.vi v8, v8, -1
2006; RV32I-NEXT:    vand.vv v8, v8, v9
2007; RV32I-NEXT:    vsrl.vi v9, v8, 1
2008; RV32I-NEXT:    li a0, 85
2009; RV32I-NEXT:    vand.vx v9, v9, a0
2010; RV32I-NEXT:    vsub.vv v8, v8, v9
2011; RV32I-NEXT:    li a0, 51
2012; RV32I-NEXT:    vand.vx v9, v8, a0
2013; RV32I-NEXT:    vsrl.vi v8, v8, 2
2014; RV32I-NEXT:    vand.vx v8, v8, a0
2015; RV32I-NEXT:    vadd.vv v8, v9, v8
2016; RV32I-NEXT:    vsrl.vi v9, v8, 4
2017; RV32I-NEXT:    vadd.vv v8, v8, v9
2018; RV32I-NEXT:    vand.vi v8, v8, 15
2019; RV32I-NEXT:    ret
2020;
2021; RV64I-LABEL: cttz_zero_undef_nxv4i8:
2022; RV64I:       # %bb.0:
2023; RV64I-NEXT:    li a0, 1
2024; RV64I-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
2025; RV64I-NEXT:    vsub.vx v9, v8, a0
2026; RV64I-NEXT:    vxor.vi v8, v8, -1
2027; RV64I-NEXT:    vand.vv v8, v8, v9
2028; RV64I-NEXT:    vsrl.vi v9, v8, 1
2029; RV64I-NEXT:    li a0, 85
2030; RV64I-NEXT:    vand.vx v9, v9, a0
2031; RV64I-NEXT:    vsub.vv v8, v8, v9
2032; RV64I-NEXT:    li a0, 51
2033; RV64I-NEXT:    vand.vx v9, v8, a0
2034; RV64I-NEXT:    vsrl.vi v8, v8, 2
2035; RV64I-NEXT:    vand.vx v8, v8, a0
2036; RV64I-NEXT:    vadd.vv v8, v9, v8
2037; RV64I-NEXT:    vsrl.vi v9, v8, 4
2038; RV64I-NEXT:    vadd.vv v8, v8, v9
2039; RV64I-NEXT:    vand.vi v8, v8, 15
2040; RV64I-NEXT:    ret
2041;
2042; RV32D-LABEL: cttz_zero_undef_nxv4i8:
2043; RV32D:       # %bb.0:
2044; RV32D-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
2045; RV32D-NEXT:    vrsub.vi v9, v8, 0
2046; RV32D-NEXT:    vand.vv v8, v8, v9
2047; RV32D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
2048; RV32D-NEXT:    vzext.vf4 v10, v8
2049; RV32D-NEXT:    vfcvt.f.xu.v v8, v10
2050; RV32D-NEXT:    vsrl.vi v8, v8, 23
2051; RV32D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
2052; RV32D-NEXT:    vnsrl.wi v10, v8, 0
2053; RV32D-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
2054; RV32D-NEXT:    vnsrl.wi v8, v10, 0
2055; RV32D-NEXT:    li a0, 127
2056; RV32D-NEXT:    vsub.vx v8, v8, a0
2057; RV32D-NEXT:    ret
2058;
2059; RV64D-LABEL: cttz_zero_undef_nxv4i8:
2060; RV64D:       # %bb.0:
2061; RV64D-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
2062; RV64D-NEXT:    vrsub.vi v9, v8, 0
2063; RV64D-NEXT:    vand.vv v8, v8, v9
2064; RV64D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
2065; RV64D-NEXT:    vzext.vf4 v10, v8
2066; RV64D-NEXT:    vfcvt.f.xu.v v8, v10
2067; RV64D-NEXT:    vsrl.vi v8, v8, 23
2068; RV64D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
2069; RV64D-NEXT:    vnsrl.wi v10, v8, 0
2070; RV64D-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
2071; RV64D-NEXT:    vnsrl.wi v8, v10, 0
2072; RV64D-NEXT:    li a0, 127
2073; RV64D-NEXT:    vsub.vx v8, v8, a0
2074; RV64D-NEXT:    ret
2075  %a = call <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 true)
2076  ret <vscale x 4 x i8> %a
2077}
2078
2079define <vscale x 8 x i8> @cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va) {
2080; RV32I-LABEL: cttz_zero_undef_nxv8i8:
2081; RV32I:       # %bb.0:
2082; RV32I-NEXT:    li a0, 1
2083; RV32I-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
2084; RV32I-NEXT:    vsub.vx v9, v8, a0
2085; RV32I-NEXT:    vxor.vi v8, v8, -1
2086; RV32I-NEXT:    vand.vv v8, v8, v9
2087; RV32I-NEXT:    vsrl.vi v9, v8, 1
2088; RV32I-NEXT:    li a0, 85
2089; RV32I-NEXT:    vand.vx v9, v9, a0
2090; RV32I-NEXT:    vsub.vv v8, v8, v9
2091; RV32I-NEXT:    li a0, 51
2092; RV32I-NEXT:    vand.vx v9, v8, a0
2093; RV32I-NEXT:    vsrl.vi v8, v8, 2
2094; RV32I-NEXT:    vand.vx v8, v8, a0
2095; RV32I-NEXT:    vadd.vv v8, v9, v8
2096; RV32I-NEXT:    vsrl.vi v9, v8, 4
2097; RV32I-NEXT:    vadd.vv v8, v8, v9
2098; RV32I-NEXT:    vand.vi v8, v8, 15
2099; RV32I-NEXT:    ret
2100;
2101; RV64I-LABEL: cttz_zero_undef_nxv8i8:
2102; RV64I:       # %bb.0:
2103; RV64I-NEXT:    li a0, 1
2104; RV64I-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
2105; RV64I-NEXT:    vsub.vx v9, v8, a0
2106; RV64I-NEXT:    vxor.vi v8, v8, -1
2107; RV64I-NEXT:    vand.vv v8, v8, v9
2108; RV64I-NEXT:    vsrl.vi v9, v8, 1
2109; RV64I-NEXT:    li a0, 85
2110; RV64I-NEXT:    vand.vx v9, v9, a0
2111; RV64I-NEXT:    vsub.vv v8, v8, v9
2112; RV64I-NEXT:    li a0, 51
2113; RV64I-NEXT:    vand.vx v9, v8, a0
2114; RV64I-NEXT:    vsrl.vi v8, v8, 2
2115; RV64I-NEXT:    vand.vx v8, v8, a0
2116; RV64I-NEXT:    vadd.vv v8, v9, v8
2117; RV64I-NEXT:    vsrl.vi v9, v8, 4
2118; RV64I-NEXT:    vadd.vv v8, v8, v9
2119; RV64I-NEXT:    vand.vi v8, v8, 15
2120; RV64I-NEXT:    ret
2121;
2122; RV32D-LABEL: cttz_zero_undef_nxv8i8:
2123; RV32D:       # %bb.0:
2124; RV32D-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
2125; RV32D-NEXT:    vrsub.vi v9, v8, 0
2126; RV32D-NEXT:    vand.vv v8, v8, v9
2127; RV32D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
2128; RV32D-NEXT:    vzext.vf4 v12, v8
2129; RV32D-NEXT:    vfcvt.f.xu.v v8, v12
2130; RV32D-NEXT:    vsrl.vi v8, v8, 23
2131; RV32D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
2132; RV32D-NEXT:    vnsrl.wi v12, v8, 0
2133; RV32D-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
2134; RV32D-NEXT:    vnsrl.wi v8, v12, 0
2135; RV32D-NEXT:    li a0, 127
2136; RV32D-NEXT:    vsub.vx v8, v8, a0
2137; RV32D-NEXT:    ret
2138;
2139; RV64D-LABEL: cttz_zero_undef_nxv8i8:
2140; RV64D:       # %bb.0:
2141; RV64D-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
2142; RV64D-NEXT:    vrsub.vi v9, v8, 0
2143; RV64D-NEXT:    vand.vv v8, v8, v9
2144; RV64D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
2145; RV64D-NEXT:    vzext.vf4 v12, v8
2146; RV64D-NEXT:    vfcvt.f.xu.v v8, v12
2147; RV64D-NEXT:    vsrl.vi v8, v8, 23
2148; RV64D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
2149; RV64D-NEXT:    vnsrl.wi v12, v8, 0
2150; RV64D-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
2151; RV64D-NEXT:    vnsrl.wi v8, v12, 0
2152; RV64D-NEXT:    li a0, 127
2153; RV64D-NEXT:    vsub.vx v8, v8, a0
2154; RV64D-NEXT:    ret
2155  %a = call <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 true)
2156  ret <vscale x 8 x i8> %a
2157}
2158
2159define <vscale x 16 x i8> @cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) {
2160; RV32I-LABEL: cttz_zero_undef_nxv16i8:
2161; RV32I:       # %bb.0:
2162; RV32I-NEXT:    li a0, 1
2163; RV32I-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
2164; RV32I-NEXT:    vsub.vx v10, v8, a0
2165; RV32I-NEXT:    vxor.vi v8, v8, -1
2166; RV32I-NEXT:    vand.vv v8, v8, v10
2167; RV32I-NEXT:    vsrl.vi v10, v8, 1
2168; RV32I-NEXT:    li a0, 85
2169; RV32I-NEXT:    vand.vx v10, v10, a0
2170; RV32I-NEXT:    vsub.vv v8, v8, v10
2171; RV32I-NEXT:    li a0, 51
2172; RV32I-NEXT:    vand.vx v10, v8, a0
2173; RV32I-NEXT:    vsrl.vi v8, v8, 2
2174; RV32I-NEXT:    vand.vx v8, v8, a0
2175; RV32I-NEXT:    vadd.vv v8, v10, v8
2176; RV32I-NEXT:    vsrl.vi v10, v8, 4
2177; RV32I-NEXT:    vadd.vv v8, v8, v10
2178; RV32I-NEXT:    vand.vi v8, v8, 15
2179; RV32I-NEXT:    ret
2180;
2181; RV64I-LABEL: cttz_zero_undef_nxv16i8:
2182; RV64I:       # %bb.0:
2183; RV64I-NEXT:    li a0, 1
2184; RV64I-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
2185; RV64I-NEXT:    vsub.vx v10, v8, a0
2186; RV64I-NEXT:    vxor.vi v8, v8, -1
2187; RV64I-NEXT:    vand.vv v8, v8, v10
2188; RV64I-NEXT:    vsrl.vi v10, v8, 1
2189; RV64I-NEXT:    li a0, 85
2190; RV64I-NEXT:    vand.vx v10, v10, a0
2191; RV64I-NEXT:    vsub.vv v8, v8, v10
2192; RV64I-NEXT:    li a0, 51
2193; RV64I-NEXT:    vand.vx v10, v8, a0
2194; RV64I-NEXT:    vsrl.vi v8, v8, 2
2195; RV64I-NEXT:    vand.vx v8, v8, a0
2196; RV64I-NEXT:    vadd.vv v8, v10, v8
2197; RV64I-NEXT:    vsrl.vi v10, v8, 4
2198; RV64I-NEXT:    vadd.vv v8, v8, v10
2199; RV64I-NEXT:    vand.vi v8, v8, 15
2200; RV64I-NEXT:    ret
2201;
2202; RV32D-LABEL: cttz_zero_undef_nxv16i8:
2203; RV32D:       # %bb.0:
2204; RV32D-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
2205; RV32D-NEXT:    vrsub.vi v10, v8, 0
2206; RV32D-NEXT:    vand.vv v8, v8, v10
2207; RV32D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
2208; RV32D-NEXT:    vzext.vf4 v16, v8
2209; RV32D-NEXT:    vfcvt.f.xu.v v8, v16
2210; RV32D-NEXT:    vsrl.vi v8, v8, 23
2211; RV32D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
2212; RV32D-NEXT:    vnsrl.wi v16, v8, 0
2213; RV32D-NEXT:    vsetvli zero, zero, e8, m2, ta, mu
2214; RV32D-NEXT:    vnsrl.wi v8, v16, 0
2215; RV32D-NEXT:    li a0, 127
2216; RV32D-NEXT:    vsub.vx v8, v8, a0
2217; RV32D-NEXT:    ret
2218;
2219; RV64D-LABEL: cttz_zero_undef_nxv16i8:
2220; RV64D:       # %bb.0:
2221; RV64D-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
2222; RV64D-NEXT:    vrsub.vi v10, v8, 0
2223; RV64D-NEXT:    vand.vv v8, v8, v10
2224; RV64D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
2225; RV64D-NEXT:    vzext.vf4 v16, v8
2226; RV64D-NEXT:    vfcvt.f.xu.v v8, v16
2227; RV64D-NEXT:    vsrl.vi v8, v8, 23
2228; RV64D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
2229; RV64D-NEXT:    vnsrl.wi v16, v8, 0
2230; RV64D-NEXT:    vsetvli zero, zero, e8, m2, ta, mu
2231; RV64D-NEXT:    vnsrl.wi v8, v16, 0
2232; RV64D-NEXT:    li a0, 127
2233; RV64D-NEXT:    vsub.vx v8, v8, a0
2234; RV64D-NEXT:    ret
2235  %a = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 true)
2236  ret <vscale x 16 x i8> %a
2237}
2238
2239define <vscale x 32 x i8> @cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va) {
2240; CHECK-LABEL: cttz_zero_undef_nxv32i8:
2241; CHECK:       # %bb.0:
2242; CHECK-NEXT:    li a0, 1
2243; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
2244; CHECK-NEXT:    vsub.vx v12, v8, a0
2245; CHECK-NEXT:    vxor.vi v8, v8, -1
2246; CHECK-NEXT:    vand.vv v8, v8, v12
2247; CHECK-NEXT:    vsrl.vi v12, v8, 1
2248; CHECK-NEXT:    li a0, 85
2249; CHECK-NEXT:    vand.vx v12, v12, a0
2250; CHECK-NEXT:    vsub.vv v8, v8, v12
2251; CHECK-NEXT:    li a0, 51
2252; CHECK-NEXT:    vand.vx v12, v8, a0
2253; CHECK-NEXT:    vsrl.vi v8, v8, 2
2254; CHECK-NEXT:    vand.vx v8, v8, a0
2255; CHECK-NEXT:    vadd.vv v8, v12, v8
2256; CHECK-NEXT:    vsrl.vi v12, v8, 4
2257; CHECK-NEXT:    vadd.vv v8, v8, v12
2258; CHECK-NEXT:    vand.vi v8, v8, 15
2259; CHECK-NEXT:    ret
2260  %a = call <vscale x 32 x i8> @llvm.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 true)
2261  ret <vscale x 32 x i8> %a
2262}
2263
2264define <vscale x 64 x i8> @cttz_zero_undef_nxv64i8(<vscale x 64 x i8> %va) {
2265; CHECK-LABEL: cttz_zero_undef_nxv64i8:
2266; CHECK:       # %bb.0:
2267; CHECK-NEXT:    li a0, 1
2268; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
2269; CHECK-NEXT:    vsub.vx v16, v8, a0
2270; CHECK-NEXT:    vxor.vi v8, v8, -1
2271; CHECK-NEXT:    vand.vv v8, v8, v16
2272; CHECK-NEXT:    vsrl.vi v16, v8, 1
2273; CHECK-NEXT:    li a0, 85
2274; CHECK-NEXT:    vand.vx v16, v16, a0
2275; CHECK-NEXT:    vsub.vv v8, v8, v16
2276; CHECK-NEXT:    li a0, 51
2277; CHECK-NEXT:    vand.vx v16, v8, a0
2278; CHECK-NEXT:    vsrl.vi v8, v8, 2
2279; CHECK-NEXT:    vand.vx v8, v8, a0
2280; CHECK-NEXT:    vadd.vv v8, v16, v8
2281; CHECK-NEXT:    vsrl.vi v16, v8, 4
2282; CHECK-NEXT:    vadd.vv v8, v8, v16
2283; CHECK-NEXT:    vand.vi v8, v8, 15
2284; CHECK-NEXT:    ret
2285  %a = call <vscale x 64 x i8> @llvm.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 true)
2286  ret <vscale x 64 x i8> %a
2287}
2288
2289define <vscale x 1 x i16> @cttz_zero_undef_nxv1i16(<vscale x 1 x i16> %va) {
2290; RV32I-LABEL: cttz_zero_undef_nxv1i16:
2291; RV32I:       # %bb.0:
2292; RV32I-NEXT:    li a0, 1
2293; RV32I-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
2294; RV32I-NEXT:    vsub.vx v9, v8, a0
2295; RV32I-NEXT:    vxor.vi v8, v8, -1
2296; RV32I-NEXT:    vand.vv v8, v8, v9
2297; RV32I-NEXT:    vsrl.vi v9, v8, 1
2298; RV32I-NEXT:    lui a0, 5
2299; RV32I-NEXT:    addi a0, a0, 1365
2300; RV32I-NEXT:    vand.vx v9, v9, a0
2301; RV32I-NEXT:    vsub.vv v8, v8, v9
2302; RV32I-NEXT:    lui a0, 3
2303; RV32I-NEXT:    addi a0, a0, 819
2304; RV32I-NEXT:    vand.vx v9, v8, a0
2305; RV32I-NEXT:    vsrl.vi v8, v8, 2
2306; RV32I-NEXT:    vand.vx v8, v8, a0
2307; RV32I-NEXT:    vadd.vv v8, v9, v8
2308; RV32I-NEXT:    vsrl.vi v9, v8, 4
2309; RV32I-NEXT:    vadd.vv v8, v8, v9
2310; RV32I-NEXT:    lui a0, 1
2311; RV32I-NEXT:    addi a0, a0, -241
2312; RV32I-NEXT:    vand.vx v8, v8, a0
2313; RV32I-NEXT:    li a0, 257
2314; RV32I-NEXT:    vmul.vx v8, v8, a0
2315; RV32I-NEXT:    vsrl.vi v8, v8, 8
2316; RV32I-NEXT:    ret
2317;
2318; RV64I-LABEL: cttz_zero_undef_nxv1i16:
2319; RV64I:       # %bb.0:
2320; RV64I-NEXT:    li a0, 1
2321; RV64I-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
2322; RV64I-NEXT:    vsub.vx v9, v8, a0
2323; RV64I-NEXT:    vxor.vi v8, v8, -1
2324; RV64I-NEXT:    vand.vv v8, v8, v9
2325; RV64I-NEXT:    vsrl.vi v9, v8, 1
2326; RV64I-NEXT:    lui a0, 5
2327; RV64I-NEXT:    addiw a0, a0, 1365
2328; RV64I-NEXT:    vand.vx v9, v9, a0
2329; RV64I-NEXT:    vsub.vv v8, v8, v9
2330; RV64I-NEXT:    lui a0, 3
2331; RV64I-NEXT:    addiw a0, a0, 819
2332; RV64I-NEXT:    vand.vx v9, v8, a0
2333; RV64I-NEXT:    vsrl.vi v8, v8, 2
2334; RV64I-NEXT:    vand.vx v8, v8, a0
2335; RV64I-NEXT:    vadd.vv v8, v9, v8
2336; RV64I-NEXT:    vsrl.vi v9, v8, 4
2337; RV64I-NEXT:    vadd.vv v8, v8, v9
2338; RV64I-NEXT:    lui a0, 1
2339; RV64I-NEXT:    addiw a0, a0, -241
2340; RV64I-NEXT:    vand.vx v8, v8, a0
2341; RV64I-NEXT:    li a0, 257
2342; RV64I-NEXT:    vmul.vx v8, v8, a0
2343; RV64I-NEXT:    vsrl.vi v8, v8, 8
2344; RV64I-NEXT:    ret
2345;
2346; RV32D-LABEL: cttz_zero_undef_nxv1i16:
2347; RV32D:       # %bb.0:
2348; RV32D-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
2349; RV32D-NEXT:    vrsub.vi v9, v8, 0
2350; RV32D-NEXT:    vand.vv v8, v8, v9
2351; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
2352; RV32D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
2353; RV32D-NEXT:    vsrl.vi v8, v9, 23
2354; RV32D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
2355; RV32D-NEXT:    vnsrl.wi v8, v8, 0
2356; RV32D-NEXT:    li a0, 127
2357; RV32D-NEXT:    vsub.vx v8, v8, a0
2358; RV32D-NEXT:    ret
2359;
2360; RV64D-LABEL: cttz_zero_undef_nxv1i16:
2361; RV64D:       # %bb.0:
2362; RV64D-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
2363; RV64D-NEXT:    vrsub.vi v9, v8, 0
2364; RV64D-NEXT:    vand.vv v8, v8, v9
2365; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
2366; RV64D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
2367; RV64D-NEXT:    vsrl.vi v8, v9, 23
2368; RV64D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
2369; RV64D-NEXT:    vnsrl.wi v8, v8, 0
2370; RV64D-NEXT:    li a0, 127
2371; RV64D-NEXT:    vsub.vx v8, v8, a0
2372; RV64D-NEXT:    ret
2373  %a = call <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 true)
2374  ret <vscale x 1 x i16> %a
2375}
2376
2377define <vscale x 2 x i16> @cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) {
2378; RV32I-LABEL: cttz_zero_undef_nxv2i16:
2379; RV32I:       # %bb.0:
2380; RV32I-NEXT:    li a0, 1
2381; RV32I-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
2382; RV32I-NEXT:    vsub.vx v9, v8, a0
2383; RV32I-NEXT:    vxor.vi v8, v8, -1
2384; RV32I-NEXT:    vand.vv v8, v8, v9
2385; RV32I-NEXT:    vsrl.vi v9, v8, 1
2386; RV32I-NEXT:    lui a0, 5
2387; RV32I-NEXT:    addi a0, a0, 1365
2388; RV32I-NEXT:    vand.vx v9, v9, a0
2389; RV32I-NEXT:    vsub.vv v8, v8, v9
2390; RV32I-NEXT:    lui a0, 3
2391; RV32I-NEXT:    addi a0, a0, 819
2392; RV32I-NEXT:    vand.vx v9, v8, a0
2393; RV32I-NEXT:    vsrl.vi v8, v8, 2
2394; RV32I-NEXT:    vand.vx v8, v8, a0
2395; RV32I-NEXT:    vadd.vv v8, v9, v8
2396; RV32I-NEXT:    vsrl.vi v9, v8, 4
2397; RV32I-NEXT:    vadd.vv v8, v8, v9
2398; RV32I-NEXT:    lui a0, 1
2399; RV32I-NEXT:    addi a0, a0, -241
2400; RV32I-NEXT:    vand.vx v8, v8, a0
2401; RV32I-NEXT:    li a0, 257
2402; RV32I-NEXT:    vmul.vx v8, v8, a0
2403; RV32I-NEXT:    vsrl.vi v8, v8, 8
2404; RV32I-NEXT:    ret
2405;
2406; RV64I-LABEL: cttz_zero_undef_nxv2i16:
2407; RV64I:       # %bb.0:
2408; RV64I-NEXT:    li a0, 1
2409; RV64I-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
2410; RV64I-NEXT:    vsub.vx v9, v8, a0
2411; RV64I-NEXT:    vxor.vi v8, v8, -1
2412; RV64I-NEXT:    vand.vv v8, v8, v9
2413; RV64I-NEXT:    vsrl.vi v9, v8, 1
2414; RV64I-NEXT:    lui a0, 5
2415; RV64I-NEXT:    addiw a0, a0, 1365
2416; RV64I-NEXT:    vand.vx v9, v9, a0
2417; RV64I-NEXT:    vsub.vv v8, v8, v9
2418; RV64I-NEXT:    lui a0, 3
2419; RV64I-NEXT:    addiw a0, a0, 819
2420; RV64I-NEXT:    vand.vx v9, v8, a0
2421; RV64I-NEXT:    vsrl.vi v8, v8, 2
2422; RV64I-NEXT:    vand.vx v8, v8, a0
2423; RV64I-NEXT:    vadd.vv v8, v9, v8
2424; RV64I-NEXT:    vsrl.vi v9, v8, 4
2425; RV64I-NEXT:    vadd.vv v8, v8, v9
2426; RV64I-NEXT:    lui a0, 1
2427; RV64I-NEXT:    addiw a0, a0, -241
2428; RV64I-NEXT:    vand.vx v8, v8, a0
2429; RV64I-NEXT:    li a0, 257
2430; RV64I-NEXT:    vmul.vx v8, v8, a0
2431; RV64I-NEXT:    vsrl.vi v8, v8, 8
2432; RV64I-NEXT:    ret
2433;
2434; RV32D-LABEL: cttz_zero_undef_nxv2i16:
2435; RV32D:       # %bb.0:
2436; RV32D-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
2437; RV32D-NEXT:    vrsub.vi v9, v8, 0
2438; RV32D-NEXT:    vand.vv v8, v8, v9
2439; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
2440; RV32D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
2441; RV32D-NEXT:    vsrl.vi v8, v9, 23
2442; RV32D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
2443; RV32D-NEXT:    vnsrl.wi v8, v8, 0
2444; RV32D-NEXT:    li a0, 127
2445; RV32D-NEXT:    vsub.vx v8, v8, a0
2446; RV32D-NEXT:    ret
2447;
2448; RV64D-LABEL: cttz_zero_undef_nxv2i16:
2449; RV64D:       # %bb.0:
2450; RV64D-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
2451; RV64D-NEXT:    vrsub.vi v9, v8, 0
2452; RV64D-NEXT:    vand.vv v8, v8, v9
2453; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
2454; RV64D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
2455; RV64D-NEXT:    vsrl.vi v8, v9, 23
2456; RV64D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
2457; RV64D-NEXT:    vnsrl.wi v8, v8, 0
2458; RV64D-NEXT:    li a0, 127
2459; RV64D-NEXT:    vsub.vx v8, v8, a0
2460; RV64D-NEXT:    ret
2461  %a = call <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 true)
2462  ret <vscale x 2 x i16> %a
2463}
2464
2465define <vscale x 4 x i16> @cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) {
2466; RV32I-LABEL: cttz_zero_undef_nxv4i16:
2467; RV32I:       # %bb.0:
2468; RV32I-NEXT:    li a0, 1
2469; RV32I-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
2470; RV32I-NEXT:    vsub.vx v9, v8, a0
2471; RV32I-NEXT:    vxor.vi v8, v8, -1
2472; RV32I-NEXT:    vand.vv v8, v8, v9
2473; RV32I-NEXT:    vsrl.vi v9, v8, 1
2474; RV32I-NEXT:    lui a0, 5
2475; RV32I-NEXT:    addi a0, a0, 1365
2476; RV32I-NEXT:    vand.vx v9, v9, a0
2477; RV32I-NEXT:    vsub.vv v8, v8, v9
2478; RV32I-NEXT:    lui a0, 3
2479; RV32I-NEXT:    addi a0, a0, 819
2480; RV32I-NEXT:    vand.vx v9, v8, a0
2481; RV32I-NEXT:    vsrl.vi v8, v8, 2
2482; RV32I-NEXT:    vand.vx v8, v8, a0
2483; RV32I-NEXT:    vadd.vv v8, v9, v8
2484; RV32I-NEXT:    vsrl.vi v9, v8, 4
2485; RV32I-NEXT:    vadd.vv v8, v8, v9
2486; RV32I-NEXT:    lui a0, 1
2487; RV32I-NEXT:    addi a0, a0, -241
2488; RV32I-NEXT:    vand.vx v8, v8, a0
2489; RV32I-NEXT:    li a0, 257
2490; RV32I-NEXT:    vmul.vx v8, v8, a0
2491; RV32I-NEXT:    vsrl.vi v8, v8, 8
2492; RV32I-NEXT:    ret
2493;
2494; RV64I-LABEL: cttz_zero_undef_nxv4i16:
2495; RV64I:       # %bb.0:
2496; RV64I-NEXT:    li a0, 1
2497; RV64I-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
2498; RV64I-NEXT:    vsub.vx v9, v8, a0
2499; RV64I-NEXT:    vxor.vi v8, v8, -1
2500; RV64I-NEXT:    vand.vv v8, v8, v9
2501; RV64I-NEXT:    vsrl.vi v9, v8, 1
2502; RV64I-NEXT:    lui a0, 5
2503; RV64I-NEXT:    addiw a0, a0, 1365
2504; RV64I-NEXT:    vand.vx v9, v9, a0
2505; RV64I-NEXT:    vsub.vv v8, v8, v9
2506; RV64I-NEXT:    lui a0, 3
2507; RV64I-NEXT:    addiw a0, a0, 819
2508; RV64I-NEXT:    vand.vx v9, v8, a0
2509; RV64I-NEXT:    vsrl.vi v8, v8, 2
2510; RV64I-NEXT:    vand.vx v8, v8, a0
2511; RV64I-NEXT:    vadd.vv v8, v9, v8
2512; RV64I-NEXT:    vsrl.vi v9, v8, 4
2513; RV64I-NEXT:    vadd.vv v8, v8, v9
2514; RV64I-NEXT:    lui a0, 1
2515; RV64I-NEXT:    addiw a0, a0, -241
2516; RV64I-NEXT:    vand.vx v8, v8, a0
2517; RV64I-NEXT:    li a0, 257
2518; RV64I-NEXT:    vmul.vx v8, v8, a0
2519; RV64I-NEXT:    vsrl.vi v8, v8, 8
2520; RV64I-NEXT:    ret
2521;
2522; RV32D-LABEL: cttz_zero_undef_nxv4i16:
2523; RV32D:       # %bb.0:
2524; RV32D-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
2525; RV32D-NEXT:    vrsub.vi v9, v8, 0
2526; RV32D-NEXT:    vand.vv v8, v8, v9
2527; RV32D-NEXT:    vfwcvt.f.xu.v v10, v8
2528; RV32D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
2529; RV32D-NEXT:    vsrl.vi v8, v10, 23
2530; RV32D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
2531; RV32D-NEXT:    vnsrl.wi v10, v8, 0
2532; RV32D-NEXT:    li a0, 127
2533; RV32D-NEXT:    vsub.vx v8, v10, a0
2534; RV32D-NEXT:    ret
2535;
2536; RV64D-LABEL: cttz_zero_undef_nxv4i16:
2537; RV64D:       # %bb.0:
2538; RV64D-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
2539; RV64D-NEXT:    vrsub.vi v9, v8, 0
2540; RV64D-NEXT:    vand.vv v8, v8, v9
2541; RV64D-NEXT:    vfwcvt.f.xu.v v10, v8
2542; RV64D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
2543; RV64D-NEXT:    vsrl.vi v8, v10, 23
2544; RV64D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
2545; RV64D-NEXT:    vnsrl.wi v10, v8, 0
2546; RV64D-NEXT:    li a0, 127
2547; RV64D-NEXT:    vsub.vx v8, v10, a0
2548; RV64D-NEXT:    ret
2549  %a = call <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 true)
2550  ret <vscale x 4 x i16> %a
2551}
2552
2553define <vscale x 8 x i16> @cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
2554; RV32I-LABEL: cttz_zero_undef_nxv8i16:
2555; RV32I:       # %bb.0:
2556; RV32I-NEXT:    li a0, 1
2557; RV32I-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
2558; RV32I-NEXT:    vsub.vx v10, v8, a0
2559; RV32I-NEXT:    vxor.vi v8, v8, -1
2560; RV32I-NEXT:    vand.vv v8, v8, v10
2561; RV32I-NEXT:    vsrl.vi v10, v8, 1
2562; RV32I-NEXT:    lui a0, 5
2563; RV32I-NEXT:    addi a0, a0, 1365
2564; RV32I-NEXT:    vand.vx v10, v10, a0
2565; RV32I-NEXT:    vsub.vv v8, v8, v10
2566; RV32I-NEXT:    lui a0, 3
2567; RV32I-NEXT:    addi a0, a0, 819
2568; RV32I-NEXT:    vand.vx v10, v8, a0
2569; RV32I-NEXT:    vsrl.vi v8, v8, 2
2570; RV32I-NEXT:    vand.vx v8, v8, a0
2571; RV32I-NEXT:    vadd.vv v8, v10, v8
2572; RV32I-NEXT:    vsrl.vi v10, v8, 4
2573; RV32I-NEXT:    vadd.vv v8, v8, v10
2574; RV32I-NEXT:    lui a0, 1
2575; RV32I-NEXT:    addi a0, a0, -241
2576; RV32I-NEXT:    vand.vx v8, v8, a0
2577; RV32I-NEXT:    li a0, 257
2578; RV32I-NEXT:    vmul.vx v8, v8, a0
2579; RV32I-NEXT:    vsrl.vi v8, v8, 8
2580; RV32I-NEXT:    ret
2581;
2582; RV64I-LABEL: cttz_zero_undef_nxv8i16:
2583; RV64I:       # %bb.0:
2584; RV64I-NEXT:    li a0, 1
2585; RV64I-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
2586; RV64I-NEXT:    vsub.vx v10, v8, a0
2587; RV64I-NEXT:    vxor.vi v8, v8, -1
2588; RV64I-NEXT:    vand.vv v8, v8, v10
2589; RV64I-NEXT:    vsrl.vi v10, v8, 1
2590; RV64I-NEXT:    lui a0, 5
2591; RV64I-NEXT:    addiw a0, a0, 1365
2592; RV64I-NEXT:    vand.vx v10, v10, a0
2593; RV64I-NEXT:    vsub.vv v8, v8, v10
2594; RV64I-NEXT:    lui a0, 3
2595; RV64I-NEXT:    addiw a0, a0, 819
2596; RV64I-NEXT:    vand.vx v10, v8, a0
2597; RV64I-NEXT:    vsrl.vi v8, v8, 2
2598; RV64I-NEXT:    vand.vx v8, v8, a0
2599; RV64I-NEXT:    vadd.vv v8, v10, v8
2600; RV64I-NEXT:    vsrl.vi v10, v8, 4
2601; RV64I-NEXT:    vadd.vv v8, v8, v10
2602; RV64I-NEXT:    lui a0, 1
2603; RV64I-NEXT:    addiw a0, a0, -241
2604; RV64I-NEXT:    vand.vx v8, v8, a0
2605; RV64I-NEXT:    li a0, 257
2606; RV64I-NEXT:    vmul.vx v8, v8, a0
2607; RV64I-NEXT:    vsrl.vi v8, v8, 8
2608; RV64I-NEXT:    ret
2609;
2610; RV32D-LABEL: cttz_zero_undef_nxv8i16:
2611; RV32D:       # %bb.0:
2612; RV32D-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
2613; RV32D-NEXT:    vrsub.vi v10, v8, 0
2614; RV32D-NEXT:    vand.vv v8, v8, v10
2615; RV32D-NEXT:    vfwcvt.f.xu.v v12, v8
2616; RV32D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
2617; RV32D-NEXT:    vsrl.vi v8, v12, 23
2618; RV32D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
2619; RV32D-NEXT:    vnsrl.wi v12, v8, 0
2620; RV32D-NEXT:    li a0, 127
2621; RV32D-NEXT:    vsub.vx v8, v12, a0
2622; RV32D-NEXT:    ret
2623;
2624; RV64D-LABEL: cttz_zero_undef_nxv8i16:
2625; RV64D:       # %bb.0:
2626; RV64D-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
2627; RV64D-NEXT:    vrsub.vi v10, v8, 0
2628; RV64D-NEXT:    vand.vv v8, v8, v10
2629; RV64D-NEXT:    vfwcvt.f.xu.v v12, v8
2630; RV64D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
2631; RV64D-NEXT:    vsrl.vi v8, v12, 23
2632; RV64D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
2633; RV64D-NEXT:    vnsrl.wi v12, v8, 0
2634; RV64D-NEXT:    li a0, 127
2635; RV64D-NEXT:    vsub.vx v8, v12, a0
2636; RV64D-NEXT:    ret
2637  %a = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 true)
2638  ret <vscale x 8 x i16> %a
2639}
2640
2641define <vscale x 16 x i16> @cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
2642; RV32I-LABEL: cttz_zero_undef_nxv16i16:
2643; RV32I:       # %bb.0:
2644; RV32I-NEXT:    li a0, 1
2645; RV32I-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
2646; RV32I-NEXT:    vsub.vx v12, v8, a0
2647; RV32I-NEXT:    vxor.vi v8, v8, -1
2648; RV32I-NEXT:    vand.vv v8, v8, v12
2649; RV32I-NEXT:    vsrl.vi v12, v8, 1
2650; RV32I-NEXT:    lui a0, 5
2651; RV32I-NEXT:    addi a0, a0, 1365
2652; RV32I-NEXT:    vand.vx v12, v12, a0
2653; RV32I-NEXT:    vsub.vv v8, v8, v12
2654; RV32I-NEXT:    lui a0, 3
2655; RV32I-NEXT:    addi a0, a0, 819
2656; RV32I-NEXT:    vand.vx v12, v8, a0
2657; RV32I-NEXT:    vsrl.vi v8, v8, 2
2658; RV32I-NEXT:    vand.vx v8, v8, a0
2659; RV32I-NEXT:    vadd.vv v8, v12, v8
2660; RV32I-NEXT:    vsrl.vi v12, v8, 4
2661; RV32I-NEXT:    vadd.vv v8, v8, v12
2662; RV32I-NEXT:    lui a0, 1
2663; RV32I-NEXT:    addi a0, a0, -241
2664; RV32I-NEXT:    vand.vx v8, v8, a0
2665; RV32I-NEXT:    li a0, 257
2666; RV32I-NEXT:    vmul.vx v8, v8, a0
2667; RV32I-NEXT:    vsrl.vi v8, v8, 8
2668; RV32I-NEXT:    ret
2669;
2670; RV64I-LABEL: cttz_zero_undef_nxv16i16:
2671; RV64I:       # %bb.0:
2672; RV64I-NEXT:    li a0, 1
2673; RV64I-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
2674; RV64I-NEXT:    vsub.vx v12, v8, a0
2675; RV64I-NEXT:    vxor.vi v8, v8, -1
2676; RV64I-NEXT:    vand.vv v8, v8, v12
2677; RV64I-NEXT:    vsrl.vi v12, v8, 1
2678; RV64I-NEXT:    lui a0, 5
2679; RV64I-NEXT:    addiw a0, a0, 1365
2680; RV64I-NEXT:    vand.vx v12, v12, a0
2681; RV64I-NEXT:    vsub.vv v8, v8, v12
2682; RV64I-NEXT:    lui a0, 3
2683; RV64I-NEXT:    addiw a0, a0, 819
2684; RV64I-NEXT:    vand.vx v12, v8, a0
2685; RV64I-NEXT:    vsrl.vi v8, v8, 2
2686; RV64I-NEXT:    vand.vx v8, v8, a0
2687; RV64I-NEXT:    vadd.vv v8, v12, v8
2688; RV64I-NEXT:    vsrl.vi v12, v8, 4
2689; RV64I-NEXT:    vadd.vv v8, v8, v12
2690; RV64I-NEXT:    lui a0, 1
2691; RV64I-NEXT:    addiw a0, a0, -241
2692; RV64I-NEXT:    vand.vx v8, v8, a0
2693; RV64I-NEXT:    li a0, 257
2694; RV64I-NEXT:    vmul.vx v8, v8, a0
2695; RV64I-NEXT:    vsrl.vi v8, v8, 8
2696; RV64I-NEXT:    ret
2697;
2698; RV32D-LABEL: cttz_zero_undef_nxv16i16:
2699; RV32D:       # %bb.0:
2700; RV32D-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
2701; RV32D-NEXT:    vrsub.vi v12, v8, 0
2702; RV32D-NEXT:    vand.vv v8, v8, v12
2703; RV32D-NEXT:    vfwcvt.f.xu.v v16, v8
2704; RV32D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
2705; RV32D-NEXT:    vsrl.vi v8, v16, 23
2706; RV32D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
2707; RV32D-NEXT:    vnsrl.wi v16, v8, 0
2708; RV32D-NEXT:    li a0, 127
2709; RV32D-NEXT:    vsub.vx v8, v16, a0
2710; RV32D-NEXT:    ret
2711;
2712; RV64D-LABEL: cttz_zero_undef_nxv16i16:
2713; RV64D:       # %bb.0:
2714; RV64D-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
2715; RV64D-NEXT:    vrsub.vi v12, v8, 0
2716; RV64D-NEXT:    vand.vv v8, v8, v12
2717; RV64D-NEXT:    vfwcvt.f.xu.v v16, v8
2718; RV64D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
2719; RV64D-NEXT:    vsrl.vi v8, v16, 23
2720; RV64D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
2721; RV64D-NEXT:    vnsrl.wi v16, v8, 0
2722; RV64D-NEXT:    li a0, 127
2723; RV64D-NEXT:    vsub.vx v8, v16, a0
2724; RV64D-NEXT:    ret
2725  %a = call <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 true)
2726  ret <vscale x 16 x i16> %a
2727}
2728
2729define <vscale x 32 x i16> @cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va) {
2730; RV32-LABEL: cttz_zero_undef_nxv32i16:
2731; RV32:       # %bb.0:
2732; RV32-NEXT:    li a0, 1
2733; RV32-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
2734; RV32-NEXT:    vsub.vx v16, v8, a0
2735; RV32-NEXT:    vxor.vi v8, v8, -1
2736; RV32-NEXT:    vand.vv v8, v8, v16
2737; RV32-NEXT:    vsrl.vi v16, v8, 1
2738; RV32-NEXT:    lui a0, 5
2739; RV32-NEXT:    addi a0, a0, 1365
2740; RV32-NEXT:    vand.vx v16, v16, a0
2741; RV32-NEXT:    vsub.vv v8, v8, v16
2742; RV32-NEXT:    lui a0, 3
2743; RV32-NEXT:    addi a0, a0, 819
2744; RV32-NEXT:    vand.vx v16, v8, a0
2745; RV32-NEXT:    vsrl.vi v8, v8, 2
2746; RV32-NEXT:    vand.vx v8, v8, a0
2747; RV32-NEXT:    vadd.vv v8, v16, v8
2748; RV32-NEXT:    vsrl.vi v16, v8, 4
2749; RV32-NEXT:    vadd.vv v8, v8, v16
2750; RV32-NEXT:    lui a0, 1
2751; RV32-NEXT:    addi a0, a0, -241
2752; RV32-NEXT:    vand.vx v8, v8, a0
2753; RV32-NEXT:    li a0, 257
2754; RV32-NEXT:    vmul.vx v8, v8, a0
2755; RV32-NEXT:    vsrl.vi v8, v8, 8
2756; RV32-NEXT:    ret
2757;
2758; RV64-LABEL: cttz_zero_undef_nxv32i16:
2759; RV64:       # %bb.0:
2760; RV64-NEXT:    li a0, 1
2761; RV64-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
2762; RV64-NEXT:    vsub.vx v16, v8, a0
2763; RV64-NEXT:    vxor.vi v8, v8, -1
2764; RV64-NEXT:    vand.vv v8, v8, v16
2765; RV64-NEXT:    vsrl.vi v16, v8, 1
2766; RV64-NEXT:    lui a0, 5
2767; RV64-NEXT:    addiw a0, a0, 1365
2768; RV64-NEXT:    vand.vx v16, v16, a0
2769; RV64-NEXT:    vsub.vv v8, v8, v16
2770; RV64-NEXT:    lui a0, 3
2771; RV64-NEXT:    addiw a0, a0, 819
2772; RV64-NEXT:    vand.vx v16, v8, a0
2773; RV64-NEXT:    vsrl.vi v8, v8, 2
2774; RV64-NEXT:    vand.vx v8, v8, a0
2775; RV64-NEXT:    vadd.vv v8, v16, v8
2776; RV64-NEXT:    vsrl.vi v16, v8, 4
2777; RV64-NEXT:    vadd.vv v8, v8, v16
2778; RV64-NEXT:    lui a0, 1
2779; RV64-NEXT:    addiw a0, a0, -241
2780; RV64-NEXT:    vand.vx v8, v8, a0
2781; RV64-NEXT:    li a0, 257
2782; RV64-NEXT:    vmul.vx v8, v8, a0
2783; RV64-NEXT:    vsrl.vi v8, v8, 8
2784; RV64-NEXT:    ret
2785  %a = call <vscale x 32 x i16> @llvm.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 true)
2786  ret <vscale x 32 x i16> %a
2787}
2788
2789define <vscale x 1 x i32> @cttz_zero_undef_nxv1i32(<vscale x 1 x i32> %va) {
2790; RV32I-LABEL: cttz_zero_undef_nxv1i32:
2791; RV32I:       # %bb.0:
2792; RV32I-NEXT:    li a0, 1
2793; RV32I-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
2794; RV32I-NEXT:    vsub.vx v9, v8, a0
2795; RV32I-NEXT:    vxor.vi v8, v8, -1
2796; RV32I-NEXT:    vand.vv v8, v8, v9
2797; RV32I-NEXT:    vsrl.vi v9, v8, 1
2798; RV32I-NEXT:    lui a0, 349525
2799; RV32I-NEXT:    addi a0, a0, 1365
2800; RV32I-NEXT:    vand.vx v9, v9, a0
2801; RV32I-NEXT:    vsub.vv v8, v8, v9
2802; RV32I-NEXT:    lui a0, 209715
2803; RV32I-NEXT:    addi a0, a0, 819
2804; RV32I-NEXT:    vand.vx v9, v8, a0
2805; RV32I-NEXT:    vsrl.vi v8, v8, 2
2806; RV32I-NEXT:    vand.vx v8, v8, a0
2807; RV32I-NEXT:    vadd.vv v8, v9, v8
2808; RV32I-NEXT:    vsrl.vi v9, v8, 4
2809; RV32I-NEXT:    vadd.vv v8, v8, v9
2810; RV32I-NEXT:    lui a0, 61681
2811; RV32I-NEXT:    addi a0, a0, -241
2812; RV32I-NEXT:    vand.vx v8, v8, a0
2813; RV32I-NEXT:    lui a0, 4112
2814; RV32I-NEXT:    addi a0, a0, 257
2815; RV32I-NEXT:    vmul.vx v8, v8, a0
2816; RV32I-NEXT:    vsrl.vi v8, v8, 24
2817; RV32I-NEXT:    ret
2818;
2819; RV64I-LABEL: cttz_zero_undef_nxv1i32:
2820; RV64I:       # %bb.0:
2821; RV64I-NEXT:    li a0, 1
2822; RV64I-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
2823; RV64I-NEXT:    vsub.vx v9, v8, a0
2824; RV64I-NEXT:    vxor.vi v8, v8, -1
2825; RV64I-NEXT:    vand.vv v8, v8, v9
2826; RV64I-NEXT:    vsrl.vi v9, v8, 1
2827; RV64I-NEXT:    lui a0, 349525
2828; RV64I-NEXT:    addiw a0, a0, 1365
2829; RV64I-NEXT:    vand.vx v9, v9, a0
2830; RV64I-NEXT:    vsub.vv v8, v8, v9
2831; RV64I-NEXT:    lui a0, 209715
2832; RV64I-NEXT:    addiw a0, a0, 819
2833; RV64I-NEXT:    vand.vx v9, v8, a0
2834; RV64I-NEXT:    vsrl.vi v8, v8, 2
2835; RV64I-NEXT:    vand.vx v8, v8, a0
2836; RV64I-NEXT:    vadd.vv v8, v9, v8
2837; RV64I-NEXT:    vsrl.vi v9, v8, 4
2838; RV64I-NEXT:    vadd.vv v8, v8, v9
2839; RV64I-NEXT:    lui a0, 61681
2840; RV64I-NEXT:    addiw a0, a0, -241
2841; RV64I-NEXT:    vand.vx v8, v8, a0
2842; RV64I-NEXT:    lui a0, 4112
2843; RV64I-NEXT:    addiw a0, a0, 257
2844; RV64I-NEXT:    vmul.vx v8, v8, a0
2845; RV64I-NEXT:    vsrl.vi v8, v8, 24
2846; RV64I-NEXT:    ret
2847;
2848; RV32D-LABEL: cttz_zero_undef_nxv1i32:
2849; RV32D:       # %bb.0:
2850; RV32D-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
2851; RV32D-NEXT:    vrsub.vi v9, v8, 0
2852; RV32D-NEXT:    vand.vv v8, v8, v9
2853; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
2854; RV32D-NEXT:    li a0, 52
2855; RV32D-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
2856; RV32D-NEXT:    vsrl.vx v8, v9, a0
2857; RV32D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
2858; RV32D-NEXT:    vnsrl.wi v8, v8, 0
2859; RV32D-NEXT:    li a0, 1023
2860; RV32D-NEXT:    vsub.vx v8, v8, a0
2861; RV32D-NEXT:    ret
2862;
2863; RV64D-LABEL: cttz_zero_undef_nxv1i32:
2864; RV64D:       # %bb.0:
2865; RV64D-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
2866; RV64D-NEXT:    vrsub.vi v9, v8, 0
2867; RV64D-NEXT:    vand.vv v8, v8, v9
2868; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
2869; RV64D-NEXT:    li a0, 52
2870; RV64D-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
2871; RV64D-NEXT:    vsrl.vx v8, v9, a0
2872; RV64D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
2873; RV64D-NEXT:    vnsrl.wi v8, v8, 0
2874; RV64D-NEXT:    li a0, 1023
2875; RV64D-NEXT:    vsub.vx v8, v8, a0
2876; RV64D-NEXT:    ret
2877  %a = call <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 true)
2878  ret <vscale x 1 x i32> %a
2879}
2880
2881define <vscale x 2 x i32> @cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) {
2882; RV32I-LABEL: cttz_zero_undef_nxv2i32:
2883; RV32I:       # %bb.0:
2884; RV32I-NEXT:    li a0, 1
2885; RV32I-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
2886; RV32I-NEXT:    vsub.vx v9, v8, a0
2887; RV32I-NEXT:    vxor.vi v8, v8, -1
2888; RV32I-NEXT:    vand.vv v8, v8, v9
2889; RV32I-NEXT:    vsrl.vi v9, v8, 1
2890; RV32I-NEXT:    lui a0, 349525
2891; RV32I-NEXT:    addi a0, a0, 1365
2892; RV32I-NEXT:    vand.vx v9, v9, a0
2893; RV32I-NEXT:    vsub.vv v8, v8, v9
2894; RV32I-NEXT:    lui a0, 209715
2895; RV32I-NEXT:    addi a0, a0, 819
2896; RV32I-NEXT:    vand.vx v9, v8, a0
2897; RV32I-NEXT:    vsrl.vi v8, v8, 2
2898; RV32I-NEXT:    vand.vx v8, v8, a0
2899; RV32I-NEXT:    vadd.vv v8, v9, v8
2900; RV32I-NEXT:    vsrl.vi v9, v8, 4
2901; RV32I-NEXT:    vadd.vv v8, v8, v9
2902; RV32I-NEXT:    lui a0, 61681
2903; RV32I-NEXT:    addi a0, a0, -241
2904; RV32I-NEXT:    vand.vx v8, v8, a0
2905; RV32I-NEXT:    lui a0, 4112
2906; RV32I-NEXT:    addi a0, a0, 257
2907; RV32I-NEXT:    vmul.vx v8, v8, a0
2908; RV32I-NEXT:    vsrl.vi v8, v8, 24
2909; RV32I-NEXT:    ret
2910;
2911; RV64I-LABEL: cttz_zero_undef_nxv2i32:
2912; RV64I:       # %bb.0:
2913; RV64I-NEXT:    li a0, 1
2914; RV64I-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
2915; RV64I-NEXT:    vsub.vx v9, v8, a0
2916; RV64I-NEXT:    vxor.vi v8, v8, -1
2917; RV64I-NEXT:    vand.vv v8, v8, v9
2918; RV64I-NEXT:    vsrl.vi v9, v8, 1
2919; RV64I-NEXT:    lui a0, 349525
2920; RV64I-NEXT:    addiw a0, a0, 1365
2921; RV64I-NEXT:    vand.vx v9, v9, a0
2922; RV64I-NEXT:    vsub.vv v8, v8, v9
2923; RV64I-NEXT:    lui a0, 209715
2924; RV64I-NEXT:    addiw a0, a0, 819
2925; RV64I-NEXT:    vand.vx v9, v8, a0
2926; RV64I-NEXT:    vsrl.vi v8, v8, 2
2927; RV64I-NEXT:    vand.vx v8, v8, a0
2928; RV64I-NEXT:    vadd.vv v8, v9, v8
2929; RV64I-NEXT:    vsrl.vi v9, v8, 4
2930; RV64I-NEXT:    vadd.vv v8, v8, v9
2931; RV64I-NEXT:    lui a0, 61681
2932; RV64I-NEXT:    addiw a0, a0, -241
2933; RV64I-NEXT:    vand.vx v8, v8, a0
2934; RV64I-NEXT:    lui a0, 4112
2935; RV64I-NEXT:    addiw a0, a0, 257
2936; RV64I-NEXT:    vmul.vx v8, v8, a0
2937; RV64I-NEXT:    vsrl.vi v8, v8, 24
2938; RV64I-NEXT:    ret
2939;
2940; RV32D-LABEL: cttz_zero_undef_nxv2i32:
2941; RV32D:       # %bb.0:
2942; RV32D-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
2943; RV32D-NEXT:    vrsub.vi v9, v8, 0
2944; RV32D-NEXT:    vand.vv v8, v8, v9
2945; RV32D-NEXT:    vfwcvt.f.xu.v v10, v8
2946; RV32D-NEXT:    li a0, 52
2947; RV32D-NEXT:    vsetvli zero, zero, e64, m2, ta, mu
2948; RV32D-NEXT:    vsrl.vx v8, v10, a0
2949; RV32D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
2950; RV32D-NEXT:    vnsrl.wi v10, v8, 0
2951; RV32D-NEXT:    li a0, 1023
2952; RV32D-NEXT:    vsub.vx v8, v10, a0
2953; RV32D-NEXT:    ret
2954;
2955; RV64D-LABEL: cttz_zero_undef_nxv2i32:
2956; RV64D:       # %bb.0:
2957; RV64D-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
2958; RV64D-NEXT:    vrsub.vi v9, v8, 0
2959; RV64D-NEXT:    vand.vv v8, v8, v9
2960; RV64D-NEXT:    vfwcvt.f.xu.v v10, v8
2961; RV64D-NEXT:    li a0, 52
2962; RV64D-NEXT:    vsetvli zero, zero, e64, m2, ta, mu
2963; RV64D-NEXT:    vsrl.vx v8, v10, a0
2964; RV64D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
2965; RV64D-NEXT:    vnsrl.wi v10, v8, 0
2966; RV64D-NEXT:    li a0, 1023
2967; RV64D-NEXT:    vsub.vx v8, v10, a0
2968; RV64D-NEXT:    ret
2969  %a = call <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 true)
2970  ret <vscale x 2 x i32> %a
2971}
2972
2973define <vscale x 4 x i32> @cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
2974; RV32I-LABEL: cttz_zero_undef_nxv4i32:
2975; RV32I:       # %bb.0:
2976; RV32I-NEXT:    li a0, 1
2977; RV32I-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
2978; RV32I-NEXT:    vsub.vx v10, v8, a0
2979; RV32I-NEXT:    vxor.vi v8, v8, -1
2980; RV32I-NEXT:    vand.vv v8, v8, v10
2981; RV32I-NEXT:    vsrl.vi v10, v8, 1
2982; RV32I-NEXT:    lui a0, 349525
2983; RV32I-NEXT:    addi a0, a0, 1365
2984; RV32I-NEXT:    vand.vx v10, v10, a0
2985; RV32I-NEXT:    vsub.vv v8, v8, v10
2986; RV32I-NEXT:    lui a0, 209715
2987; RV32I-NEXT:    addi a0, a0, 819
2988; RV32I-NEXT:    vand.vx v10, v8, a0
2989; RV32I-NEXT:    vsrl.vi v8, v8, 2
2990; RV32I-NEXT:    vand.vx v8, v8, a0
2991; RV32I-NEXT:    vadd.vv v8, v10, v8
2992; RV32I-NEXT:    vsrl.vi v10, v8, 4
2993; RV32I-NEXT:    vadd.vv v8, v8, v10
2994; RV32I-NEXT:    lui a0, 61681
2995; RV32I-NEXT:    addi a0, a0, -241
2996; RV32I-NEXT:    vand.vx v8, v8, a0
2997; RV32I-NEXT:    lui a0, 4112
2998; RV32I-NEXT:    addi a0, a0, 257
2999; RV32I-NEXT:    vmul.vx v8, v8, a0
3000; RV32I-NEXT:    vsrl.vi v8, v8, 24
3001; RV32I-NEXT:    ret
3002;
3003; RV64I-LABEL: cttz_zero_undef_nxv4i32:
3004; RV64I:       # %bb.0:
3005; RV64I-NEXT:    li a0, 1
3006; RV64I-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
3007; RV64I-NEXT:    vsub.vx v10, v8, a0
3008; RV64I-NEXT:    vxor.vi v8, v8, -1
3009; RV64I-NEXT:    vand.vv v8, v8, v10
3010; RV64I-NEXT:    vsrl.vi v10, v8, 1
3011; RV64I-NEXT:    lui a0, 349525
3012; RV64I-NEXT:    addiw a0, a0, 1365
3013; RV64I-NEXT:    vand.vx v10, v10, a0
3014; RV64I-NEXT:    vsub.vv v8, v8, v10
3015; RV64I-NEXT:    lui a0, 209715
3016; RV64I-NEXT:    addiw a0, a0, 819
3017; RV64I-NEXT:    vand.vx v10, v8, a0
3018; RV64I-NEXT:    vsrl.vi v8, v8, 2
3019; RV64I-NEXT:    vand.vx v8, v8, a0
3020; RV64I-NEXT:    vadd.vv v8, v10, v8
3021; RV64I-NEXT:    vsrl.vi v10, v8, 4
3022; RV64I-NEXT:    vadd.vv v8, v8, v10
3023; RV64I-NEXT:    lui a0, 61681
3024; RV64I-NEXT:    addiw a0, a0, -241
3025; RV64I-NEXT:    vand.vx v8, v8, a0
3026; RV64I-NEXT:    lui a0, 4112
3027; RV64I-NEXT:    addiw a0, a0, 257
3028; RV64I-NEXT:    vmul.vx v8, v8, a0
3029; RV64I-NEXT:    vsrl.vi v8, v8, 24
3030; RV64I-NEXT:    ret
3031;
3032; RV32D-LABEL: cttz_zero_undef_nxv4i32:
3033; RV32D:       # %bb.0:
3034; RV32D-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
3035; RV32D-NEXT:    vrsub.vi v10, v8, 0
3036; RV32D-NEXT:    vand.vv v8, v8, v10
3037; RV32D-NEXT:    vfwcvt.f.xu.v v12, v8
3038; RV32D-NEXT:    li a0, 52
3039; RV32D-NEXT:    vsetvli zero, zero, e64, m4, ta, mu
3040; RV32D-NEXT:    vsrl.vx v8, v12, a0
3041; RV32D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
3042; RV32D-NEXT:    vnsrl.wi v12, v8, 0
3043; RV32D-NEXT:    li a0, 1023
3044; RV32D-NEXT:    vsub.vx v8, v12, a0
3045; RV32D-NEXT:    ret
3046;
3047; RV64D-LABEL: cttz_zero_undef_nxv4i32:
3048; RV64D:       # %bb.0:
3049; RV64D-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
3050; RV64D-NEXT:    vrsub.vi v10, v8, 0
3051; RV64D-NEXT:    vand.vv v8, v8, v10
3052; RV64D-NEXT:    vfwcvt.f.xu.v v12, v8
3053; RV64D-NEXT:    li a0, 52
3054; RV64D-NEXT:    vsetvli zero, zero, e64, m4, ta, mu
3055; RV64D-NEXT:    vsrl.vx v8, v12, a0
3056; RV64D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
3057; RV64D-NEXT:    vnsrl.wi v12, v8, 0
3058; RV64D-NEXT:    li a0, 1023
3059; RV64D-NEXT:    vsub.vx v8, v12, a0
3060; RV64D-NEXT:    ret
3061  %a = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 true)
3062  ret <vscale x 4 x i32> %a
3063}
3064
3065define <vscale x 8 x i32> @cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
3066; RV32I-LABEL: cttz_zero_undef_nxv8i32:
3067; RV32I:       # %bb.0:
3068; RV32I-NEXT:    li a0, 1
3069; RV32I-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
3070; RV32I-NEXT:    vsub.vx v12, v8, a0
3071; RV32I-NEXT:    vxor.vi v8, v8, -1
3072; RV32I-NEXT:    vand.vv v8, v8, v12
3073; RV32I-NEXT:    vsrl.vi v12, v8, 1
3074; RV32I-NEXT:    lui a0, 349525
3075; RV32I-NEXT:    addi a0, a0, 1365
3076; RV32I-NEXT:    vand.vx v12, v12, a0
3077; RV32I-NEXT:    vsub.vv v8, v8, v12
3078; RV32I-NEXT:    lui a0, 209715
3079; RV32I-NEXT:    addi a0, a0, 819
3080; RV32I-NEXT:    vand.vx v12, v8, a0
3081; RV32I-NEXT:    vsrl.vi v8, v8, 2
3082; RV32I-NEXT:    vand.vx v8, v8, a0
3083; RV32I-NEXT:    vadd.vv v8, v12, v8
3084; RV32I-NEXT:    vsrl.vi v12, v8, 4
3085; RV32I-NEXT:    vadd.vv v8, v8, v12
3086; RV32I-NEXT:    lui a0, 61681
3087; RV32I-NEXT:    addi a0, a0, -241
3088; RV32I-NEXT:    vand.vx v8, v8, a0
3089; RV32I-NEXT:    lui a0, 4112
3090; RV32I-NEXT:    addi a0, a0, 257
3091; RV32I-NEXT:    vmul.vx v8, v8, a0
3092; RV32I-NEXT:    vsrl.vi v8, v8, 24
3093; RV32I-NEXT:    ret
3094;
3095; RV64I-LABEL: cttz_zero_undef_nxv8i32:
3096; RV64I:       # %bb.0:
3097; RV64I-NEXT:    li a0, 1
3098; RV64I-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
3099; RV64I-NEXT:    vsub.vx v12, v8, a0
3100; RV64I-NEXT:    vxor.vi v8, v8, -1
3101; RV64I-NEXT:    vand.vv v8, v8, v12
3102; RV64I-NEXT:    vsrl.vi v12, v8, 1
3103; RV64I-NEXT:    lui a0, 349525
3104; RV64I-NEXT:    addiw a0, a0, 1365
3105; RV64I-NEXT:    vand.vx v12, v12, a0
3106; RV64I-NEXT:    vsub.vv v8, v8, v12
3107; RV64I-NEXT:    lui a0, 209715
3108; RV64I-NEXT:    addiw a0, a0, 819
3109; RV64I-NEXT:    vand.vx v12, v8, a0
3110; RV64I-NEXT:    vsrl.vi v8, v8, 2
3111; RV64I-NEXT:    vand.vx v8, v8, a0
3112; RV64I-NEXT:    vadd.vv v8, v12, v8
3113; RV64I-NEXT:    vsrl.vi v12, v8, 4
3114; RV64I-NEXT:    vadd.vv v8, v8, v12
3115; RV64I-NEXT:    lui a0, 61681
3116; RV64I-NEXT:    addiw a0, a0, -241
3117; RV64I-NEXT:    vand.vx v8, v8, a0
3118; RV64I-NEXT:    lui a0, 4112
3119; RV64I-NEXT:    addiw a0, a0, 257
3120; RV64I-NEXT:    vmul.vx v8, v8, a0
3121; RV64I-NEXT:    vsrl.vi v8, v8, 24
3122; RV64I-NEXT:    ret
3123;
3124; RV32D-LABEL: cttz_zero_undef_nxv8i32:
3125; RV32D:       # %bb.0:
3126; RV32D-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
3127; RV32D-NEXT:    vrsub.vi v12, v8, 0
3128; RV32D-NEXT:    vand.vv v8, v8, v12
3129; RV32D-NEXT:    vfwcvt.f.xu.v v16, v8
3130; RV32D-NEXT:    li a0, 52
3131; RV32D-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
3132; RV32D-NEXT:    vsrl.vx v8, v16, a0
3133; RV32D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
3134; RV32D-NEXT:    vnsrl.wi v16, v8, 0
3135; RV32D-NEXT:    li a0, 1023
3136; RV32D-NEXT:    vsub.vx v8, v16, a0
3137; RV32D-NEXT:    ret
3138;
3139; RV64D-LABEL: cttz_zero_undef_nxv8i32:
3140; RV64D:       # %bb.0:
3141; RV64D-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
3142; RV64D-NEXT:    vrsub.vi v12, v8, 0
3143; RV64D-NEXT:    vand.vv v8, v8, v12
3144; RV64D-NEXT:    vfwcvt.f.xu.v v16, v8
3145; RV64D-NEXT:    li a0, 52
3146; RV64D-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
3147; RV64D-NEXT:    vsrl.vx v8, v16, a0
3148; RV64D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
3149; RV64D-NEXT:    vnsrl.wi v16, v8, 0
3150; RV64D-NEXT:    li a0, 1023
3151; RV64D-NEXT:    vsub.vx v8, v16, a0
3152; RV64D-NEXT:    ret
3153  %a = call <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 true)
3154  ret <vscale x 8 x i32> %a
3155}
3156
3157define <vscale x 16 x i32> @cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) {
3158; RV32-LABEL: cttz_zero_undef_nxv16i32:
3159; RV32:       # %bb.0:
3160; RV32-NEXT:    li a0, 1
3161; RV32-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
3162; RV32-NEXT:    vsub.vx v16, v8, a0
3163; RV32-NEXT:    vxor.vi v8, v8, -1
3164; RV32-NEXT:    vand.vv v8, v8, v16
3165; RV32-NEXT:    vsrl.vi v16, v8, 1
3166; RV32-NEXT:    lui a0, 349525
3167; RV32-NEXT:    addi a0, a0, 1365
3168; RV32-NEXT:    vand.vx v16, v16, a0
3169; RV32-NEXT:    vsub.vv v8, v8, v16
3170; RV32-NEXT:    lui a0, 209715
3171; RV32-NEXT:    addi a0, a0, 819
3172; RV32-NEXT:    vand.vx v16, v8, a0
3173; RV32-NEXT:    vsrl.vi v8, v8, 2
3174; RV32-NEXT:    vand.vx v8, v8, a0
3175; RV32-NEXT:    vadd.vv v8, v16, v8
3176; RV32-NEXT:    vsrl.vi v16, v8, 4
3177; RV32-NEXT:    vadd.vv v8, v8, v16
3178; RV32-NEXT:    lui a0, 61681
3179; RV32-NEXT:    addi a0, a0, -241
3180; RV32-NEXT:    vand.vx v8, v8, a0
3181; RV32-NEXT:    lui a0, 4112
3182; RV32-NEXT:    addi a0, a0, 257
3183; RV32-NEXT:    vmul.vx v8, v8, a0
3184; RV32-NEXT:    vsrl.vi v8, v8, 24
3185; RV32-NEXT:    ret
3186;
3187; RV64-LABEL: cttz_zero_undef_nxv16i32:
3188; RV64:       # %bb.0:
3189; RV64-NEXT:    li a0, 1
3190; RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
3191; RV64-NEXT:    vsub.vx v16, v8, a0
3192; RV64-NEXT:    vxor.vi v8, v8, -1
3193; RV64-NEXT:    vand.vv v8, v8, v16
3194; RV64-NEXT:    vsrl.vi v16, v8, 1
3195; RV64-NEXT:    lui a0, 349525
3196; RV64-NEXT:    addiw a0, a0, 1365
3197; RV64-NEXT:    vand.vx v16, v16, a0
3198; RV64-NEXT:    vsub.vv v8, v8, v16
3199; RV64-NEXT:    lui a0, 209715
3200; RV64-NEXT:    addiw a0, a0, 819
3201; RV64-NEXT:    vand.vx v16, v8, a0
3202; RV64-NEXT:    vsrl.vi v8, v8, 2
3203; RV64-NEXT:    vand.vx v8, v8, a0
3204; RV64-NEXT:    vadd.vv v8, v16, v8
3205; RV64-NEXT:    vsrl.vi v16, v8, 4
3206; RV64-NEXT:    vadd.vv v8, v8, v16
3207; RV64-NEXT:    lui a0, 61681
3208; RV64-NEXT:    addiw a0, a0, -241
3209; RV64-NEXT:    vand.vx v8, v8, a0
3210; RV64-NEXT:    lui a0, 4112
3211; RV64-NEXT:    addiw a0, a0, 257
3212; RV64-NEXT:    vmul.vx v8, v8, a0
3213; RV64-NEXT:    vsrl.vi v8, v8, 24
3214; RV64-NEXT:    ret
3215  %a = call <vscale x 16 x i32> @llvm.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 true)
3216  ret <vscale x 16 x i32> %a
3217}
3218
3219define <vscale x 1 x i64> @cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
3220; RV32-LABEL: cttz_zero_undef_nxv1i64:
3221; RV32:       # %bb.0:
3222; RV32-NEXT:    addi sp, sp, -16
3223; RV32-NEXT:    .cfi_def_cfa_offset 16
3224; RV32-NEXT:    lui a0, 349525
3225; RV32-NEXT:    addi a0, a0, 1365
3226; RV32-NEXT:    sw a0, 12(sp)
3227; RV32-NEXT:    sw a0, 8(sp)
3228; RV32-NEXT:    lui a0, 209715
3229; RV32-NEXT:    addi a0, a0, 819
3230; RV32-NEXT:    sw a0, 12(sp)
3231; RV32-NEXT:    sw a0, 8(sp)
3232; RV32-NEXT:    lui a0, 61681
3233; RV32-NEXT:    addi a0, a0, -241
3234; RV32-NEXT:    sw a0, 12(sp)
3235; RV32-NEXT:    sw a0, 8(sp)
3236; RV32-NEXT:    lui a0, 4112
3237; RV32-NEXT:    addi a0, a0, 257
3238; RV32-NEXT:    sw a0, 12(sp)
3239; RV32-NEXT:    sw a0, 8(sp)
3240; RV32-NEXT:    li a0, 1
3241; RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
3242; RV32-NEXT:    vsub.vx v9, v8, a0
3243; RV32-NEXT:    vxor.vi v8, v8, -1
3244; RV32-NEXT:    addi a0, sp, 8
3245; RV32-NEXT:    vlse64.v v10, (a0), zero
3246; RV32-NEXT:    vand.vv v8, v8, v9
3247; RV32-NEXT:    addi a0, sp, 8
3248; RV32-NEXT:    vlse64.v v9, (a0), zero
3249; RV32-NEXT:    vsrl.vi v11, v8, 1
3250; RV32-NEXT:    vand.vv v10, v11, v10
3251; RV32-NEXT:    vsub.vv v8, v8, v10
3252; RV32-NEXT:    vand.vv v10, v8, v9
3253; RV32-NEXT:    vsrl.vi v8, v8, 2
3254; RV32-NEXT:    vand.vv v8, v8, v9
3255; RV32-NEXT:    vadd.vv v8, v10, v8
3256; RV32-NEXT:    addi a0, sp, 8
3257; RV32-NEXT:    vlse64.v v9, (a0), zero
3258; RV32-NEXT:    addi a0, sp, 8
3259; RV32-NEXT:    vlse64.v v10, (a0), zero
3260; RV32-NEXT:    vsrl.vi v11, v8, 4
3261; RV32-NEXT:    vadd.vv v8, v8, v11
3262; RV32-NEXT:    vand.vv v8, v8, v9
3263; RV32-NEXT:    vmul.vv v8, v8, v10
3264; RV32-NEXT:    li a0, 56
3265; RV32-NEXT:    vsrl.vx v8, v8, a0
3266; RV32-NEXT:    addi sp, sp, 16
3267; RV32-NEXT:    ret
3268;
3269; RV64-LABEL: cttz_zero_undef_nxv1i64:
3270; RV64:       # %bb.0:
3271; RV64-NEXT:    li a0, 1
3272; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
3273; RV64-NEXT:    vsub.vx v9, v8, a0
3274; RV64-NEXT:    vxor.vi v8, v8, -1
3275; RV64-NEXT:    vand.vv v8, v8, v9
3276; RV64-NEXT:    lui a0, %hi(.LCPI40_0)
3277; RV64-NEXT:    ld a0, %lo(.LCPI40_0)(a0)
3278; RV64-NEXT:    lui a1, %hi(.LCPI40_1)
3279; RV64-NEXT:    ld a1, %lo(.LCPI40_1)(a1)
3280; RV64-NEXT:    vsrl.vi v9, v8, 1
3281; RV64-NEXT:    vand.vx v9, v9, a0
3282; RV64-NEXT:    vsub.vv v8, v8, v9
3283; RV64-NEXT:    vand.vx v9, v8, a1
3284; RV64-NEXT:    vsrl.vi v8, v8, 2
3285; RV64-NEXT:    vand.vx v8, v8, a1
3286; RV64-NEXT:    vadd.vv v8, v9, v8
3287; RV64-NEXT:    lui a0, %hi(.LCPI40_2)
3288; RV64-NEXT:    ld a0, %lo(.LCPI40_2)(a0)
3289; RV64-NEXT:    lui a1, %hi(.LCPI40_3)
3290; RV64-NEXT:    ld a1, %lo(.LCPI40_3)(a1)
3291; RV64-NEXT:    vsrl.vi v9, v8, 4
3292; RV64-NEXT:    vadd.vv v8, v8, v9
3293; RV64-NEXT:    vand.vx v8, v8, a0
3294; RV64-NEXT:    vmul.vx v8, v8, a1
3295; RV64-NEXT:    li a0, 56
3296; RV64-NEXT:    vsrl.vx v8, v8, a0
3297; RV64-NEXT:    ret
3298  %a = call <vscale x 1 x i64> @llvm.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 true)
3299  ret <vscale x 1 x i64> %a
3300}
3301
3302define <vscale x 2 x i64> @cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
3303; RV32-LABEL: cttz_zero_undef_nxv2i64:
3304; RV32:       # %bb.0:
3305; RV32-NEXT:    addi sp, sp, -16
3306; RV32-NEXT:    .cfi_def_cfa_offset 16
3307; RV32-NEXT:    lui a0, 349525
3308; RV32-NEXT:    addi a0, a0, 1365
3309; RV32-NEXT:    sw a0, 12(sp)
3310; RV32-NEXT:    sw a0, 8(sp)
3311; RV32-NEXT:    lui a0, 209715
3312; RV32-NEXT:    addi a0, a0, 819
3313; RV32-NEXT:    sw a0, 12(sp)
3314; RV32-NEXT:    sw a0, 8(sp)
3315; RV32-NEXT:    lui a0, 61681
3316; RV32-NEXT:    addi a0, a0, -241
3317; RV32-NEXT:    sw a0, 12(sp)
3318; RV32-NEXT:    sw a0, 8(sp)
3319; RV32-NEXT:    lui a0, 4112
3320; RV32-NEXT:    addi a0, a0, 257
3321; RV32-NEXT:    sw a0, 12(sp)
3322; RV32-NEXT:    sw a0, 8(sp)
3323; RV32-NEXT:    li a0, 1
3324; RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
3325; RV32-NEXT:    vsub.vx v10, v8, a0
3326; RV32-NEXT:    vxor.vi v8, v8, -1
3327; RV32-NEXT:    addi a0, sp, 8
3328; RV32-NEXT:    vlse64.v v12, (a0), zero
3329; RV32-NEXT:    vand.vv v8, v8, v10
3330; RV32-NEXT:    addi a0, sp, 8
3331; RV32-NEXT:    vlse64.v v10, (a0), zero
3332; RV32-NEXT:    vsrl.vi v14, v8, 1
3333; RV32-NEXT:    vand.vv v12, v14, v12
3334; RV32-NEXT:    vsub.vv v8, v8, v12
3335; RV32-NEXT:    vand.vv v12, v8, v10
3336; RV32-NEXT:    vsrl.vi v8, v8, 2
3337; RV32-NEXT:    vand.vv v8, v8, v10
3338; RV32-NEXT:    vadd.vv v8, v12, v8
3339; RV32-NEXT:    addi a0, sp, 8
3340; RV32-NEXT:    vlse64.v v10, (a0), zero
3341; RV32-NEXT:    addi a0, sp, 8
3342; RV32-NEXT:    vlse64.v v12, (a0), zero
3343; RV32-NEXT:    vsrl.vi v14, v8, 4
3344; RV32-NEXT:    vadd.vv v8, v8, v14
3345; RV32-NEXT:    vand.vv v8, v8, v10
3346; RV32-NEXT:    vmul.vv v8, v8, v12
3347; RV32-NEXT:    li a0, 56
3348; RV32-NEXT:    vsrl.vx v8, v8, a0
3349; RV32-NEXT:    addi sp, sp, 16
3350; RV32-NEXT:    ret
3351;
3352; RV64-LABEL: cttz_zero_undef_nxv2i64:
3353; RV64:       # %bb.0:
3354; RV64-NEXT:    li a0, 1
3355; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
3356; RV64-NEXT:    vsub.vx v10, v8, a0
3357; RV64-NEXT:    vxor.vi v8, v8, -1
3358; RV64-NEXT:    vand.vv v8, v8, v10
3359; RV64-NEXT:    lui a0, %hi(.LCPI41_0)
3360; RV64-NEXT:    ld a0, %lo(.LCPI41_0)(a0)
3361; RV64-NEXT:    lui a1, %hi(.LCPI41_1)
3362; RV64-NEXT:    ld a1, %lo(.LCPI41_1)(a1)
3363; RV64-NEXT:    vsrl.vi v10, v8, 1
3364; RV64-NEXT:    vand.vx v10, v10, a0
3365; RV64-NEXT:    vsub.vv v8, v8, v10
3366; RV64-NEXT:    vand.vx v10, v8, a1
3367; RV64-NEXT:    vsrl.vi v8, v8, 2
3368; RV64-NEXT:    vand.vx v8, v8, a1
3369; RV64-NEXT:    vadd.vv v8, v10, v8
3370; RV64-NEXT:    lui a0, %hi(.LCPI41_2)
3371; RV64-NEXT:    ld a0, %lo(.LCPI41_2)(a0)
3372; RV64-NEXT:    lui a1, %hi(.LCPI41_3)
3373; RV64-NEXT:    ld a1, %lo(.LCPI41_3)(a1)
3374; RV64-NEXT:    vsrl.vi v10, v8, 4
3375; RV64-NEXT:    vadd.vv v8, v8, v10
3376; RV64-NEXT:    vand.vx v8, v8, a0
3377; RV64-NEXT:    vmul.vx v8, v8, a1
3378; RV64-NEXT:    li a0, 56
3379; RV64-NEXT:    vsrl.vx v8, v8, a0
3380; RV64-NEXT:    ret
3381  %a = call <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 true)
3382  ret <vscale x 2 x i64> %a
3383}
3384
3385define <vscale x 4 x i64> @cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
3386; RV32-LABEL: cttz_zero_undef_nxv4i64:
3387; RV32:       # %bb.0:
3388; RV32-NEXT:    addi sp, sp, -16
3389; RV32-NEXT:    .cfi_def_cfa_offset 16
3390; RV32-NEXT:    lui a0, 349525
3391; RV32-NEXT:    addi a0, a0, 1365
3392; RV32-NEXT:    sw a0, 12(sp)
3393; RV32-NEXT:    sw a0, 8(sp)
3394; RV32-NEXT:    lui a0, 209715
3395; RV32-NEXT:    addi a0, a0, 819
3396; RV32-NEXT:    sw a0, 12(sp)
3397; RV32-NEXT:    sw a0, 8(sp)
3398; RV32-NEXT:    lui a0, 61681
3399; RV32-NEXT:    addi a0, a0, -241
3400; RV32-NEXT:    sw a0, 12(sp)
3401; RV32-NEXT:    sw a0, 8(sp)
3402; RV32-NEXT:    lui a0, 4112
3403; RV32-NEXT:    addi a0, a0, 257
3404; RV32-NEXT:    sw a0, 12(sp)
3405; RV32-NEXT:    sw a0, 8(sp)
3406; RV32-NEXT:    li a0, 1
3407; RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
3408; RV32-NEXT:    vsub.vx v12, v8, a0
3409; RV32-NEXT:    vxor.vi v8, v8, -1
3410; RV32-NEXT:    addi a0, sp, 8
3411; RV32-NEXT:    vlse64.v v16, (a0), zero
3412; RV32-NEXT:    vand.vv v8, v8, v12
3413; RV32-NEXT:    addi a0, sp, 8
3414; RV32-NEXT:    vlse64.v v12, (a0), zero
3415; RV32-NEXT:    vsrl.vi v20, v8, 1
3416; RV32-NEXT:    vand.vv v16, v20, v16
3417; RV32-NEXT:    vsub.vv v8, v8, v16
3418; RV32-NEXT:    vand.vv v16, v8, v12
3419; RV32-NEXT:    vsrl.vi v8, v8, 2
3420; RV32-NEXT:    vand.vv v8, v8, v12
3421; RV32-NEXT:    vadd.vv v8, v16, v8
3422; RV32-NEXT:    addi a0, sp, 8
3423; RV32-NEXT:    vlse64.v v12, (a0), zero
3424; RV32-NEXT:    addi a0, sp, 8
3425; RV32-NEXT:    vlse64.v v16, (a0), zero
3426; RV32-NEXT:    vsrl.vi v20, v8, 4
3427; RV32-NEXT:    vadd.vv v8, v8, v20
3428; RV32-NEXT:    vand.vv v8, v8, v12
3429; RV32-NEXT:    vmul.vv v8, v8, v16
3430; RV32-NEXT:    li a0, 56
3431; RV32-NEXT:    vsrl.vx v8, v8, a0
3432; RV32-NEXT:    addi sp, sp, 16
3433; RV32-NEXT:    ret
3434;
3435; RV64-LABEL: cttz_zero_undef_nxv4i64:
3436; RV64:       # %bb.0:
3437; RV64-NEXT:    li a0, 1
3438; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
3439; RV64-NEXT:    vsub.vx v12, v8, a0
3440; RV64-NEXT:    vxor.vi v8, v8, -1
3441; RV64-NEXT:    vand.vv v8, v8, v12
3442; RV64-NEXT:    lui a0, %hi(.LCPI42_0)
3443; RV64-NEXT:    ld a0, %lo(.LCPI42_0)(a0)
3444; RV64-NEXT:    lui a1, %hi(.LCPI42_1)
3445; RV64-NEXT:    ld a1, %lo(.LCPI42_1)(a1)
3446; RV64-NEXT:    vsrl.vi v12, v8, 1
3447; RV64-NEXT:    vand.vx v12, v12, a0
3448; RV64-NEXT:    vsub.vv v8, v8, v12
3449; RV64-NEXT:    vand.vx v12, v8, a1
3450; RV64-NEXT:    vsrl.vi v8, v8, 2
3451; RV64-NEXT:    vand.vx v8, v8, a1
3452; RV64-NEXT:    vadd.vv v8, v12, v8
3453; RV64-NEXT:    lui a0, %hi(.LCPI42_2)
3454; RV64-NEXT:    ld a0, %lo(.LCPI42_2)(a0)
3455; RV64-NEXT:    lui a1, %hi(.LCPI42_3)
3456; RV64-NEXT:    ld a1, %lo(.LCPI42_3)(a1)
3457; RV64-NEXT:    vsrl.vi v12, v8, 4
3458; RV64-NEXT:    vadd.vv v8, v8, v12
3459; RV64-NEXT:    vand.vx v8, v8, a0
3460; RV64-NEXT:    vmul.vx v8, v8, a1
3461; RV64-NEXT:    li a0, 56
3462; RV64-NEXT:    vsrl.vx v8, v8, a0
3463; RV64-NEXT:    ret
3464  %a = call <vscale x 4 x i64> @llvm.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 true)
3465  ret <vscale x 4 x i64> %a
3466}
3467
3468define <vscale x 8 x i64> @cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
3469; RV32-LABEL: cttz_zero_undef_nxv8i64:
3470; RV32:       # %bb.0:
3471; RV32-NEXT:    addi sp, sp, -16
3472; RV32-NEXT:    .cfi_def_cfa_offset 16
3473; RV32-NEXT:    lui a0, 349525
3474; RV32-NEXT:    addi a0, a0, 1365
3475; RV32-NEXT:    sw a0, 12(sp)
3476; RV32-NEXT:    sw a0, 8(sp)
3477; RV32-NEXT:    lui a0, 209715
3478; RV32-NEXT:    addi a0, a0, 819
3479; RV32-NEXT:    sw a0, 12(sp)
3480; RV32-NEXT:    sw a0, 8(sp)
3481; RV32-NEXT:    lui a0, 61681
3482; RV32-NEXT:    addi a0, a0, -241
3483; RV32-NEXT:    sw a0, 12(sp)
3484; RV32-NEXT:    sw a0, 8(sp)
3485; RV32-NEXT:    lui a0, 4112
3486; RV32-NEXT:    addi a0, a0, 257
3487; RV32-NEXT:    sw a0, 12(sp)
3488; RV32-NEXT:    sw a0, 8(sp)
3489; RV32-NEXT:    li a0, 1
3490; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
3491; RV32-NEXT:    vsub.vx v16, v8, a0
3492; RV32-NEXT:    vxor.vi v8, v8, -1
3493; RV32-NEXT:    addi a0, sp, 8
3494; RV32-NEXT:    vlse64.v v24, (a0), zero
3495; RV32-NEXT:    vand.vv v8, v8, v16
3496; RV32-NEXT:    addi a0, sp, 8
3497; RV32-NEXT:    vlse64.v v16, (a0), zero
3498; RV32-NEXT:    vsrl.vi v0, v8, 1
3499; RV32-NEXT:    vand.vv v24, v0, v24
3500; RV32-NEXT:    vsub.vv v8, v8, v24
3501; RV32-NEXT:    vand.vv v24, v8, v16
3502; RV32-NEXT:    vsrl.vi v8, v8, 2
3503; RV32-NEXT:    vand.vv v8, v8, v16
3504; RV32-NEXT:    vadd.vv v8, v24, v8
3505; RV32-NEXT:    addi a0, sp, 8
3506; RV32-NEXT:    vlse64.v v16, (a0), zero
3507; RV32-NEXT:    addi a0, sp, 8
3508; RV32-NEXT:    vlse64.v v24, (a0), zero
3509; RV32-NEXT:    vsrl.vi v0, v8, 4
3510; RV32-NEXT:    vadd.vv v8, v8, v0
3511; RV32-NEXT:    vand.vv v8, v8, v16
3512; RV32-NEXT:    vmul.vv v8, v8, v24
3513; RV32-NEXT:    li a0, 56
3514; RV32-NEXT:    vsrl.vx v8, v8, a0
3515; RV32-NEXT:    addi sp, sp, 16
3516; RV32-NEXT:    ret
3517;
3518; RV64-LABEL: cttz_zero_undef_nxv8i64:
3519; RV64:       # %bb.0:
3520; RV64-NEXT:    li a0, 1
3521; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
3522; RV64-NEXT:    vsub.vx v16, v8, a0
3523; RV64-NEXT:    vxor.vi v8, v8, -1
3524; RV64-NEXT:    vand.vv v8, v8, v16
3525; RV64-NEXT:    lui a0, %hi(.LCPI43_0)
3526; RV64-NEXT:    ld a0, %lo(.LCPI43_0)(a0)
3527; RV64-NEXT:    lui a1, %hi(.LCPI43_1)
3528; RV64-NEXT:    ld a1, %lo(.LCPI43_1)(a1)
3529; RV64-NEXT:    vsrl.vi v16, v8, 1
3530; RV64-NEXT:    vand.vx v16, v16, a0
3531; RV64-NEXT:    vsub.vv v8, v8, v16
3532; RV64-NEXT:    vand.vx v16, v8, a1
3533; RV64-NEXT:    vsrl.vi v8, v8, 2
3534; RV64-NEXT:    vand.vx v8, v8, a1
3535; RV64-NEXT:    vadd.vv v8, v16, v8
3536; RV64-NEXT:    lui a0, %hi(.LCPI43_2)
3537; RV64-NEXT:    ld a0, %lo(.LCPI43_2)(a0)
3538; RV64-NEXT:    lui a1, %hi(.LCPI43_3)
3539; RV64-NEXT:    ld a1, %lo(.LCPI43_3)(a1)
3540; RV64-NEXT:    vsrl.vi v16, v8, 4
3541; RV64-NEXT:    vadd.vv v8, v8, v16
3542; RV64-NEXT:    vand.vx v8, v8, a0
3543; RV64-NEXT:    vmul.vx v8, v8, a1
3544; RV64-NEXT:    li a0, 56
3545; RV64-NEXT:    vsrl.vx v8, v8, a0
3546; RV64-NEXT:    ret
3547  %a = call <vscale x 8 x i64> @llvm.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 true)
3548  ret <vscale x 8 x i64> %a
3549}
3550