1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
3; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
4
5define <vscale x 1 x i8> @cttz_nxv1i8(<vscale x 1 x i8> %va) {
6; CHECK-LABEL: cttz_nxv1i8:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    addi a0, zero, 1
9; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
10; CHECK-NEXT:    vsub.vx v9, v8, a0
11; CHECK-NEXT:    vxor.vi v8, v8, -1
12; CHECK-NEXT:    vand.vv v8, v8, v9
13; CHECK-NEXT:    vsrl.vi v9, v8, 1
14; CHECK-NEXT:    addi a0, zero, 85
15; CHECK-NEXT:    vand.vx v9, v9, a0
16; CHECK-NEXT:    vsub.vv v8, v8, v9
17; CHECK-NEXT:    addi a0, zero, 51
18; CHECK-NEXT:    vand.vx v9, v8, a0
19; CHECK-NEXT:    vsrl.vi v8, v8, 2
20; CHECK-NEXT:    vand.vx v8, v8, a0
21; CHECK-NEXT:    vadd.vv v8, v9, v8
22; CHECK-NEXT:    vsrl.vi v9, v8, 4
23; CHECK-NEXT:    vadd.vv v8, v8, v9
24; CHECK-NEXT:    vand.vi v8, v8, 15
25; CHECK-NEXT:    ret
26  %a = call <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 false)
27  ret <vscale x 1 x i8> %a
28}
29declare <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8>, i1)
30
31define <vscale x 2 x i8> @cttz_nxv2i8(<vscale x 2 x i8> %va) {
32; CHECK-LABEL: cttz_nxv2i8:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    addi a0, zero, 1
35; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
36; CHECK-NEXT:    vsub.vx v9, v8, a0
37; CHECK-NEXT:    vxor.vi v8, v8, -1
38; CHECK-NEXT:    vand.vv v8, v8, v9
39; CHECK-NEXT:    vsrl.vi v9, v8, 1
40; CHECK-NEXT:    addi a0, zero, 85
41; CHECK-NEXT:    vand.vx v9, v9, a0
42; CHECK-NEXT:    vsub.vv v8, v8, v9
43; CHECK-NEXT:    addi a0, zero, 51
44; CHECK-NEXT:    vand.vx v9, v8, a0
45; CHECK-NEXT:    vsrl.vi v8, v8, 2
46; CHECK-NEXT:    vand.vx v8, v8, a0
47; CHECK-NEXT:    vadd.vv v8, v9, v8
48; CHECK-NEXT:    vsrl.vi v9, v8, 4
49; CHECK-NEXT:    vadd.vv v8, v8, v9
50; CHECK-NEXT:    vand.vi v8, v8, 15
51; CHECK-NEXT:    ret
52  %a = call <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 false)
53  ret <vscale x 2 x i8> %a
54}
55declare <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8>, i1)
56
57define <vscale x 4 x i8> @cttz_nxv4i8(<vscale x 4 x i8> %va) {
58; CHECK-LABEL: cttz_nxv4i8:
59; CHECK:       # %bb.0:
60; CHECK-NEXT:    addi a0, zero, 1
61; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
62; CHECK-NEXT:    vsub.vx v9, v8, a0
63; CHECK-NEXT:    vxor.vi v8, v8, -1
64; CHECK-NEXT:    vand.vv v8, v8, v9
65; CHECK-NEXT:    vsrl.vi v9, v8, 1
66; CHECK-NEXT:    addi a0, zero, 85
67; CHECK-NEXT:    vand.vx v9, v9, a0
68; CHECK-NEXT:    vsub.vv v8, v8, v9
69; CHECK-NEXT:    addi a0, zero, 51
70; CHECK-NEXT:    vand.vx v9, v8, a0
71; CHECK-NEXT:    vsrl.vi v8, v8, 2
72; CHECK-NEXT:    vand.vx v8, v8, a0
73; CHECK-NEXT:    vadd.vv v8, v9, v8
74; CHECK-NEXT:    vsrl.vi v9, v8, 4
75; CHECK-NEXT:    vadd.vv v8, v8, v9
76; CHECK-NEXT:    vand.vi v8, v8, 15
77; CHECK-NEXT:    ret
78  %a = call <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 false)
79  ret <vscale x 4 x i8> %a
80}
81declare <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8>, i1)
82
83define <vscale x 8 x i8> @cttz_nxv8i8(<vscale x 8 x i8> %va) {
84; CHECK-LABEL: cttz_nxv8i8:
85; CHECK:       # %bb.0:
86; CHECK-NEXT:    addi a0, zero, 1
87; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
88; CHECK-NEXT:    vsub.vx v9, v8, a0
89; CHECK-NEXT:    vxor.vi v8, v8, -1
90; CHECK-NEXT:    vand.vv v8, v8, v9
91; CHECK-NEXT:    vsrl.vi v9, v8, 1
92; CHECK-NEXT:    addi a0, zero, 85
93; CHECK-NEXT:    vand.vx v9, v9, a0
94; CHECK-NEXT:    vsub.vv v8, v8, v9
95; CHECK-NEXT:    addi a0, zero, 51
96; CHECK-NEXT:    vand.vx v9, v8, a0
97; CHECK-NEXT:    vsrl.vi v8, v8, 2
98; CHECK-NEXT:    vand.vx v8, v8, a0
99; CHECK-NEXT:    vadd.vv v8, v9, v8
100; CHECK-NEXT:    vsrl.vi v9, v8, 4
101; CHECK-NEXT:    vadd.vv v8, v8, v9
102; CHECK-NEXT:    vand.vi v8, v8, 15
103; CHECK-NEXT:    ret
104  %a = call <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 false)
105  ret <vscale x 8 x i8> %a
106}
107declare <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8>, i1)
108
109define <vscale x 16 x i8> @cttz_nxv16i8(<vscale x 16 x i8> %va) {
110; CHECK-LABEL: cttz_nxv16i8:
111; CHECK:       # %bb.0:
112; CHECK-NEXT:    addi a0, zero, 1
113; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
114; CHECK-NEXT:    vsub.vx v10, v8, a0
115; CHECK-NEXT:    vxor.vi v8, v8, -1
116; CHECK-NEXT:    vand.vv v8, v8, v10
117; CHECK-NEXT:    vsrl.vi v10, v8, 1
118; CHECK-NEXT:    addi a0, zero, 85
119; CHECK-NEXT:    vand.vx v10, v10, a0
120; CHECK-NEXT:    vsub.vv v8, v8, v10
121; CHECK-NEXT:    addi a0, zero, 51
122; CHECK-NEXT:    vand.vx v10, v8, a0
123; CHECK-NEXT:    vsrl.vi v8, v8, 2
124; CHECK-NEXT:    vand.vx v8, v8, a0
125; CHECK-NEXT:    vadd.vv v8, v10, v8
126; CHECK-NEXT:    vsrl.vi v10, v8, 4
127; CHECK-NEXT:    vadd.vv v8, v8, v10
128; CHECK-NEXT:    vand.vi v8, v8, 15
129; CHECK-NEXT:    ret
130  %a = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 false)
131  ret <vscale x 16 x i8> %a
132}
133declare <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8>, i1)
134
135define <vscale x 32 x i8> @cttz_nxv32i8(<vscale x 32 x i8> %va) {
136; CHECK-LABEL: cttz_nxv32i8:
137; CHECK:       # %bb.0:
138; CHECK-NEXT:    addi a0, zero, 1
139; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
140; CHECK-NEXT:    vsub.vx v12, v8, a0
141; CHECK-NEXT:    vxor.vi v8, v8, -1
142; CHECK-NEXT:    vand.vv v8, v8, v12
143; CHECK-NEXT:    vsrl.vi v12, v8, 1
144; CHECK-NEXT:    addi a0, zero, 85
145; CHECK-NEXT:    vand.vx v12, v12, a0
146; CHECK-NEXT:    vsub.vv v8, v8, v12
147; CHECK-NEXT:    addi a0, zero, 51
148; CHECK-NEXT:    vand.vx v12, v8, a0
149; CHECK-NEXT:    vsrl.vi v8, v8, 2
150; CHECK-NEXT:    vand.vx v8, v8, a0
151; CHECK-NEXT:    vadd.vv v8, v12, v8
152; CHECK-NEXT:    vsrl.vi v12, v8, 4
153; CHECK-NEXT:    vadd.vv v8, v8, v12
154; CHECK-NEXT:    vand.vi v8, v8, 15
155; CHECK-NEXT:    ret
156  %a = call <vscale x 32 x i8> @llvm.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 false)
157  ret <vscale x 32 x i8> %a
158}
159declare <vscale x 32 x i8> @llvm.cttz.nxv32i8(<vscale x 32 x i8>, i1)
160
161define <vscale x 64 x i8> @cttz_nxv64i8(<vscale x 64 x i8> %va) {
162; CHECK-LABEL: cttz_nxv64i8:
163; CHECK:       # %bb.0:
164; CHECK-NEXT:    addi a0, zero, 1
165; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
166; CHECK-NEXT:    vsub.vx v16, v8, a0
167; CHECK-NEXT:    vxor.vi v8, v8, -1
168; CHECK-NEXT:    vand.vv v8, v8, v16
169; CHECK-NEXT:    vsrl.vi v16, v8, 1
170; CHECK-NEXT:    addi a0, zero, 85
171; CHECK-NEXT:    vand.vx v16, v16, a0
172; CHECK-NEXT:    vsub.vv v8, v8, v16
173; CHECK-NEXT:    addi a0, zero, 51
174; CHECK-NEXT:    vand.vx v16, v8, a0
175; CHECK-NEXT:    vsrl.vi v8, v8, 2
176; CHECK-NEXT:    vand.vx v8, v8, a0
177; CHECK-NEXT:    vadd.vv v8, v16, v8
178; CHECK-NEXT:    vsrl.vi v16, v8, 4
179; CHECK-NEXT:    vadd.vv v8, v8, v16
180; CHECK-NEXT:    vand.vi v8, v8, 15
181; CHECK-NEXT:    ret
182  %a = call <vscale x 64 x i8> @llvm.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 false)
183  ret <vscale x 64 x i8> %a
184}
185declare <vscale x 64 x i8> @llvm.cttz.nxv64i8(<vscale x 64 x i8>, i1)
186
187define <vscale x 1 x i16> @cttz_nxv1i16(<vscale x 1 x i16> %va) {
188; RV32-LABEL: cttz_nxv1i16:
189; RV32:       # %bb.0:
190; RV32-NEXT:    addi a0, zero, 1
191; RV32-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
192; RV32-NEXT:    vsub.vx v9, v8, a0
193; RV32-NEXT:    vxor.vi v8, v8, -1
194; RV32-NEXT:    vand.vv v8, v8, v9
195; RV32-NEXT:    vsrl.vi v9, v8, 1
196; RV32-NEXT:    lui a0, 5
197; RV32-NEXT:    addi a0, a0, 1365
198; RV32-NEXT:    vand.vx v9, v9, a0
199; RV32-NEXT:    vsub.vv v8, v8, v9
200; RV32-NEXT:    lui a0, 3
201; RV32-NEXT:    addi a0, a0, 819
202; RV32-NEXT:    vand.vx v9, v8, a0
203; RV32-NEXT:    vsrl.vi v8, v8, 2
204; RV32-NEXT:    vand.vx v8, v8, a0
205; RV32-NEXT:    vadd.vv v8, v9, v8
206; RV32-NEXT:    vsrl.vi v9, v8, 4
207; RV32-NEXT:    vadd.vv v8, v8, v9
208; RV32-NEXT:    lui a0, 1
209; RV32-NEXT:    addi a0, a0, -241
210; RV32-NEXT:    vand.vx v8, v8, a0
211; RV32-NEXT:    addi a0, zero, 257
212; RV32-NEXT:    vmul.vx v8, v8, a0
213; RV32-NEXT:    vsrl.vi v8, v8, 8
214; RV32-NEXT:    ret
215;
216; RV64-LABEL: cttz_nxv1i16:
217; RV64:       # %bb.0:
218; RV64-NEXT:    addi a0, zero, 1
219; RV64-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
220; RV64-NEXT:    vsub.vx v9, v8, a0
221; RV64-NEXT:    vxor.vi v8, v8, -1
222; RV64-NEXT:    vand.vv v8, v8, v9
223; RV64-NEXT:    vsrl.vi v9, v8, 1
224; RV64-NEXT:    lui a0, 5
225; RV64-NEXT:    addiw a0, a0, 1365
226; RV64-NEXT:    vand.vx v9, v9, a0
227; RV64-NEXT:    vsub.vv v8, v8, v9
228; RV64-NEXT:    lui a0, 3
229; RV64-NEXT:    addiw a0, a0, 819
230; RV64-NEXT:    vand.vx v9, v8, a0
231; RV64-NEXT:    vsrl.vi v8, v8, 2
232; RV64-NEXT:    vand.vx v8, v8, a0
233; RV64-NEXT:    vadd.vv v8, v9, v8
234; RV64-NEXT:    vsrl.vi v9, v8, 4
235; RV64-NEXT:    vadd.vv v8, v8, v9
236; RV64-NEXT:    lui a0, 1
237; RV64-NEXT:    addiw a0, a0, -241
238; RV64-NEXT:    vand.vx v8, v8, a0
239; RV64-NEXT:    addi a0, zero, 257
240; RV64-NEXT:    vmul.vx v8, v8, a0
241; RV64-NEXT:    vsrl.vi v8, v8, 8
242; RV64-NEXT:    ret
243  %a = call <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 false)
244  ret <vscale x 1 x i16> %a
245}
246declare <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16>, i1)
247
248define <vscale x 2 x i16> @cttz_nxv2i16(<vscale x 2 x i16> %va) {
249; RV32-LABEL: cttz_nxv2i16:
250; RV32:       # %bb.0:
251; RV32-NEXT:    addi a0, zero, 1
252; RV32-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
253; RV32-NEXT:    vsub.vx v9, v8, a0
254; RV32-NEXT:    vxor.vi v8, v8, -1
255; RV32-NEXT:    vand.vv v8, v8, v9
256; RV32-NEXT:    vsrl.vi v9, v8, 1
257; RV32-NEXT:    lui a0, 5
258; RV32-NEXT:    addi a0, a0, 1365
259; RV32-NEXT:    vand.vx v9, v9, a0
260; RV32-NEXT:    vsub.vv v8, v8, v9
261; RV32-NEXT:    lui a0, 3
262; RV32-NEXT:    addi a0, a0, 819
263; RV32-NEXT:    vand.vx v9, v8, a0
264; RV32-NEXT:    vsrl.vi v8, v8, 2
265; RV32-NEXT:    vand.vx v8, v8, a0
266; RV32-NEXT:    vadd.vv v8, v9, v8
267; RV32-NEXT:    vsrl.vi v9, v8, 4
268; RV32-NEXT:    vadd.vv v8, v8, v9
269; RV32-NEXT:    lui a0, 1
270; RV32-NEXT:    addi a0, a0, -241
271; RV32-NEXT:    vand.vx v8, v8, a0
272; RV32-NEXT:    addi a0, zero, 257
273; RV32-NEXT:    vmul.vx v8, v8, a0
274; RV32-NEXT:    vsrl.vi v8, v8, 8
275; RV32-NEXT:    ret
276;
277; RV64-LABEL: cttz_nxv2i16:
278; RV64:       # %bb.0:
279; RV64-NEXT:    addi a0, zero, 1
280; RV64-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
281; RV64-NEXT:    vsub.vx v9, v8, a0
282; RV64-NEXT:    vxor.vi v8, v8, -1
283; RV64-NEXT:    vand.vv v8, v8, v9
284; RV64-NEXT:    vsrl.vi v9, v8, 1
285; RV64-NEXT:    lui a0, 5
286; RV64-NEXT:    addiw a0, a0, 1365
287; RV64-NEXT:    vand.vx v9, v9, a0
288; RV64-NEXT:    vsub.vv v8, v8, v9
289; RV64-NEXT:    lui a0, 3
290; RV64-NEXT:    addiw a0, a0, 819
291; RV64-NEXT:    vand.vx v9, v8, a0
292; RV64-NEXT:    vsrl.vi v8, v8, 2
293; RV64-NEXT:    vand.vx v8, v8, a0
294; RV64-NEXT:    vadd.vv v8, v9, v8
295; RV64-NEXT:    vsrl.vi v9, v8, 4
296; RV64-NEXT:    vadd.vv v8, v8, v9
297; RV64-NEXT:    lui a0, 1
298; RV64-NEXT:    addiw a0, a0, -241
299; RV64-NEXT:    vand.vx v8, v8, a0
300; RV64-NEXT:    addi a0, zero, 257
301; RV64-NEXT:    vmul.vx v8, v8, a0
302; RV64-NEXT:    vsrl.vi v8, v8, 8
303; RV64-NEXT:    ret
304  %a = call <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 false)
305  ret <vscale x 2 x i16> %a
306}
307declare <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16>, i1)
308
309define <vscale x 4 x i16> @cttz_nxv4i16(<vscale x 4 x i16> %va) {
310; RV32-LABEL: cttz_nxv4i16:
311; RV32:       # %bb.0:
312; RV32-NEXT:    addi a0, zero, 1
313; RV32-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
314; RV32-NEXT:    vsub.vx v9, v8, a0
315; RV32-NEXT:    vxor.vi v8, v8, -1
316; RV32-NEXT:    vand.vv v8, v8, v9
317; RV32-NEXT:    vsrl.vi v9, v8, 1
318; RV32-NEXT:    lui a0, 5
319; RV32-NEXT:    addi a0, a0, 1365
320; RV32-NEXT:    vand.vx v9, v9, a0
321; RV32-NEXT:    vsub.vv v8, v8, v9
322; RV32-NEXT:    lui a0, 3
323; RV32-NEXT:    addi a0, a0, 819
324; RV32-NEXT:    vand.vx v9, v8, a0
325; RV32-NEXT:    vsrl.vi v8, v8, 2
326; RV32-NEXT:    vand.vx v8, v8, a0
327; RV32-NEXT:    vadd.vv v8, v9, v8
328; RV32-NEXT:    vsrl.vi v9, v8, 4
329; RV32-NEXT:    vadd.vv v8, v8, v9
330; RV32-NEXT:    lui a0, 1
331; RV32-NEXT:    addi a0, a0, -241
332; RV32-NEXT:    vand.vx v8, v8, a0
333; RV32-NEXT:    addi a0, zero, 257
334; RV32-NEXT:    vmul.vx v8, v8, a0
335; RV32-NEXT:    vsrl.vi v8, v8, 8
336; RV32-NEXT:    ret
337;
338; RV64-LABEL: cttz_nxv4i16:
339; RV64:       # %bb.0:
340; RV64-NEXT:    addi a0, zero, 1
341; RV64-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
342; RV64-NEXT:    vsub.vx v9, v8, a0
343; RV64-NEXT:    vxor.vi v8, v8, -1
344; RV64-NEXT:    vand.vv v8, v8, v9
345; RV64-NEXT:    vsrl.vi v9, v8, 1
346; RV64-NEXT:    lui a0, 5
347; RV64-NEXT:    addiw a0, a0, 1365
348; RV64-NEXT:    vand.vx v9, v9, a0
349; RV64-NEXT:    vsub.vv v8, v8, v9
350; RV64-NEXT:    lui a0, 3
351; RV64-NEXT:    addiw a0, a0, 819
352; RV64-NEXT:    vand.vx v9, v8, a0
353; RV64-NEXT:    vsrl.vi v8, v8, 2
354; RV64-NEXT:    vand.vx v8, v8, a0
355; RV64-NEXT:    vadd.vv v8, v9, v8
356; RV64-NEXT:    vsrl.vi v9, v8, 4
357; RV64-NEXT:    vadd.vv v8, v8, v9
358; RV64-NEXT:    lui a0, 1
359; RV64-NEXT:    addiw a0, a0, -241
360; RV64-NEXT:    vand.vx v8, v8, a0
361; RV64-NEXT:    addi a0, zero, 257
362; RV64-NEXT:    vmul.vx v8, v8, a0
363; RV64-NEXT:    vsrl.vi v8, v8, 8
364; RV64-NEXT:    ret
365  %a = call <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 false)
366  ret <vscale x 4 x i16> %a
367}
368declare <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16>, i1)
369
370define <vscale x 8 x i16> @cttz_nxv8i16(<vscale x 8 x i16> %va) {
371; RV32-LABEL: cttz_nxv8i16:
372; RV32:       # %bb.0:
373; RV32-NEXT:    addi a0, zero, 1
374; RV32-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
375; RV32-NEXT:    vsub.vx v10, v8, a0
376; RV32-NEXT:    vxor.vi v8, v8, -1
377; RV32-NEXT:    vand.vv v8, v8, v10
378; RV32-NEXT:    vsrl.vi v10, v8, 1
379; RV32-NEXT:    lui a0, 5
380; RV32-NEXT:    addi a0, a0, 1365
381; RV32-NEXT:    vand.vx v10, v10, a0
382; RV32-NEXT:    vsub.vv v8, v8, v10
383; RV32-NEXT:    lui a0, 3
384; RV32-NEXT:    addi a0, a0, 819
385; RV32-NEXT:    vand.vx v10, v8, a0
386; RV32-NEXT:    vsrl.vi v8, v8, 2
387; RV32-NEXT:    vand.vx v8, v8, a0
388; RV32-NEXT:    vadd.vv v8, v10, v8
389; RV32-NEXT:    vsrl.vi v10, v8, 4
390; RV32-NEXT:    vadd.vv v8, v8, v10
391; RV32-NEXT:    lui a0, 1
392; RV32-NEXT:    addi a0, a0, -241
393; RV32-NEXT:    vand.vx v8, v8, a0
394; RV32-NEXT:    addi a0, zero, 257
395; RV32-NEXT:    vmul.vx v8, v8, a0
396; RV32-NEXT:    vsrl.vi v8, v8, 8
397; RV32-NEXT:    ret
398;
399; RV64-LABEL: cttz_nxv8i16:
400; RV64:       # %bb.0:
401; RV64-NEXT:    addi a0, zero, 1
402; RV64-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
403; RV64-NEXT:    vsub.vx v10, v8, a0
404; RV64-NEXT:    vxor.vi v8, v8, -1
405; RV64-NEXT:    vand.vv v8, v8, v10
406; RV64-NEXT:    vsrl.vi v10, v8, 1
407; RV64-NEXT:    lui a0, 5
408; RV64-NEXT:    addiw a0, a0, 1365
409; RV64-NEXT:    vand.vx v10, v10, a0
410; RV64-NEXT:    vsub.vv v8, v8, v10
411; RV64-NEXT:    lui a0, 3
412; RV64-NEXT:    addiw a0, a0, 819
413; RV64-NEXT:    vand.vx v10, v8, a0
414; RV64-NEXT:    vsrl.vi v8, v8, 2
415; RV64-NEXT:    vand.vx v8, v8, a0
416; RV64-NEXT:    vadd.vv v8, v10, v8
417; RV64-NEXT:    vsrl.vi v10, v8, 4
418; RV64-NEXT:    vadd.vv v8, v8, v10
419; RV64-NEXT:    lui a0, 1
420; RV64-NEXT:    addiw a0, a0, -241
421; RV64-NEXT:    vand.vx v8, v8, a0
422; RV64-NEXT:    addi a0, zero, 257
423; RV64-NEXT:    vmul.vx v8, v8, a0
424; RV64-NEXT:    vsrl.vi v8, v8, 8
425; RV64-NEXT:    ret
426  %a = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 false)
427  ret <vscale x 8 x i16> %a
428}
429declare <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16>, i1)
430
431define <vscale x 16 x i16> @cttz_nxv16i16(<vscale x 16 x i16> %va) {
432; RV32-LABEL: cttz_nxv16i16:
433; RV32:       # %bb.0:
434; RV32-NEXT:    addi a0, zero, 1
435; RV32-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
436; RV32-NEXT:    vsub.vx v12, v8, a0
437; RV32-NEXT:    vxor.vi v8, v8, -1
438; RV32-NEXT:    vand.vv v8, v8, v12
439; RV32-NEXT:    vsrl.vi v12, v8, 1
440; RV32-NEXT:    lui a0, 5
441; RV32-NEXT:    addi a0, a0, 1365
442; RV32-NEXT:    vand.vx v12, v12, a0
443; RV32-NEXT:    vsub.vv v8, v8, v12
444; RV32-NEXT:    lui a0, 3
445; RV32-NEXT:    addi a0, a0, 819
446; RV32-NEXT:    vand.vx v12, v8, a0
447; RV32-NEXT:    vsrl.vi v8, v8, 2
448; RV32-NEXT:    vand.vx v8, v8, a0
449; RV32-NEXT:    vadd.vv v8, v12, v8
450; RV32-NEXT:    vsrl.vi v12, v8, 4
451; RV32-NEXT:    vadd.vv v8, v8, v12
452; RV32-NEXT:    lui a0, 1
453; RV32-NEXT:    addi a0, a0, -241
454; RV32-NEXT:    vand.vx v8, v8, a0
455; RV32-NEXT:    addi a0, zero, 257
456; RV32-NEXT:    vmul.vx v8, v8, a0
457; RV32-NEXT:    vsrl.vi v8, v8, 8
458; RV32-NEXT:    ret
459;
460; RV64-LABEL: cttz_nxv16i16:
461; RV64:       # %bb.0:
462; RV64-NEXT:    addi a0, zero, 1
463; RV64-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
464; RV64-NEXT:    vsub.vx v12, v8, a0
465; RV64-NEXT:    vxor.vi v8, v8, -1
466; RV64-NEXT:    vand.vv v8, v8, v12
467; RV64-NEXT:    vsrl.vi v12, v8, 1
468; RV64-NEXT:    lui a0, 5
469; RV64-NEXT:    addiw a0, a0, 1365
470; RV64-NEXT:    vand.vx v12, v12, a0
471; RV64-NEXT:    vsub.vv v8, v8, v12
472; RV64-NEXT:    lui a0, 3
473; RV64-NEXT:    addiw a0, a0, 819
474; RV64-NEXT:    vand.vx v12, v8, a0
475; RV64-NEXT:    vsrl.vi v8, v8, 2
476; RV64-NEXT:    vand.vx v8, v8, a0
477; RV64-NEXT:    vadd.vv v8, v12, v8
478; RV64-NEXT:    vsrl.vi v12, v8, 4
479; RV64-NEXT:    vadd.vv v8, v8, v12
480; RV64-NEXT:    lui a0, 1
481; RV64-NEXT:    addiw a0, a0, -241
482; RV64-NEXT:    vand.vx v8, v8, a0
483; RV64-NEXT:    addi a0, zero, 257
484; RV64-NEXT:    vmul.vx v8, v8, a0
485; RV64-NEXT:    vsrl.vi v8, v8, 8
486; RV64-NEXT:    ret
487  %a = call <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 false)
488  ret <vscale x 16 x i16> %a
489}
490declare <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16>, i1)
491
492define <vscale x 32 x i16> @cttz_nxv32i16(<vscale x 32 x i16> %va) {
493; RV32-LABEL: cttz_nxv32i16:
494; RV32:       # %bb.0:
495; RV32-NEXT:    addi a0, zero, 1
496; RV32-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
497; RV32-NEXT:    vsub.vx v16, v8, a0
498; RV32-NEXT:    vxor.vi v8, v8, -1
499; RV32-NEXT:    vand.vv v8, v8, v16
500; RV32-NEXT:    vsrl.vi v16, v8, 1
501; RV32-NEXT:    lui a0, 5
502; RV32-NEXT:    addi a0, a0, 1365
503; RV32-NEXT:    vand.vx v16, v16, a0
504; RV32-NEXT:    vsub.vv v8, v8, v16
505; RV32-NEXT:    lui a0, 3
506; RV32-NEXT:    addi a0, a0, 819
507; RV32-NEXT:    vand.vx v16, v8, a0
508; RV32-NEXT:    vsrl.vi v8, v8, 2
509; RV32-NEXT:    vand.vx v8, v8, a0
510; RV32-NEXT:    vadd.vv v8, v16, v8
511; RV32-NEXT:    vsrl.vi v16, v8, 4
512; RV32-NEXT:    vadd.vv v8, v8, v16
513; RV32-NEXT:    lui a0, 1
514; RV32-NEXT:    addi a0, a0, -241
515; RV32-NEXT:    vand.vx v8, v8, a0
516; RV32-NEXT:    addi a0, zero, 257
517; RV32-NEXT:    vmul.vx v8, v8, a0
518; RV32-NEXT:    vsrl.vi v8, v8, 8
519; RV32-NEXT:    ret
520;
521; RV64-LABEL: cttz_nxv32i16:
522; RV64:       # %bb.0:
523; RV64-NEXT:    addi a0, zero, 1
524; RV64-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
525; RV64-NEXT:    vsub.vx v16, v8, a0
526; RV64-NEXT:    vxor.vi v8, v8, -1
527; RV64-NEXT:    vand.vv v8, v8, v16
528; RV64-NEXT:    vsrl.vi v16, v8, 1
529; RV64-NEXT:    lui a0, 5
530; RV64-NEXT:    addiw a0, a0, 1365
531; RV64-NEXT:    vand.vx v16, v16, a0
532; RV64-NEXT:    vsub.vv v8, v8, v16
533; RV64-NEXT:    lui a0, 3
534; RV64-NEXT:    addiw a0, a0, 819
535; RV64-NEXT:    vand.vx v16, v8, a0
536; RV64-NEXT:    vsrl.vi v8, v8, 2
537; RV64-NEXT:    vand.vx v8, v8, a0
538; RV64-NEXT:    vadd.vv v8, v16, v8
539; RV64-NEXT:    vsrl.vi v16, v8, 4
540; RV64-NEXT:    vadd.vv v8, v8, v16
541; RV64-NEXT:    lui a0, 1
542; RV64-NEXT:    addiw a0, a0, -241
543; RV64-NEXT:    vand.vx v8, v8, a0
544; RV64-NEXT:    addi a0, zero, 257
545; RV64-NEXT:    vmul.vx v8, v8, a0
546; RV64-NEXT:    vsrl.vi v8, v8, 8
547; RV64-NEXT:    ret
548  %a = call <vscale x 32 x i16> @llvm.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 false)
549  ret <vscale x 32 x i16> %a
550}
551declare <vscale x 32 x i16> @llvm.cttz.nxv32i16(<vscale x 32 x i16>, i1)
552
553define <vscale x 1 x i32> @cttz_nxv1i32(<vscale x 1 x i32> %va) {
554; RV32-LABEL: cttz_nxv1i32:
555; RV32:       # %bb.0:
556; RV32-NEXT:    addi a0, zero, 1
557; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
558; RV32-NEXT:    vsub.vx v9, v8, a0
559; RV32-NEXT:    vxor.vi v8, v8, -1
560; RV32-NEXT:    vand.vv v8, v8, v9
561; RV32-NEXT:    vsrl.vi v9, v8, 1
562; RV32-NEXT:    lui a0, 349525
563; RV32-NEXT:    addi a0, a0, 1365
564; RV32-NEXT:    vand.vx v9, v9, a0
565; RV32-NEXT:    vsub.vv v8, v8, v9
566; RV32-NEXT:    lui a0, 209715
567; RV32-NEXT:    addi a0, a0, 819
568; RV32-NEXT:    vand.vx v9, v8, a0
569; RV32-NEXT:    vsrl.vi v8, v8, 2
570; RV32-NEXT:    vand.vx v8, v8, a0
571; RV32-NEXT:    vadd.vv v8, v9, v8
572; RV32-NEXT:    vsrl.vi v9, v8, 4
573; RV32-NEXT:    vadd.vv v8, v8, v9
574; RV32-NEXT:    lui a0, 61681
575; RV32-NEXT:    addi a0, a0, -241
576; RV32-NEXT:    vand.vx v8, v8, a0
577; RV32-NEXT:    lui a0, 4112
578; RV32-NEXT:    addi a0, a0, 257
579; RV32-NEXT:    vmul.vx v8, v8, a0
580; RV32-NEXT:    vsrl.vi v8, v8, 24
581; RV32-NEXT:    ret
582;
583; RV64-LABEL: cttz_nxv1i32:
584; RV64:       # %bb.0:
585; RV64-NEXT:    addi a0, zero, 1
586; RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
587; RV64-NEXT:    vsub.vx v9, v8, a0
588; RV64-NEXT:    vxor.vi v8, v8, -1
589; RV64-NEXT:    vand.vv v8, v8, v9
590; RV64-NEXT:    vsrl.vi v9, v8, 1
591; RV64-NEXT:    lui a0, 349525
592; RV64-NEXT:    addiw a0, a0, 1365
593; RV64-NEXT:    vand.vx v9, v9, a0
594; RV64-NEXT:    vsub.vv v8, v8, v9
595; RV64-NEXT:    lui a0, 209715
596; RV64-NEXT:    addiw a0, a0, 819
597; RV64-NEXT:    vand.vx v9, v8, a0
598; RV64-NEXT:    vsrl.vi v8, v8, 2
599; RV64-NEXT:    vand.vx v8, v8, a0
600; RV64-NEXT:    vadd.vv v8, v9, v8
601; RV64-NEXT:    vsrl.vi v9, v8, 4
602; RV64-NEXT:    vadd.vv v8, v8, v9
603; RV64-NEXT:    lui a0, 61681
604; RV64-NEXT:    addiw a0, a0, -241
605; RV64-NEXT:    vand.vx v8, v8, a0
606; RV64-NEXT:    lui a0, 4112
607; RV64-NEXT:    addiw a0, a0, 257
608; RV64-NEXT:    vmul.vx v8, v8, a0
609; RV64-NEXT:    vsrl.vi v8, v8, 24
610; RV64-NEXT:    ret
611  %a = call <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 false)
612  ret <vscale x 1 x i32> %a
613}
614declare <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32>, i1)
615
616define <vscale x 2 x i32> @cttz_nxv2i32(<vscale x 2 x i32> %va) {
617; RV32-LABEL: cttz_nxv2i32:
618; RV32:       # %bb.0:
619; RV32-NEXT:    addi a0, zero, 1
620; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
621; RV32-NEXT:    vsub.vx v9, v8, a0
622; RV32-NEXT:    vxor.vi v8, v8, -1
623; RV32-NEXT:    vand.vv v8, v8, v9
624; RV32-NEXT:    vsrl.vi v9, v8, 1
625; RV32-NEXT:    lui a0, 349525
626; RV32-NEXT:    addi a0, a0, 1365
627; RV32-NEXT:    vand.vx v9, v9, a0
628; RV32-NEXT:    vsub.vv v8, v8, v9
629; RV32-NEXT:    lui a0, 209715
630; RV32-NEXT:    addi a0, a0, 819
631; RV32-NEXT:    vand.vx v9, v8, a0
632; RV32-NEXT:    vsrl.vi v8, v8, 2
633; RV32-NEXT:    vand.vx v8, v8, a0
634; RV32-NEXT:    vadd.vv v8, v9, v8
635; RV32-NEXT:    vsrl.vi v9, v8, 4
636; RV32-NEXT:    vadd.vv v8, v8, v9
637; RV32-NEXT:    lui a0, 61681
638; RV32-NEXT:    addi a0, a0, -241
639; RV32-NEXT:    vand.vx v8, v8, a0
640; RV32-NEXT:    lui a0, 4112
641; RV32-NEXT:    addi a0, a0, 257
642; RV32-NEXT:    vmul.vx v8, v8, a0
643; RV32-NEXT:    vsrl.vi v8, v8, 24
644; RV32-NEXT:    ret
645;
646; RV64-LABEL: cttz_nxv2i32:
647; RV64:       # %bb.0:
648; RV64-NEXT:    addi a0, zero, 1
649; RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
650; RV64-NEXT:    vsub.vx v9, v8, a0
651; RV64-NEXT:    vxor.vi v8, v8, -1
652; RV64-NEXT:    vand.vv v8, v8, v9
653; RV64-NEXT:    vsrl.vi v9, v8, 1
654; RV64-NEXT:    lui a0, 349525
655; RV64-NEXT:    addiw a0, a0, 1365
656; RV64-NEXT:    vand.vx v9, v9, a0
657; RV64-NEXT:    vsub.vv v8, v8, v9
658; RV64-NEXT:    lui a0, 209715
659; RV64-NEXT:    addiw a0, a0, 819
660; RV64-NEXT:    vand.vx v9, v8, a0
661; RV64-NEXT:    vsrl.vi v8, v8, 2
662; RV64-NEXT:    vand.vx v8, v8, a0
663; RV64-NEXT:    vadd.vv v8, v9, v8
664; RV64-NEXT:    vsrl.vi v9, v8, 4
665; RV64-NEXT:    vadd.vv v8, v8, v9
666; RV64-NEXT:    lui a0, 61681
667; RV64-NEXT:    addiw a0, a0, -241
668; RV64-NEXT:    vand.vx v8, v8, a0
669; RV64-NEXT:    lui a0, 4112
670; RV64-NEXT:    addiw a0, a0, 257
671; RV64-NEXT:    vmul.vx v8, v8, a0
672; RV64-NEXT:    vsrl.vi v8, v8, 24
673; RV64-NEXT:    ret
674  %a = call <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 false)
675  ret <vscale x 2 x i32> %a
676}
677declare <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32>, i1)
678
679define <vscale x 4 x i32> @cttz_nxv4i32(<vscale x 4 x i32> %va) {
680; RV32-LABEL: cttz_nxv4i32:
681; RV32:       # %bb.0:
682; RV32-NEXT:    addi a0, zero, 1
683; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
684; RV32-NEXT:    vsub.vx v10, v8, a0
685; RV32-NEXT:    vxor.vi v8, v8, -1
686; RV32-NEXT:    vand.vv v8, v8, v10
687; RV32-NEXT:    vsrl.vi v10, v8, 1
688; RV32-NEXT:    lui a0, 349525
689; RV32-NEXT:    addi a0, a0, 1365
690; RV32-NEXT:    vand.vx v10, v10, a0
691; RV32-NEXT:    vsub.vv v8, v8, v10
692; RV32-NEXT:    lui a0, 209715
693; RV32-NEXT:    addi a0, a0, 819
694; RV32-NEXT:    vand.vx v10, v8, a0
695; RV32-NEXT:    vsrl.vi v8, v8, 2
696; RV32-NEXT:    vand.vx v8, v8, a0
697; RV32-NEXT:    vadd.vv v8, v10, v8
698; RV32-NEXT:    vsrl.vi v10, v8, 4
699; RV32-NEXT:    vadd.vv v8, v8, v10
700; RV32-NEXT:    lui a0, 61681
701; RV32-NEXT:    addi a0, a0, -241
702; RV32-NEXT:    vand.vx v8, v8, a0
703; RV32-NEXT:    lui a0, 4112
704; RV32-NEXT:    addi a0, a0, 257
705; RV32-NEXT:    vmul.vx v8, v8, a0
706; RV32-NEXT:    vsrl.vi v8, v8, 24
707; RV32-NEXT:    ret
708;
709; RV64-LABEL: cttz_nxv4i32:
710; RV64:       # %bb.0:
711; RV64-NEXT:    addi a0, zero, 1
712; RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
713; RV64-NEXT:    vsub.vx v10, v8, a0
714; RV64-NEXT:    vxor.vi v8, v8, -1
715; RV64-NEXT:    vand.vv v8, v8, v10
716; RV64-NEXT:    vsrl.vi v10, v8, 1
717; RV64-NEXT:    lui a0, 349525
718; RV64-NEXT:    addiw a0, a0, 1365
719; RV64-NEXT:    vand.vx v10, v10, a0
720; RV64-NEXT:    vsub.vv v8, v8, v10
721; RV64-NEXT:    lui a0, 209715
722; RV64-NEXT:    addiw a0, a0, 819
723; RV64-NEXT:    vand.vx v10, v8, a0
724; RV64-NEXT:    vsrl.vi v8, v8, 2
725; RV64-NEXT:    vand.vx v8, v8, a0
726; RV64-NEXT:    vadd.vv v8, v10, v8
727; RV64-NEXT:    vsrl.vi v10, v8, 4
728; RV64-NEXT:    vadd.vv v8, v8, v10
729; RV64-NEXT:    lui a0, 61681
730; RV64-NEXT:    addiw a0, a0, -241
731; RV64-NEXT:    vand.vx v8, v8, a0
732; RV64-NEXT:    lui a0, 4112
733; RV64-NEXT:    addiw a0, a0, 257
734; RV64-NEXT:    vmul.vx v8, v8, a0
735; RV64-NEXT:    vsrl.vi v8, v8, 24
736; RV64-NEXT:    ret
737  %a = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 false)
738  ret <vscale x 4 x i32> %a
739}
740declare <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32>, i1)
741
742define <vscale x 8 x i32> @cttz_nxv8i32(<vscale x 8 x i32> %va) {
743; RV32-LABEL: cttz_nxv8i32:
744; RV32:       # %bb.0:
745; RV32-NEXT:    addi a0, zero, 1
746; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
747; RV32-NEXT:    vsub.vx v12, v8, a0
748; RV32-NEXT:    vxor.vi v8, v8, -1
749; RV32-NEXT:    vand.vv v8, v8, v12
750; RV32-NEXT:    vsrl.vi v12, v8, 1
751; RV32-NEXT:    lui a0, 349525
752; RV32-NEXT:    addi a0, a0, 1365
753; RV32-NEXT:    vand.vx v12, v12, a0
754; RV32-NEXT:    vsub.vv v8, v8, v12
755; RV32-NEXT:    lui a0, 209715
756; RV32-NEXT:    addi a0, a0, 819
757; RV32-NEXT:    vand.vx v12, v8, a0
758; RV32-NEXT:    vsrl.vi v8, v8, 2
759; RV32-NEXT:    vand.vx v8, v8, a0
760; RV32-NEXT:    vadd.vv v8, v12, v8
761; RV32-NEXT:    vsrl.vi v12, v8, 4
762; RV32-NEXT:    vadd.vv v8, v8, v12
763; RV32-NEXT:    lui a0, 61681
764; RV32-NEXT:    addi a0, a0, -241
765; RV32-NEXT:    vand.vx v8, v8, a0
766; RV32-NEXT:    lui a0, 4112
767; RV32-NEXT:    addi a0, a0, 257
768; RV32-NEXT:    vmul.vx v8, v8, a0
769; RV32-NEXT:    vsrl.vi v8, v8, 24
770; RV32-NEXT:    ret
771;
772; RV64-LABEL: cttz_nxv8i32:
773; RV64:       # %bb.0:
774; RV64-NEXT:    addi a0, zero, 1
775; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
776; RV64-NEXT:    vsub.vx v12, v8, a0
777; RV64-NEXT:    vxor.vi v8, v8, -1
778; RV64-NEXT:    vand.vv v8, v8, v12
779; RV64-NEXT:    vsrl.vi v12, v8, 1
780; RV64-NEXT:    lui a0, 349525
781; RV64-NEXT:    addiw a0, a0, 1365
782; RV64-NEXT:    vand.vx v12, v12, a0
783; RV64-NEXT:    vsub.vv v8, v8, v12
784; RV64-NEXT:    lui a0, 209715
785; RV64-NEXT:    addiw a0, a0, 819
786; RV64-NEXT:    vand.vx v12, v8, a0
787; RV64-NEXT:    vsrl.vi v8, v8, 2
788; RV64-NEXT:    vand.vx v8, v8, a0
789; RV64-NEXT:    vadd.vv v8, v12, v8
790; RV64-NEXT:    vsrl.vi v12, v8, 4
791; RV64-NEXT:    vadd.vv v8, v8, v12
792; RV64-NEXT:    lui a0, 61681
793; RV64-NEXT:    addiw a0, a0, -241
794; RV64-NEXT:    vand.vx v8, v8, a0
795; RV64-NEXT:    lui a0, 4112
796; RV64-NEXT:    addiw a0, a0, 257
797; RV64-NEXT:    vmul.vx v8, v8, a0
798; RV64-NEXT:    vsrl.vi v8, v8, 24
799; RV64-NEXT:    ret
800  %a = call <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 false)
801  ret <vscale x 8 x i32> %a
802}
803declare <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32>, i1)
804
805define <vscale x 16 x i32> @cttz_nxv16i32(<vscale x 16 x i32> %va) {
806; RV32-LABEL: cttz_nxv16i32:
807; RV32:       # %bb.0:
808; RV32-NEXT:    addi a0, zero, 1
809; RV32-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
810; RV32-NEXT:    vsub.vx v16, v8, a0
811; RV32-NEXT:    vxor.vi v8, v8, -1
812; RV32-NEXT:    vand.vv v8, v8, v16
813; RV32-NEXT:    vsrl.vi v16, v8, 1
814; RV32-NEXT:    lui a0, 349525
815; RV32-NEXT:    addi a0, a0, 1365
816; RV32-NEXT:    vand.vx v16, v16, a0
817; RV32-NEXT:    vsub.vv v8, v8, v16
818; RV32-NEXT:    lui a0, 209715
819; RV32-NEXT:    addi a0, a0, 819
820; RV32-NEXT:    vand.vx v16, v8, a0
821; RV32-NEXT:    vsrl.vi v8, v8, 2
822; RV32-NEXT:    vand.vx v8, v8, a0
823; RV32-NEXT:    vadd.vv v8, v16, v8
824; RV32-NEXT:    vsrl.vi v16, v8, 4
825; RV32-NEXT:    vadd.vv v8, v8, v16
826; RV32-NEXT:    lui a0, 61681
827; RV32-NEXT:    addi a0, a0, -241
828; RV32-NEXT:    vand.vx v8, v8, a0
829; RV32-NEXT:    lui a0, 4112
830; RV32-NEXT:    addi a0, a0, 257
831; RV32-NEXT:    vmul.vx v8, v8, a0
832; RV32-NEXT:    vsrl.vi v8, v8, 24
833; RV32-NEXT:    ret
834;
835; RV64-LABEL: cttz_nxv16i32:
836; RV64:       # %bb.0:
837; RV64-NEXT:    addi a0, zero, 1
838; RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
839; RV64-NEXT:    vsub.vx v16, v8, a0
840; RV64-NEXT:    vxor.vi v8, v8, -1
841; RV64-NEXT:    vand.vv v8, v8, v16
842; RV64-NEXT:    vsrl.vi v16, v8, 1
843; RV64-NEXT:    lui a0, 349525
844; RV64-NEXT:    addiw a0, a0, 1365
845; RV64-NEXT:    vand.vx v16, v16, a0
846; RV64-NEXT:    vsub.vv v8, v8, v16
847; RV64-NEXT:    lui a0, 209715
848; RV64-NEXT:    addiw a0, a0, 819
849; RV64-NEXT:    vand.vx v16, v8, a0
850; RV64-NEXT:    vsrl.vi v8, v8, 2
851; RV64-NEXT:    vand.vx v8, v8, a0
852; RV64-NEXT:    vadd.vv v8, v16, v8
853; RV64-NEXT:    vsrl.vi v16, v8, 4
854; RV64-NEXT:    vadd.vv v8, v8, v16
855; RV64-NEXT:    lui a0, 61681
856; RV64-NEXT:    addiw a0, a0, -241
857; RV64-NEXT:    vand.vx v8, v8, a0
858; RV64-NEXT:    lui a0, 4112
859; RV64-NEXT:    addiw a0, a0, 257
860; RV64-NEXT:    vmul.vx v8, v8, a0
861; RV64-NEXT:    vsrl.vi v8, v8, 24
862; RV64-NEXT:    ret
863  %a = call <vscale x 16 x i32> @llvm.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 false)
864  ret <vscale x 16 x i32> %a
865}
866declare <vscale x 16 x i32> @llvm.cttz.nxv16i32(<vscale x 16 x i32>, i1)
867
868define <vscale x 1 x i64> @cttz_nxv1i64(<vscale x 1 x i64> %va) {
869; RV32-LABEL: cttz_nxv1i64:
870; RV32:       # %bb.0:
871; RV32-NEXT:    addi sp, sp, -16
872; RV32-NEXT:    .cfi_def_cfa_offset 16
873; RV32-NEXT:    lui a0, 349525
874; RV32-NEXT:    addi a0, a0, 1365
875; RV32-NEXT:    sw a0, 12(sp)
876; RV32-NEXT:    sw a0, 8(sp)
877; RV32-NEXT:    lui a0, 209715
878; RV32-NEXT:    addi a0, a0, 819
879; RV32-NEXT:    sw a0, 12(sp)
880; RV32-NEXT:    sw a0, 8(sp)
881; RV32-NEXT:    lui a0, 61681
882; RV32-NEXT:    addi a0, a0, -241
883; RV32-NEXT:    sw a0, 12(sp)
884; RV32-NEXT:    sw a0, 8(sp)
885; RV32-NEXT:    lui a0, 4112
886; RV32-NEXT:    addi a0, a0, 257
887; RV32-NEXT:    sw a0, 12(sp)
888; RV32-NEXT:    sw a0, 8(sp)
889; RV32-NEXT:    addi a0, zero, 1
890; RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
891; RV32-NEXT:    vsub.vx v9, v8, a0
892; RV32-NEXT:    vxor.vi v8, v8, -1
893; RV32-NEXT:    addi a0, sp, 8
894; RV32-NEXT:    vlse64.v v10, (a0), zero
895; RV32-NEXT:    vand.vv v8, v8, v9
896; RV32-NEXT:    addi a0, sp, 8
897; RV32-NEXT:    vlse64.v v9, (a0), zero
898; RV32-NEXT:    vsrl.vi v11, v8, 1
899; RV32-NEXT:    vand.vv v10, v11, v10
900; RV32-NEXT:    vsub.vv v8, v8, v10
901; RV32-NEXT:    vand.vv v10, v8, v9
902; RV32-NEXT:    vsrl.vi v8, v8, 2
903; RV32-NEXT:    vand.vv v8, v8, v9
904; RV32-NEXT:    vadd.vv v8, v10, v8
905; RV32-NEXT:    addi a0, sp, 8
906; RV32-NEXT:    vlse64.v v9, (a0), zero
907; RV32-NEXT:    addi a0, sp, 8
908; RV32-NEXT:    vlse64.v v10, (a0), zero
909; RV32-NEXT:    vsrl.vi v11, v8, 4
910; RV32-NEXT:    vadd.vv v8, v8, v11
911; RV32-NEXT:    vand.vv v8, v8, v9
912; RV32-NEXT:    vmul.vv v8, v8, v10
913; RV32-NEXT:    addi a0, zero, 56
914; RV32-NEXT:    vsrl.vx v8, v8, a0
915; RV32-NEXT:    addi sp, sp, 16
916; RV32-NEXT:    ret
917;
918; RV64-LABEL: cttz_nxv1i64:
919; RV64:       # %bb.0:
920; RV64-NEXT:    addi a0, zero, 1
921; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
922; RV64-NEXT:    vsub.vx v9, v8, a0
923; RV64-NEXT:    vxor.vi v8, v8, -1
924; RV64-NEXT:    vand.vv v8, v8, v9
925; RV64-NEXT:    vsrl.vi v9, v8, 1
926; RV64-NEXT:    lui a0, 21845
927; RV64-NEXT:    addiw a0, a0, 1365
928; RV64-NEXT:    slli a0, a0, 12
929; RV64-NEXT:    addi a0, a0, 1365
930; RV64-NEXT:    slli a0, a0, 12
931; RV64-NEXT:    addi a0, a0, 1365
932; RV64-NEXT:    slli a0, a0, 12
933; RV64-NEXT:    addi a0, a0, 1365
934; RV64-NEXT:    vand.vx v9, v9, a0
935; RV64-NEXT:    vsub.vv v8, v8, v9
936; RV64-NEXT:    lui a0, 13107
937; RV64-NEXT:    addiw a0, a0, 819
938; RV64-NEXT:    slli a0, a0, 12
939; RV64-NEXT:    addi a0, a0, 819
940; RV64-NEXT:    slli a0, a0, 12
941; RV64-NEXT:    addi a0, a0, 819
942; RV64-NEXT:    slli a0, a0, 12
943; RV64-NEXT:    addi a0, a0, 819
944; RV64-NEXT:    vand.vx v9, v8, a0
945; RV64-NEXT:    vsrl.vi v8, v8, 2
946; RV64-NEXT:    vand.vx v8, v8, a0
947; RV64-NEXT:    vadd.vv v8, v9, v8
948; RV64-NEXT:    vsrl.vi v9, v8, 4
949; RV64-NEXT:    vadd.vv v8, v8, v9
950; RV64-NEXT:    lui a0, 3855
951; RV64-NEXT:    addiw a0, a0, 241
952; RV64-NEXT:    slli a0, a0, 12
953; RV64-NEXT:    addi a0, a0, -241
954; RV64-NEXT:    slli a0, a0, 12
955; RV64-NEXT:    addi a0, a0, 241
956; RV64-NEXT:    slli a0, a0, 12
957; RV64-NEXT:    addi a0, a0, -241
958; RV64-NEXT:    vand.vx v8, v8, a0
959; RV64-NEXT:    lui a0, 4112
960; RV64-NEXT:    addiw a0, a0, 257
961; RV64-NEXT:    slli a0, a0, 16
962; RV64-NEXT:    addi a0, a0, 257
963; RV64-NEXT:    slli a0, a0, 16
964; RV64-NEXT:    addi a0, a0, 257
965; RV64-NEXT:    vmul.vx v8, v8, a0
966; RV64-NEXT:    addi a0, zero, 56
967; RV64-NEXT:    vsrl.vx v8, v8, a0
968; RV64-NEXT:    ret
969  %a = call <vscale x 1 x i64> @llvm.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 false)
970  ret <vscale x 1 x i64> %a
971}
972declare <vscale x 1 x i64> @llvm.cttz.nxv1i64(<vscale x 1 x i64>, i1)
973
974define <vscale x 2 x i64> @cttz_nxv2i64(<vscale x 2 x i64> %va) {
975; RV32-LABEL: cttz_nxv2i64:
976; RV32:       # %bb.0:
977; RV32-NEXT:    addi sp, sp, -16
978; RV32-NEXT:    .cfi_def_cfa_offset 16
979; RV32-NEXT:    lui a0, 349525
980; RV32-NEXT:    addi a0, a0, 1365
981; RV32-NEXT:    sw a0, 12(sp)
982; RV32-NEXT:    sw a0, 8(sp)
983; RV32-NEXT:    lui a0, 209715
984; RV32-NEXT:    addi a0, a0, 819
985; RV32-NEXT:    sw a0, 12(sp)
986; RV32-NEXT:    sw a0, 8(sp)
987; RV32-NEXT:    lui a0, 61681
988; RV32-NEXT:    addi a0, a0, -241
989; RV32-NEXT:    sw a0, 12(sp)
990; RV32-NEXT:    sw a0, 8(sp)
991; RV32-NEXT:    lui a0, 4112
992; RV32-NEXT:    addi a0, a0, 257
993; RV32-NEXT:    sw a0, 12(sp)
994; RV32-NEXT:    sw a0, 8(sp)
995; RV32-NEXT:    addi a0, zero, 1
996; RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
997; RV32-NEXT:    vsub.vx v10, v8, a0
998; RV32-NEXT:    vxor.vi v8, v8, -1
999; RV32-NEXT:    addi a0, sp, 8
1000; RV32-NEXT:    vlse64.v v12, (a0), zero
1001; RV32-NEXT:    vand.vv v8, v8, v10
1002; RV32-NEXT:    addi a0, sp, 8
1003; RV32-NEXT:    vlse64.v v10, (a0), zero
1004; RV32-NEXT:    vsrl.vi v14, v8, 1
1005; RV32-NEXT:    vand.vv v12, v14, v12
1006; RV32-NEXT:    vsub.vv v8, v8, v12
1007; RV32-NEXT:    vand.vv v12, v8, v10
1008; RV32-NEXT:    vsrl.vi v8, v8, 2
1009; RV32-NEXT:    vand.vv v8, v8, v10
1010; RV32-NEXT:    vadd.vv v8, v12, v8
1011; RV32-NEXT:    addi a0, sp, 8
1012; RV32-NEXT:    vlse64.v v10, (a0), zero
1013; RV32-NEXT:    addi a0, sp, 8
1014; RV32-NEXT:    vlse64.v v12, (a0), zero
1015; RV32-NEXT:    vsrl.vi v14, v8, 4
1016; RV32-NEXT:    vadd.vv v8, v8, v14
1017; RV32-NEXT:    vand.vv v8, v8, v10
1018; RV32-NEXT:    vmul.vv v8, v8, v12
1019; RV32-NEXT:    addi a0, zero, 56
1020; RV32-NEXT:    vsrl.vx v8, v8, a0
1021; RV32-NEXT:    addi sp, sp, 16
1022; RV32-NEXT:    ret
1023;
1024; RV64-LABEL: cttz_nxv2i64:
1025; RV64:       # %bb.0:
1026; RV64-NEXT:    addi a0, zero, 1
1027; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
1028; RV64-NEXT:    vsub.vx v10, v8, a0
1029; RV64-NEXT:    vxor.vi v8, v8, -1
1030; RV64-NEXT:    vand.vv v8, v8, v10
1031; RV64-NEXT:    vsrl.vi v10, v8, 1
1032; RV64-NEXT:    lui a0, 21845
1033; RV64-NEXT:    addiw a0, a0, 1365
1034; RV64-NEXT:    slli a0, a0, 12
1035; RV64-NEXT:    addi a0, a0, 1365
1036; RV64-NEXT:    slli a0, a0, 12
1037; RV64-NEXT:    addi a0, a0, 1365
1038; RV64-NEXT:    slli a0, a0, 12
1039; RV64-NEXT:    addi a0, a0, 1365
1040; RV64-NEXT:    vand.vx v10, v10, a0
1041; RV64-NEXT:    vsub.vv v8, v8, v10
1042; RV64-NEXT:    lui a0, 13107
1043; RV64-NEXT:    addiw a0, a0, 819
1044; RV64-NEXT:    slli a0, a0, 12
1045; RV64-NEXT:    addi a0, a0, 819
1046; RV64-NEXT:    slli a0, a0, 12
1047; RV64-NEXT:    addi a0, a0, 819
1048; RV64-NEXT:    slli a0, a0, 12
1049; RV64-NEXT:    addi a0, a0, 819
1050; RV64-NEXT:    vand.vx v10, v8, a0
1051; RV64-NEXT:    vsrl.vi v8, v8, 2
1052; RV64-NEXT:    vand.vx v8, v8, a0
1053; RV64-NEXT:    vadd.vv v8, v10, v8
1054; RV64-NEXT:    vsrl.vi v10, v8, 4
1055; RV64-NEXT:    vadd.vv v8, v8, v10
1056; RV64-NEXT:    lui a0, 3855
1057; RV64-NEXT:    addiw a0, a0, 241
1058; RV64-NEXT:    slli a0, a0, 12
1059; RV64-NEXT:    addi a0, a0, -241
1060; RV64-NEXT:    slli a0, a0, 12
1061; RV64-NEXT:    addi a0, a0, 241
1062; RV64-NEXT:    slli a0, a0, 12
1063; RV64-NEXT:    addi a0, a0, -241
1064; RV64-NEXT:    vand.vx v8, v8, a0
1065; RV64-NEXT:    lui a0, 4112
1066; RV64-NEXT:    addiw a0, a0, 257
1067; RV64-NEXT:    slli a0, a0, 16
1068; RV64-NEXT:    addi a0, a0, 257
1069; RV64-NEXT:    slli a0, a0, 16
1070; RV64-NEXT:    addi a0, a0, 257
1071; RV64-NEXT:    vmul.vx v8, v8, a0
1072; RV64-NEXT:    addi a0, zero, 56
1073; RV64-NEXT:    vsrl.vx v8, v8, a0
1074; RV64-NEXT:    ret
1075  %a = call <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 false)
1076  ret <vscale x 2 x i64> %a
1077}
1078declare <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64>, i1)
1079
1080define <vscale x 4 x i64> @cttz_nxv4i64(<vscale x 4 x i64> %va) {
1081; RV32-LABEL: cttz_nxv4i64:
1082; RV32:       # %bb.0:
1083; RV32-NEXT:    addi sp, sp, -16
1084; RV32-NEXT:    .cfi_def_cfa_offset 16
1085; RV32-NEXT:    lui a0, 349525
1086; RV32-NEXT:    addi a0, a0, 1365
1087; RV32-NEXT:    sw a0, 12(sp)
1088; RV32-NEXT:    sw a0, 8(sp)
1089; RV32-NEXT:    lui a0, 209715
1090; RV32-NEXT:    addi a0, a0, 819
1091; RV32-NEXT:    sw a0, 12(sp)
1092; RV32-NEXT:    sw a0, 8(sp)
1093; RV32-NEXT:    lui a0, 61681
1094; RV32-NEXT:    addi a0, a0, -241
1095; RV32-NEXT:    sw a0, 12(sp)
1096; RV32-NEXT:    sw a0, 8(sp)
1097; RV32-NEXT:    lui a0, 4112
1098; RV32-NEXT:    addi a0, a0, 257
1099; RV32-NEXT:    sw a0, 12(sp)
1100; RV32-NEXT:    sw a0, 8(sp)
1101; RV32-NEXT:    addi a0, zero, 1
1102; RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1103; RV32-NEXT:    vsub.vx v12, v8, a0
1104; RV32-NEXT:    vxor.vi v8, v8, -1
1105; RV32-NEXT:    addi a0, sp, 8
1106; RV32-NEXT:    vlse64.v v16, (a0), zero
1107; RV32-NEXT:    vand.vv v8, v8, v12
1108; RV32-NEXT:    addi a0, sp, 8
1109; RV32-NEXT:    vlse64.v v12, (a0), zero
1110; RV32-NEXT:    vsrl.vi v20, v8, 1
1111; RV32-NEXT:    vand.vv v16, v20, v16
1112; RV32-NEXT:    vsub.vv v8, v8, v16
1113; RV32-NEXT:    vand.vv v16, v8, v12
1114; RV32-NEXT:    vsrl.vi v8, v8, 2
1115; RV32-NEXT:    vand.vv v8, v8, v12
1116; RV32-NEXT:    vadd.vv v8, v16, v8
1117; RV32-NEXT:    addi a0, sp, 8
1118; RV32-NEXT:    vlse64.v v12, (a0), zero
1119; RV32-NEXT:    addi a0, sp, 8
1120; RV32-NEXT:    vlse64.v v16, (a0), zero
1121; RV32-NEXT:    vsrl.vi v20, v8, 4
1122; RV32-NEXT:    vadd.vv v8, v8, v20
1123; RV32-NEXT:    vand.vv v8, v8, v12
1124; RV32-NEXT:    vmul.vv v8, v8, v16
1125; RV32-NEXT:    addi a0, zero, 56
1126; RV32-NEXT:    vsrl.vx v8, v8, a0
1127; RV32-NEXT:    addi sp, sp, 16
1128; RV32-NEXT:    ret
1129;
1130; RV64-LABEL: cttz_nxv4i64:
1131; RV64:       # %bb.0:
1132; RV64-NEXT:    addi a0, zero, 1
1133; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1134; RV64-NEXT:    vsub.vx v12, v8, a0
1135; RV64-NEXT:    vxor.vi v8, v8, -1
1136; RV64-NEXT:    vand.vv v8, v8, v12
1137; RV64-NEXT:    vsrl.vi v12, v8, 1
1138; RV64-NEXT:    lui a0, 21845
1139; RV64-NEXT:    addiw a0, a0, 1365
1140; RV64-NEXT:    slli a0, a0, 12
1141; RV64-NEXT:    addi a0, a0, 1365
1142; RV64-NEXT:    slli a0, a0, 12
1143; RV64-NEXT:    addi a0, a0, 1365
1144; RV64-NEXT:    slli a0, a0, 12
1145; RV64-NEXT:    addi a0, a0, 1365
1146; RV64-NEXT:    vand.vx v12, v12, a0
1147; RV64-NEXT:    vsub.vv v8, v8, v12
1148; RV64-NEXT:    lui a0, 13107
1149; RV64-NEXT:    addiw a0, a0, 819
1150; RV64-NEXT:    slli a0, a0, 12
1151; RV64-NEXT:    addi a0, a0, 819
1152; RV64-NEXT:    slli a0, a0, 12
1153; RV64-NEXT:    addi a0, a0, 819
1154; RV64-NEXT:    slli a0, a0, 12
1155; RV64-NEXT:    addi a0, a0, 819
1156; RV64-NEXT:    vand.vx v12, v8, a0
1157; RV64-NEXT:    vsrl.vi v8, v8, 2
1158; RV64-NEXT:    vand.vx v8, v8, a0
1159; RV64-NEXT:    vadd.vv v8, v12, v8
1160; RV64-NEXT:    vsrl.vi v12, v8, 4
1161; RV64-NEXT:    vadd.vv v8, v8, v12
1162; RV64-NEXT:    lui a0, 3855
1163; RV64-NEXT:    addiw a0, a0, 241
1164; RV64-NEXT:    slli a0, a0, 12
1165; RV64-NEXT:    addi a0, a0, -241
1166; RV64-NEXT:    slli a0, a0, 12
1167; RV64-NEXT:    addi a0, a0, 241
1168; RV64-NEXT:    slli a0, a0, 12
1169; RV64-NEXT:    addi a0, a0, -241
1170; RV64-NEXT:    vand.vx v8, v8, a0
1171; RV64-NEXT:    lui a0, 4112
1172; RV64-NEXT:    addiw a0, a0, 257
1173; RV64-NEXT:    slli a0, a0, 16
1174; RV64-NEXT:    addi a0, a0, 257
1175; RV64-NEXT:    slli a0, a0, 16
1176; RV64-NEXT:    addi a0, a0, 257
1177; RV64-NEXT:    vmul.vx v8, v8, a0
1178; RV64-NEXT:    addi a0, zero, 56
1179; RV64-NEXT:    vsrl.vx v8, v8, a0
1180; RV64-NEXT:    ret
1181  %a = call <vscale x 4 x i64> @llvm.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 false)
1182  ret <vscale x 4 x i64> %a
1183}
1184declare <vscale x 4 x i64> @llvm.cttz.nxv4i64(<vscale x 4 x i64>, i1)
1185
1186define <vscale x 8 x i64> @cttz_nxv8i64(<vscale x 8 x i64> %va) {
1187; RV32-LABEL: cttz_nxv8i64:
1188; RV32:       # %bb.0:
1189; RV32-NEXT:    addi sp, sp, -16
1190; RV32-NEXT:    .cfi_def_cfa_offset 16
1191; RV32-NEXT:    lui a0, 349525
1192; RV32-NEXT:    addi a0, a0, 1365
1193; RV32-NEXT:    sw a0, 12(sp)
1194; RV32-NEXT:    sw a0, 8(sp)
1195; RV32-NEXT:    lui a0, 209715
1196; RV32-NEXT:    addi a0, a0, 819
1197; RV32-NEXT:    sw a0, 12(sp)
1198; RV32-NEXT:    sw a0, 8(sp)
1199; RV32-NEXT:    lui a0, 61681
1200; RV32-NEXT:    addi a0, a0, -241
1201; RV32-NEXT:    sw a0, 12(sp)
1202; RV32-NEXT:    sw a0, 8(sp)
1203; RV32-NEXT:    lui a0, 4112
1204; RV32-NEXT:    addi a0, a0, 257
1205; RV32-NEXT:    sw a0, 12(sp)
1206; RV32-NEXT:    sw a0, 8(sp)
1207; RV32-NEXT:    addi a0, zero, 1
1208; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1209; RV32-NEXT:    vsub.vx v16, v8, a0
1210; RV32-NEXT:    vxor.vi v8, v8, -1
1211; RV32-NEXT:    addi a0, sp, 8
1212; RV32-NEXT:    vlse64.v v24, (a0), zero
1213; RV32-NEXT:    vand.vv v8, v8, v16
1214; RV32-NEXT:    addi a0, sp, 8
1215; RV32-NEXT:    vlse64.v v16, (a0), zero
1216; RV32-NEXT:    vsrl.vi v0, v8, 1
1217; RV32-NEXT:    vand.vv v24, v0, v24
1218; RV32-NEXT:    vsub.vv v8, v8, v24
1219; RV32-NEXT:    vand.vv v24, v8, v16
1220; RV32-NEXT:    vsrl.vi v8, v8, 2
1221; RV32-NEXT:    vand.vv v8, v8, v16
1222; RV32-NEXT:    vadd.vv v8, v24, v8
1223; RV32-NEXT:    addi a0, sp, 8
1224; RV32-NEXT:    vlse64.v v16, (a0), zero
1225; RV32-NEXT:    addi a0, sp, 8
1226; RV32-NEXT:    vlse64.v v24, (a0), zero
1227; RV32-NEXT:    vsrl.vi v0, v8, 4
1228; RV32-NEXT:    vadd.vv v8, v8, v0
1229; RV32-NEXT:    vand.vv v8, v8, v16
1230; RV32-NEXT:    vmul.vv v8, v8, v24
1231; RV32-NEXT:    addi a0, zero, 56
1232; RV32-NEXT:    vsrl.vx v8, v8, a0
1233; RV32-NEXT:    addi sp, sp, 16
1234; RV32-NEXT:    ret
1235;
1236; RV64-LABEL: cttz_nxv8i64:
1237; RV64:       # %bb.0:
1238; RV64-NEXT:    addi a0, zero, 1
1239; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1240; RV64-NEXT:    vsub.vx v16, v8, a0
1241; RV64-NEXT:    vxor.vi v8, v8, -1
1242; RV64-NEXT:    vand.vv v8, v8, v16
1243; RV64-NEXT:    vsrl.vi v16, v8, 1
1244; RV64-NEXT:    lui a0, 21845
1245; RV64-NEXT:    addiw a0, a0, 1365
1246; RV64-NEXT:    slli a0, a0, 12
1247; RV64-NEXT:    addi a0, a0, 1365
1248; RV64-NEXT:    slli a0, a0, 12
1249; RV64-NEXT:    addi a0, a0, 1365
1250; RV64-NEXT:    slli a0, a0, 12
1251; RV64-NEXT:    addi a0, a0, 1365
1252; RV64-NEXT:    vand.vx v16, v16, a0
1253; RV64-NEXT:    vsub.vv v8, v8, v16
1254; RV64-NEXT:    lui a0, 13107
1255; RV64-NEXT:    addiw a0, a0, 819
1256; RV64-NEXT:    slli a0, a0, 12
1257; RV64-NEXT:    addi a0, a0, 819
1258; RV64-NEXT:    slli a0, a0, 12
1259; RV64-NEXT:    addi a0, a0, 819
1260; RV64-NEXT:    slli a0, a0, 12
1261; RV64-NEXT:    addi a0, a0, 819
1262; RV64-NEXT:    vand.vx v16, v8, a0
1263; RV64-NEXT:    vsrl.vi v8, v8, 2
1264; RV64-NEXT:    vand.vx v8, v8, a0
1265; RV64-NEXT:    vadd.vv v8, v16, v8
1266; RV64-NEXT:    vsrl.vi v16, v8, 4
1267; RV64-NEXT:    vadd.vv v8, v8, v16
1268; RV64-NEXT:    lui a0, 3855
1269; RV64-NEXT:    addiw a0, a0, 241
1270; RV64-NEXT:    slli a0, a0, 12
1271; RV64-NEXT:    addi a0, a0, -241
1272; RV64-NEXT:    slli a0, a0, 12
1273; RV64-NEXT:    addi a0, a0, 241
1274; RV64-NEXT:    slli a0, a0, 12
1275; RV64-NEXT:    addi a0, a0, -241
1276; RV64-NEXT:    vand.vx v8, v8, a0
1277; RV64-NEXT:    lui a0, 4112
1278; RV64-NEXT:    addiw a0, a0, 257
1279; RV64-NEXT:    slli a0, a0, 16
1280; RV64-NEXT:    addi a0, a0, 257
1281; RV64-NEXT:    slli a0, a0, 16
1282; RV64-NEXT:    addi a0, a0, 257
1283; RV64-NEXT:    vmul.vx v8, v8, a0
1284; RV64-NEXT:    addi a0, zero, 56
1285; RV64-NEXT:    vsrl.vx v8, v8, a0
1286; RV64-NEXT:    ret
1287  %a = call <vscale x 8 x i64> @llvm.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 false)
1288  ret <vscale x 8 x i64> %a
1289}
1290declare <vscale x 8 x i64> @llvm.cttz.nxv8i64(<vscale x 8 x i64>, i1)
1291
1292define <vscale x 1 x i8> @cttz_zero_undef_nxv1i8(<vscale x 1 x i8> %va) {
1293; CHECK-LABEL: cttz_zero_undef_nxv1i8:
1294; CHECK:       # %bb.0:
1295; CHECK-NEXT:    addi a0, zero, 1
1296; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
1297; CHECK-NEXT:    vsub.vx v9, v8, a0
1298; CHECK-NEXT:    vxor.vi v8, v8, -1
1299; CHECK-NEXT:    vand.vv v8, v8, v9
1300; CHECK-NEXT:    vsrl.vi v9, v8, 1
1301; CHECK-NEXT:    addi a0, zero, 85
1302; CHECK-NEXT:    vand.vx v9, v9, a0
1303; CHECK-NEXT:    vsub.vv v8, v8, v9
1304; CHECK-NEXT:    addi a0, zero, 51
1305; CHECK-NEXT:    vand.vx v9, v8, a0
1306; CHECK-NEXT:    vsrl.vi v8, v8, 2
1307; CHECK-NEXT:    vand.vx v8, v8, a0
1308; CHECK-NEXT:    vadd.vv v8, v9, v8
1309; CHECK-NEXT:    vsrl.vi v9, v8, 4
1310; CHECK-NEXT:    vadd.vv v8, v8, v9
1311; CHECK-NEXT:    vand.vi v8, v8, 15
1312; CHECK-NEXT:    ret
1313  %a = call <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 true)
1314  ret <vscale x 1 x i8> %a
1315}
1316
1317define <vscale x 2 x i8> @cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va) {
1318; CHECK-LABEL: cttz_zero_undef_nxv2i8:
1319; CHECK:       # %bb.0:
1320; CHECK-NEXT:    addi a0, zero, 1
1321; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
1322; CHECK-NEXT:    vsub.vx v9, v8, a0
1323; CHECK-NEXT:    vxor.vi v8, v8, -1
1324; CHECK-NEXT:    vand.vv v8, v8, v9
1325; CHECK-NEXT:    vsrl.vi v9, v8, 1
1326; CHECK-NEXT:    addi a0, zero, 85
1327; CHECK-NEXT:    vand.vx v9, v9, a0
1328; CHECK-NEXT:    vsub.vv v8, v8, v9
1329; CHECK-NEXT:    addi a0, zero, 51
1330; CHECK-NEXT:    vand.vx v9, v8, a0
1331; CHECK-NEXT:    vsrl.vi v8, v8, 2
1332; CHECK-NEXT:    vand.vx v8, v8, a0
1333; CHECK-NEXT:    vadd.vv v8, v9, v8
1334; CHECK-NEXT:    vsrl.vi v9, v8, 4
1335; CHECK-NEXT:    vadd.vv v8, v8, v9
1336; CHECK-NEXT:    vand.vi v8, v8, 15
1337; CHECK-NEXT:    ret
1338  %a = call <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 true)
1339  ret <vscale x 2 x i8> %a
1340}
1341
1342define <vscale x 4 x i8> @cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va) {
1343; CHECK-LABEL: cttz_zero_undef_nxv4i8:
1344; CHECK:       # %bb.0:
1345; CHECK-NEXT:    addi a0, zero, 1
1346; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
1347; CHECK-NEXT:    vsub.vx v9, v8, a0
1348; CHECK-NEXT:    vxor.vi v8, v8, -1
1349; CHECK-NEXT:    vand.vv v8, v8, v9
1350; CHECK-NEXT:    vsrl.vi v9, v8, 1
1351; CHECK-NEXT:    addi a0, zero, 85
1352; CHECK-NEXT:    vand.vx v9, v9, a0
1353; CHECK-NEXT:    vsub.vv v8, v8, v9
1354; CHECK-NEXT:    addi a0, zero, 51
1355; CHECK-NEXT:    vand.vx v9, v8, a0
1356; CHECK-NEXT:    vsrl.vi v8, v8, 2
1357; CHECK-NEXT:    vand.vx v8, v8, a0
1358; CHECK-NEXT:    vadd.vv v8, v9, v8
1359; CHECK-NEXT:    vsrl.vi v9, v8, 4
1360; CHECK-NEXT:    vadd.vv v8, v8, v9
1361; CHECK-NEXT:    vand.vi v8, v8, 15
1362; CHECK-NEXT:    ret
1363  %a = call <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 true)
1364  ret <vscale x 4 x i8> %a
1365}
1366
1367define <vscale x 8 x i8> @cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va) {
1368; CHECK-LABEL: cttz_zero_undef_nxv8i8:
1369; CHECK:       # %bb.0:
1370; CHECK-NEXT:    addi a0, zero, 1
1371; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
1372; CHECK-NEXT:    vsub.vx v9, v8, a0
1373; CHECK-NEXT:    vxor.vi v8, v8, -1
1374; CHECK-NEXT:    vand.vv v8, v8, v9
1375; CHECK-NEXT:    vsrl.vi v9, v8, 1
1376; CHECK-NEXT:    addi a0, zero, 85
1377; CHECK-NEXT:    vand.vx v9, v9, a0
1378; CHECK-NEXT:    vsub.vv v8, v8, v9
1379; CHECK-NEXT:    addi a0, zero, 51
1380; CHECK-NEXT:    vand.vx v9, v8, a0
1381; CHECK-NEXT:    vsrl.vi v8, v8, 2
1382; CHECK-NEXT:    vand.vx v8, v8, a0
1383; CHECK-NEXT:    vadd.vv v8, v9, v8
1384; CHECK-NEXT:    vsrl.vi v9, v8, 4
1385; CHECK-NEXT:    vadd.vv v8, v8, v9
1386; CHECK-NEXT:    vand.vi v8, v8, 15
1387; CHECK-NEXT:    ret
1388  %a = call <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 true)
1389  ret <vscale x 8 x i8> %a
1390}
1391
1392define <vscale x 16 x i8> @cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) {
1393; CHECK-LABEL: cttz_zero_undef_nxv16i8:
1394; CHECK:       # %bb.0:
1395; CHECK-NEXT:    addi a0, zero, 1
1396; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
1397; CHECK-NEXT:    vsub.vx v10, v8, a0
1398; CHECK-NEXT:    vxor.vi v8, v8, -1
1399; CHECK-NEXT:    vand.vv v8, v8, v10
1400; CHECK-NEXT:    vsrl.vi v10, v8, 1
1401; CHECK-NEXT:    addi a0, zero, 85
1402; CHECK-NEXT:    vand.vx v10, v10, a0
1403; CHECK-NEXT:    vsub.vv v8, v8, v10
1404; CHECK-NEXT:    addi a0, zero, 51
1405; CHECK-NEXT:    vand.vx v10, v8, a0
1406; CHECK-NEXT:    vsrl.vi v8, v8, 2
1407; CHECK-NEXT:    vand.vx v8, v8, a0
1408; CHECK-NEXT:    vadd.vv v8, v10, v8
1409; CHECK-NEXT:    vsrl.vi v10, v8, 4
1410; CHECK-NEXT:    vadd.vv v8, v8, v10
1411; CHECK-NEXT:    vand.vi v8, v8, 15
1412; CHECK-NEXT:    ret
1413  %a = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 true)
1414  ret <vscale x 16 x i8> %a
1415}
1416
1417define <vscale x 32 x i8> @cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va) {
1418; CHECK-LABEL: cttz_zero_undef_nxv32i8:
1419; CHECK:       # %bb.0:
1420; CHECK-NEXT:    addi a0, zero, 1
1421; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
1422; CHECK-NEXT:    vsub.vx v12, v8, a0
1423; CHECK-NEXT:    vxor.vi v8, v8, -1
1424; CHECK-NEXT:    vand.vv v8, v8, v12
1425; CHECK-NEXT:    vsrl.vi v12, v8, 1
1426; CHECK-NEXT:    addi a0, zero, 85
1427; CHECK-NEXT:    vand.vx v12, v12, a0
1428; CHECK-NEXT:    vsub.vv v8, v8, v12
1429; CHECK-NEXT:    addi a0, zero, 51
1430; CHECK-NEXT:    vand.vx v12, v8, a0
1431; CHECK-NEXT:    vsrl.vi v8, v8, 2
1432; CHECK-NEXT:    vand.vx v8, v8, a0
1433; CHECK-NEXT:    vadd.vv v8, v12, v8
1434; CHECK-NEXT:    vsrl.vi v12, v8, 4
1435; CHECK-NEXT:    vadd.vv v8, v8, v12
1436; CHECK-NEXT:    vand.vi v8, v8, 15
1437; CHECK-NEXT:    ret
1438  %a = call <vscale x 32 x i8> @llvm.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 true)
1439  ret <vscale x 32 x i8> %a
1440}
1441
1442define <vscale x 64 x i8> @cttz_zero_undef_nxv64i8(<vscale x 64 x i8> %va) {
1443; CHECK-LABEL: cttz_zero_undef_nxv64i8:
1444; CHECK:       # %bb.0:
1445; CHECK-NEXT:    addi a0, zero, 1
1446; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
1447; CHECK-NEXT:    vsub.vx v16, v8, a0
1448; CHECK-NEXT:    vxor.vi v8, v8, -1
1449; CHECK-NEXT:    vand.vv v8, v8, v16
1450; CHECK-NEXT:    vsrl.vi v16, v8, 1
1451; CHECK-NEXT:    addi a0, zero, 85
1452; CHECK-NEXT:    vand.vx v16, v16, a0
1453; CHECK-NEXT:    vsub.vv v8, v8, v16
1454; CHECK-NEXT:    addi a0, zero, 51
1455; CHECK-NEXT:    vand.vx v16, v8, a0
1456; CHECK-NEXT:    vsrl.vi v8, v8, 2
1457; CHECK-NEXT:    vand.vx v8, v8, a0
1458; CHECK-NEXT:    vadd.vv v8, v16, v8
1459; CHECK-NEXT:    vsrl.vi v16, v8, 4
1460; CHECK-NEXT:    vadd.vv v8, v8, v16
1461; CHECK-NEXT:    vand.vi v8, v8, 15
1462; CHECK-NEXT:    ret
1463  %a = call <vscale x 64 x i8> @llvm.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 true)
1464  ret <vscale x 64 x i8> %a
1465}
1466
1467define <vscale x 1 x i16> @cttz_zero_undef_nxv1i16(<vscale x 1 x i16> %va) {
1468; RV32-LABEL: cttz_zero_undef_nxv1i16:
1469; RV32:       # %bb.0:
1470; RV32-NEXT:    addi a0, zero, 1
1471; RV32-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
1472; RV32-NEXT:    vsub.vx v9, v8, a0
1473; RV32-NEXT:    vxor.vi v8, v8, -1
1474; RV32-NEXT:    vand.vv v8, v8, v9
1475; RV32-NEXT:    vsrl.vi v9, v8, 1
1476; RV32-NEXT:    lui a0, 5
1477; RV32-NEXT:    addi a0, a0, 1365
1478; RV32-NEXT:    vand.vx v9, v9, a0
1479; RV32-NEXT:    vsub.vv v8, v8, v9
1480; RV32-NEXT:    lui a0, 3
1481; RV32-NEXT:    addi a0, a0, 819
1482; RV32-NEXT:    vand.vx v9, v8, a0
1483; RV32-NEXT:    vsrl.vi v8, v8, 2
1484; RV32-NEXT:    vand.vx v8, v8, a0
1485; RV32-NEXT:    vadd.vv v8, v9, v8
1486; RV32-NEXT:    vsrl.vi v9, v8, 4
1487; RV32-NEXT:    vadd.vv v8, v8, v9
1488; RV32-NEXT:    lui a0, 1
1489; RV32-NEXT:    addi a0, a0, -241
1490; RV32-NEXT:    vand.vx v8, v8, a0
1491; RV32-NEXT:    addi a0, zero, 257
1492; RV32-NEXT:    vmul.vx v8, v8, a0
1493; RV32-NEXT:    vsrl.vi v8, v8, 8
1494; RV32-NEXT:    ret
1495;
1496; RV64-LABEL: cttz_zero_undef_nxv1i16:
1497; RV64:       # %bb.0:
1498; RV64-NEXT:    addi a0, zero, 1
1499; RV64-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
1500; RV64-NEXT:    vsub.vx v9, v8, a0
1501; RV64-NEXT:    vxor.vi v8, v8, -1
1502; RV64-NEXT:    vand.vv v8, v8, v9
1503; RV64-NEXT:    vsrl.vi v9, v8, 1
1504; RV64-NEXT:    lui a0, 5
1505; RV64-NEXT:    addiw a0, a0, 1365
1506; RV64-NEXT:    vand.vx v9, v9, a0
1507; RV64-NEXT:    vsub.vv v8, v8, v9
1508; RV64-NEXT:    lui a0, 3
1509; RV64-NEXT:    addiw a0, a0, 819
1510; RV64-NEXT:    vand.vx v9, v8, a0
1511; RV64-NEXT:    vsrl.vi v8, v8, 2
1512; RV64-NEXT:    vand.vx v8, v8, a0
1513; RV64-NEXT:    vadd.vv v8, v9, v8
1514; RV64-NEXT:    vsrl.vi v9, v8, 4
1515; RV64-NEXT:    vadd.vv v8, v8, v9
1516; RV64-NEXT:    lui a0, 1
1517; RV64-NEXT:    addiw a0, a0, -241
1518; RV64-NEXT:    vand.vx v8, v8, a0
1519; RV64-NEXT:    addi a0, zero, 257
1520; RV64-NEXT:    vmul.vx v8, v8, a0
1521; RV64-NEXT:    vsrl.vi v8, v8, 8
1522; RV64-NEXT:    ret
1523  %a = call <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 true)
1524  ret <vscale x 1 x i16> %a
1525}
1526
1527define <vscale x 2 x i16> @cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) {
1528; RV32-LABEL: cttz_zero_undef_nxv2i16:
1529; RV32:       # %bb.0:
1530; RV32-NEXT:    addi a0, zero, 1
1531; RV32-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
1532; RV32-NEXT:    vsub.vx v9, v8, a0
1533; RV32-NEXT:    vxor.vi v8, v8, -1
1534; RV32-NEXT:    vand.vv v8, v8, v9
1535; RV32-NEXT:    vsrl.vi v9, v8, 1
1536; RV32-NEXT:    lui a0, 5
1537; RV32-NEXT:    addi a0, a0, 1365
1538; RV32-NEXT:    vand.vx v9, v9, a0
1539; RV32-NEXT:    vsub.vv v8, v8, v9
1540; RV32-NEXT:    lui a0, 3
1541; RV32-NEXT:    addi a0, a0, 819
1542; RV32-NEXT:    vand.vx v9, v8, a0
1543; RV32-NEXT:    vsrl.vi v8, v8, 2
1544; RV32-NEXT:    vand.vx v8, v8, a0
1545; RV32-NEXT:    vadd.vv v8, v9, v8
1546; RV32-NEXT:    vsrl.vi v9, v8, 4
1547; RV32-NEXT:    vadd.vv v8, v8, v9
1548; RV32-NEXT:    lui a0, 1
1549; RV32-NEXT:    addi a0, a0, -241
1550; RV32-NEXT:    vand.vx v8, v8, a0
1551; RV32-NEXT:    addi a0, zero, 257
1552; RV32-NEXT:    vmul.vx v8, v8, a0
1553; RV32-NEXT:    vsrl.vi v8, v8, 8
1554; RV32-NEXT:    ret
1555;
1556; RV64-LABEL: cttz_zero_undef_nxv2i16:
1557; RV64:       # %bb.0:
1558; RV64-NEXT:    addi a0, zero, 1
1559; RV64-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
1560; RV64-NEXT:    vsub.vx v9, v8, a0
1561; RV64-NEXT:    vxor.vi v8, v8, -1
1562; RV64-NEXT:    vand.vv v8, v8, v9
1563; RV64-NEXT:    vsrl.vi v9, v8, 1
1564; RV64-NEXT:    lui a0, 5
1565; RV64-NEXT:    addiw a0, a0, 1365
1566; RV64-NEXT:    vand.vx v9, v9, a0
1567; RV64-NEXT:    vsub.vv v8, v8, v9
1568; RV64-NEXT:    lui a0, 3
1569; RV64-NEXT:    addiw a0, a0, 819
1570; RV64-NEXT:    vand.vx v9, v8, a0
1571; RV64-NEXT:    vsrl.vi v8, v8, 2
1572; RV64-NEXT:    vand.vx v8, v8, a0
1573; RV64-NEXT:    vadd.vv v8, v9, v8
1574; RV64-NEXT:    vsrl.vi v9, v8, 4
1575; RV64-NEXT:    vadd.vv v8, v8, v9
1576; RV64-NEXT:    lui a0, 1
1577; RV64-NEXT:    addiw a0, a0, -241
1578; RV64-NEXT:    vand.vx v8, v8, a0
1579; RV64-NEXT:    addi a0, zero, 257
1580; RV64-NEXT:    vmul.vx v8, v8, a0
1581; RV64-NEXT:    vsrl.vi v8, v8, 8
1582; RV64-NEXT:    ret
1583  %a = call <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 true)
1584  ret <vscale x 2 x i16> %a
1585}
1586
1587define <vscale x 4 x i16> @cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) {
1588; RV32-LABEL: cttz_zero_undef_nxv4i16:
1589; RV32:       # %bb.0:
1590; RV32-NEXT:    addi a0, zero, 1
1591; RV32-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
1592; RV32-NEXT:    vsub.vx v9, v8, a0
1593; RV32-NEXT:    vxor.vi v8, v8, -1
1594; RV32-NEXT:    vand.vv v8, v8, v9
1595; RV32-NEXT:    vsrl.vi v9, v8, 1
1596; RV32-NEXT:    lui a0, 5
1597; RV32-NEXT:    addi a0, a0, 1365
1598; RV32-NEXT:    vand.vx v9, v9, a0
1599; RV32-NEXT:    vsub.vv v8, v8, v9
1600; RV32-NEXT:    lui a0, 3
1601; RV32-NEXT:    addi a0, a0, 819
1602; RV32-NEXT:    vand.vx v9, v8, a0
1603; RV32-NEXT:    vsrl.vi v8, v8, 2
1604; RV32-NEXT:    vand.vx v8, v8, a0
1605; RV32-NEXT:    vadd.vv v8, v9, v8
1606; RV32-NEXT:    vsrl.vi v9, v8, 4
1607; RV32-NEXT:    vadd.vv v8, v8, v9
1608; RV32-NEXT:    lui a0, 1
1609; RV32-NEXT:    addi a0, a0, -241
1610; RV32-NEXT:    vand.vx v8, v8, a0
1611; RV32-NEXT:    addi a0, zero, 257
1612; RV32-NEXT:    vmul.vx v8, v8, a0
1613; RV32-NEXT:    vsrl.vi v8, v8, 8
1614; RV32-NEXT:    ret
1615;
1616; RV64-LABEL: cttz_zero_undef_nxv4i16:
1617; RV64:       # %bb.0:
1618; RV64-NEXT:    addi a0, zero, 1
1619; RV64-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
1620; RV64-NEXT:    vsub.vx v9, v8, a0
1621; RV64-NEXT:    vxor.vi v8, v8, -1
1622; RV64-NEXT:    vand.vv v8, v8, v9
1623; RV64-NEXT:    vsrl.vi v9, v8, 1
1624; RV64-NEXT:    lui a0, 5
1625; RV64-NEXT:    addiw a0, a0, 1365
1626; RV64-NEXT:    vand.vx v9, v9, a0
1627; RV64-NEXT:    vsub.vv v8, v8, v9
1628; RV64-NEXT:    lui a0, 3
1629; RV64-NEXT:    addiw a0, a0, 819
1630; RV64-NEXT:    vand.vx v9, v8, a0
1631; RV64-NEXT:    vsrl.vi v8, v8, 2
1632; RV64-NEXT:    vand.vx v8, v8, a0
1633; RV64-NEXT:    vadd.vv v8, v9, v8
1634; RV64-NEXT:    vsrl.vi v9, v8, 4
1635; RV64-NEXT:    vadd.vv v8, v8, v9
1636; RV64-NEXT:    lui a0, 1
1637; RV64-NEXT:    addiw a0, a0, -241
1638; RV64-NEXT:    vand.vx v8, v8, a0
1639; RV64-NEXT:    addi a0, zero, 257
1640; RV64-NEXT:    vmul.vx v8, v8, a0
1641; RV64-NEXT:    vsrl.vi v8, v8, 8
1642; RV64-NEXT:    ret
1643  %a = call <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 true)
1644  ret <vscale x 4 x i16> %a
1645}
1646
1647define <vscale x 8 x i16> @cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
1648; RV32-LABEL: cttz_zero_undef_nxv8i16:
1649; RV32:       # %bb.0:
1650; RV32-NEXT:    addi a0, zero, 1
1651; RV32-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
1652; RV32-NEXT:    vsub.vx v10, v8, a0
1653; RV32-NEXT:    vxor.vi v8, v8, -1
1654; RV32-NEXT:    vand.vv v8, v8, v10
1655; RV32-NEXT:    vsrl.vi v10, v8, 1
1656; RV32-NEXT:    lui a0, 5
1657; RV32-NEXT:    addi a0, a0, 1365
1658; RV32-NEXT:    vand.vx v10, v10, a0
1659; RV32-NEXT:    vsub.vv v8, v8, v10
1660; RV32-NEXT:    lui a0, 3
1661; RV32-NEXT:    addi a0, a0, 819
1662; RV32-NEXT:    vand.vx v10, v8, a0
1663; RV32-NEXT:    vsrl.vi v8, v8, 2
1664; RV32-NEXT:    vand.vx v8, v8, a0
1665; RV32-NEXT:    vadd.vv v8, v10, v8
1666; RV32-NEXT:    vsrl.vi v10, v8, 4
1667; RV32-NEXT:    vadd.vv v8, v8, v10
1668; RV32-NEXT:    lui a0, 1
1669; RV32-NEXT:    addi a0, a0, -241
1670; RV32-NEXT:    vand.vx v8, v8, a0
1671; RV32-NEXT:    addi a0, zero, 257
1672; RV32-NEXT:    vmul.vx v8, v8, a0
1673; RV32-NEXT:    vsrl.vi v8, v8, 8
1674; RV32-NEXT:    ret
1675;
1676; RV64-LABEL: cttz_zero_undef_nxv8i16:
1677; RV64:       # %bb.0:
1678; RV64-NEXT:    addi a0, zero, 1
1679; RV64-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
1680; RV64-NEXT:    vsub.vx v10, v8, a0
1681; RV64-NEXT:    vxor.vi v8, v8, -1
1682; RV64-NEXT:    vand.vv v8, v8, v10
1683; RV64-NEXT:    vsrl.vi v10, v8, 1
1684; RV64-NEXT:    lui a0, 5
1685; RV64-NEXT:    addiw a0, a0, 1365
1686; RV64-NEXT:    vand.vx v10, v10, a0
1687; RV64-NEXT:    vsub.vv v8, v8, v10
1688; RV64-NEXT:    lui a0, 3
1689; RV64-NEXT:    addiw a0, a0, 819
1690; RV64-NEXT:    vand.vx v10, v8, a0
1691; RV64-NEXT:    vsrl.vi v8, v8, 2
1692; RV64-NEXT:    vand.vx v8, v8, a0
1693; RV64-NEXT:    vadd.vv v8, v10, v8
1694; RV64-NEXT:    vsrl.vi v10, v8, 4
1695; RV64-NEXT:    vadd.vv v8, v8, v10
1696; RV64-NEXT:    lui a0, 1
1697; RV64-NEXT:    addiw a0, a0, -241
1698; RV64-NEXT:    vand.vx v8, v8, a0
1699; RV64-NEXT:    addi a0, zero, 257
1700; RV64-NEXT:    vmul.vx v8, v8, a0
1701; RV64-NEXT:    vsrl.vi v8, v8, 8
1702; RV64-NEXT:    ret
1703  %a = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 true)
1704  ret <vscale x 8 x i16> %a
1705}
1706
1707define <vscale x 16 x i16> @cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
1708; RV32-LABEL: cttz_zero_undef_nxv16i16:
1709; RV32:       # %bb.0:
1710; RV32-NEXT:    addi a0, zero, 1
1711; RV32-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
1712; RV32-NEXT:    vsub.vx v12, v8, a0
1713; RV32-NEXT:    vxor.vi v8, v8, -1
1714; RV32-NEXT:    vand.vv v8, v8, v12
1715; RV32-NEXT:    vsrl.vi v12, v8, 1
1716; RV32-NEXT:    lui a0, 5
1717; RV32-NEXT:    addi a0, a0, 1365
1718; RV32-NEXT:    vand.vx v12, v12, a0
1719; RV32-NEXT:    vsub.vv v8, v8, v12
1720; RV32-NEXT:    lui a0, 3
1721; RV32-NEXT:    addi a0, a0, 819
1722; RV32-NEXT:    vand.vx v12, v8, a0
1723; RV32-NEXT:    vsrl.vi v8, v8, 2
1724; RV32-NEXT:    vand.vx v8, v8, a0
1725; RV32-NEXT:    vadd.vv v8, v12, v8
1726; RV32-NEXT:    vsrl.vi v12, v8, 4
1727; RV32-NEXT:    vadd.vv v8, v8, v12
1728; RV32-NEXT:    lui a0, 1
1729; RV32-NEXT:    addi a0, a0, -241
1730; RV32-NEXT:    vand.vx v8, v8, a0
1731; RV32-NEXT:    addi a0, zero, 257
1732; RV32-NEXT:    vmul.vx v8, v8, a0
1733; RV32-NEXT:    vsrl.vi v8, v8, 8
1734; RV32-NEXT:    ret
1735;
1736; RV64-LABEL: cttz_zero_undef_nxv16i16:
1737; RV64:       # %bb.0:
1738; RV64-NEXT:    addi a0, zero, 1
1739; RV64-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
1740; RV64-NEXT:    vsub.vx v12, v8, a0
1741; RV64-NEXT:    vxor.vi v8, v8, -1
1742; RV64-NEXT:    vand.vv v8, v8, v12
1743; RV64-NEXT:    vsrl.vi v12, v8, 1
1744; RV64-NEXT:    lui a0, 5
1745; RV64-NEXT:    addiw a0, a0, 1365
1746; RV64-NEXT:    vand.vx v12, v12, a0
1747; RV64-NEXT:    vsub.vv v8, v8, v12
1748; RV64-NEXT:    lui a0, 3
1749; RV64-NEXT:    addiw a0, a0, 819
1750; RV64-NEXT:    vand.vx v12, v8, a0
1751; RV64-NEXT:    vsrl.vi v8, v8, 2
1752; RV64-NEXT:    vand.vx v8, v8, a0
1753; RV64-NEXT:    vadd.vv v8, v12, v8
1754; RV64-NEXT:    vsrl.vi v12, v8, 4
1755; RV64-NEXT:    vadd.vv v8, v8, v12
1756; RV64-NEXT:    lui a0, 1
1757; RV64-NEXT:    addiw a0, a0, -241
1758; RV64-NEXT:    vand.vx v8, v8, a0
1759; RV64-NEXT:    addi a0, zero, 257
1760; RV64-NEXT:    vmul.vx v8, v8, a0
1761; RV64-NEXT:    vsrl.vi v8, v8, 8
1762; RV64-NEXT:    ret
1763  %a = call <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 true)
1764  ret <vscale x 16 x i16> %a
1765}
1766
1767define <vscale x 32 x i16> @cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va) {
1768; RV32-LABEL: cttz_zero_undef_nxv32i16:
1769; RV32:       # %bb.0:
1770; RV32-NEXT:    addi a0, zero, 1
1771; RV32-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
1772; RV32-NEXT:    vsub.vx v16, v8, a0
1773; RV32-NEXT:    vxor.vi v8, v8, -1
1774; RV32-NEXT:    vand.vv v8, v8, v16
1775; RV32-NEXT:    vsrl.vi v16, v8, 1
1776; RV32-NEXT:    lui a0, 5
1777; RV32-NEXT:    addi a0, a0, 1365
1778; RV32-NEXT:    vand.vx v16, v16, a0
1779; RV32-NEXT:    vsub.vv v8, v8, v16
1780; RV32-NEXT:    lui a0, 3
1781; RV32-NEXT:    addi a0, a0, 819
1782; RV32-NEXT:    vand.vx v16, v8, a0
1783; RV32-NEXT:    vsrl.vi v8, v8, 2
1784; RV32-NEXT:    vand.vx v8, v8, a0
1785; RV32-NEXT:    vadd.vv v8, v16, v8
1786; RV32-NEXT:    vsrl.vi v16, v8, 4
1787; RV32-NEXT:    vadd.vv v8, v8, v16
1788; RV32-NEXT:    lui a0, 1
1789; RV32-NEXT:    addi a0, a0, -241
1790; RV32-NEXT:    vand.vx v8, v8, a0
1791; RV32-NEXT:    addi a0, zero, 257
1792; RV32-NEXT:    vmul.vx v8, v8, a0
1793; RV32-NEXT:    vsrl.vi v8, v8, 8
1794; RV32-NEXT:    ret
1795;
1796; RV64-LABEL: cttz_zero_undef_nxv32i16:
1797; RV64:       # %bb.0:
1798; RV64-NEXT:    addi a0, zero, 1
1799; RV64-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
1800; RV64-NEXT:    vsub.vx v16, v8, a0
1801; RV64-NEXT:    vxor.vi v8, v8, -1
1802; RV64-NEXT:    vand.vv v8, v8, v16
1803; RV64-NEXT:    vsrl.vi v16, v8, 1
1804; RV64-NEXT:    lui a0, 5
1805; RV64-NEXT:    addiw a0, a0, 1365
1806; RV64-NEXT:    vand.vx v16, v16, a0
1807; RV64-NEXT:    vsub.vv v8, v8, v16
1808; RV64-NEXT:    lui a0, 3
1809; RV64-NEXT:    addiw a0, a0, 819
1810; RV64-NEXT:    vand.vx v16, v8, a0
1811; RV64-NEXT:    vsrl.vi v8, v8, 2
1812; RV64-NEXT:    vand.vx v8, v8, a0
1813; RV64-NEXT:    vadd.vv v8, v16, v8
1814; RV64-NEXT:    vsrl.vi v16, v8, 4
1815; RV64-NEXT:    vadd.vv v8, v8, v16
1816; RV64-NEXT:    lui a0, 1
1817; RV64-NEXT:    addiw a0, a0, -241
1818; RV64-NEXT:    vand.vx v8, v8, a0
1819; RV64-NEXT:    addi a0, zero, 257
1820; RV64-NEXT:    vmul.vx v8, v8, a0
1821; RV64-NEXT:    vsrl.vi v8, v8, 8
1822; RV64-NEXT:    ret
1823  %a = call <vscale x 32 x i16> @llvm.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 true)
1824  ret <vscale x 32 x i16> %a
1825}
1826
1827define <vscale x 1 x i32> @cttz_zero_undef_nxv1i32(<vscale x 1 x i32> %va) {
1828; RV32-LABEL: cttz_zero_undef_nxv1i32:
1829; RV32:       # %bb.0:
1830; RV32-NEXT:    addi a0, zero, 1
1831; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
1832; RV32-NEXT:    vsub.vx v9, v8, a0
1833; RV32-NEXT:    vxor.vi v8, v8, -1
1834; RV32-NEXT:    vand.vv v8, v8, v9
1835; RV32-NEXT:    vsrl.vi v9, v8, 1
1836; RV32-NEXT:    lui a0, 349525
1837; RV32-NEXT:    addi a0, a0, 1365
1838; RV32-NEXT:    vand.vx v9, v9, a0
1839; RV32-NEXT:    vsub.vv v8, v8, v9
1840; RV32-NEXT:    lui a0, 209715
1841; RV32-NEXT:    addi a0, a0, 819
1842; RV32-NEXT:    vand.vx v9, v8, a0
1843; RV32-NEXT:    vsrl.vi v8, v8, 2
1844; RV32-NEXT:    vand.vx v8, v8, a0
1845; RV32-NEXT:    vadd.vv v8, v9, v8
1846; RV32-NEXT:    vsrl.vi v9, v8, 4
1847; RV32-NEXT:    vadd.vv v8, v8, v9
1848; RV32-NEXT:    lui a0, 61681
1849; RV32-NEXT:    addi a0, a0, -241
1850; RV32-NEXT:    vand.vx v8, v8, a0
1851; RV32-NEXT:    lui a0, 4112
1852; RV32-NEXT:    addi a0, a0, 257
1853; RV32-NEXT:    vmul.vx v8, v8, a0
1854; RV32-NEXT:    vsrl.vi v8, v8, 24
1855; RV32-NEXT:    ret
1856;
1857; RV64-LABEL: cttz_zero_undef_nxv1i32:
1858; RV64:       # %bb.0:
1859; RV64-NEXT:    addi a0, zero, 1
1860; RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
1861; RV64-NEXT:    vsub.vx v9, v8, a0
1862; RV64-NEXT:    vxor.vi v8, v8, -1
1863; RV64-NEXT:    vand.vv v8, v8, v9
1864; RV64-NEXT:    vsrl.vi v9, v8, 1
1865; RV64-NEXT:    lui a0, 349525
1866; RV64-NEXT:    addiw a0, a0, 1365
1867; RV64-NEXT:    vand.vx v9, v9, a0
1868; RV64-NEXT:    vsub.vv v8, v8, v9
1869; RV64-NEXT:    lui a0, 209715
1870; RV64-NEXT:    addiw a0, a0, 819
1871; RV64-NEXT:    vand.vx v9, v8, a0
1872; RV64-NEXT:    vsrl.vi v8, v8, 2
1873; RV64-NEXT:    vand.vx v8, v8, a0
1874; RV64-NEXT:    vadd.vv v8, v9, v8
1875; RV64-NEXT:    vsrl.vi v9, v8, 4
1876; RV64-NEXT:    vadd.vv v8, v8, v9
1877; RV64-NEXT:    lui a0, 61681
1878; RV64-NEXT:    addiw a0, a0, -241
1879; RV64-NEXT:    vand.vx v8, v8, a0
1880; RV64-NEXT:    lui a0, 4112
1881; RV64-NEXT:    addiw a0, a0, 257
1882; RV64-NEXT:    vmul.vx v8, v8, a0
1883; RV64-NEXT:    vsrl.vi v8, v8, 24
1884; RV64-NEXT:    ret
1885  %a = call <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 true)
1886  ret <vscale x 1 x i32> %a
1887}
1888
1889define <vscale x 2 x i32> @cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) {
1890; RV32-LABEL: cttz_zero_undef_nxv2i32:
1891; RV32:       # %bb.0:
1892; RV32-NEXT:    addi a0, zero, 1
1893; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
1894; RV32-NEXT:    vsub.vx v9, v8, a0
1895; RV32-NEXT:    vxor.vi v8, v8, -1
1896; RV32-NEXT:    vand.vv v8, v8, v9
1897; RV32-NEXT:    vsrl.vi v9, v8, 1
1898; RV32-NEXT:    lui a0, 349525
1899; RV32-NEXT:    addi a0, a0, 1365
1900; RV32-NEXT:    vand.vx v9, v9, a0
1901; RV32-NEXT:    vsub.vv v8, v8, v9
1902; RV32-NEXT:    lui a0, 209715
1903; RV32-NEXT:    addi a0, a0, 819
1904; RV32-NEXT:    vand.vx v9, v8, a0
1905; RV32-NEXT:    vsrl.vi v8, v8, 2
1906; RV32-NEXT:    vand.vx v8, v8, a0
1907; RV32-NEXT:    vadd.vv v8, v9, v8
1908; RV32-NEXT:    vsrl.vi v9, v8, 4
1909; RV32-NEXT:    vadd.vv v8, v8, v9
1910; RV32-NEXT:    lui a0, 61681
1911; RV32-NEXT:    addi a0, a0, -241
1912; RV32-NEXT:    vand.vx v8, v8, a0
1913; RV32-NEXT:    lui a0, 4112
1914; RV32-NEXT:    addi a0, a0, 257
1915; RV32-NEXT:    vmul.vx v8, v8, a0
1916; RV32-NEXT:    vsrl.vi v8, v8, 24
1917; RV32-NEXT:    ret
1918;
1919; RV64-LABEL: cttz_zero_undef_nxv2i32:
1920; RV64:       # %bb.0:
1921; RV64-NEXT:    addi a0, zero, 1
1922; RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
1923; RV64-NEXT:    vsub.vx v9, v8, a0
1924; RV64-NEXT:    vxor.vi v8, v8, -1
1925; RV64-NEXT:    vand.vv v8, v8, v9
1926; RV64-NEXT:    vsrl.vi v9, v8, 1
1927; RV64-NEXT:    lui a0, 349525
1928; RV64-NEXT:    addiw a0, a0, 1365
1929; RV64-NEXT:    vand.vx v9, v9, a0
1930; RV64-NEXT:    vsub.vv v8, v8, v9
1931; RV64-NEXT:    lui a0, 209715
1932; RV64-NEXT:    addiw a0, a0, 819
1933; RV64-NEXT:    vand.vx v9, v8, a0
1934; RV64-NEXT:    vsrl.vi v8, v8, 2
1935; RV64-NEXT:    vand.vx v8, v8, a0
1936; RV64-NEXT:    vadd.vv v8, v9, v8
1937; RV64-NEXT:    vsrl.vi v9, v8, 4
1938; RV64-NEXT:    vadd.vv v8, v8, v9
1939; RV64-NEXT:    lui a0, 61681
1940; RV64-NEXT:    addiw a0, a0, -241
1941; RV64-NEXT:    vand.vx v8, v8, a0
1942; RV64-NEXT:    lui a0, 4112
1943; RV64-NEXT:    addiw a0, a0, 257
1944; RV64-NEXT:    vmul.vx v8, v8, a0
1945; RV64-NEXT:    vsrl.vi v8, v8, 24
1946; RV64-NEXT:    ret
1947  %a = call <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 true)
1948  ret <vscale x 2 x i32> %a
1949}
1950
1951define <vscale x 4 x i32> @cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
1952; RV32-LABEL: cttz_zero_undef_nxv4i32:
1953; RV32:       # %bb.0:
1954; RV32-NEXT:    addi a0, zero, 1
1955; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
1956; RV32-NEXT:    vsub.vx v10, v8, a0
1957; RV32-NEXT:    vxor.vi v8, v8, -1
1958; RV32-NEXT:    vand.vv v8, v8, v10
1959; RV32-NEXT:    vsrl.vi v10, v8, 1
1960; RV32-NEXT:    lui a0, 349525
1961; RV32-NEXT:    addi a0, a0, 1365
1962; RV32-NEXT:    vand.vx v10, v10, a0
1963; RV32-NEXT:    vsub.vv v8, v8, v10
1964; RV32-NEXT:    lui a0, 209715
1965; RV32-NEXT:    addi a0, a0, 819
1966; RV32-NEXT:    vand.vx v10, v8, a0
1967; RV32-NEXT:    vsrl.vi v8, v8, 2
1968; RV32-NEXT:    vand.vx v8, v8, a0
1969; RV32-NEXT:    vadd.vv v8, v10, v8
1970; RV32-NEXT:    vsrl.vi v10, v8, 4
1971; RV32-NEXT:    vadd.vv v8, v8, v10
1972; RV32-NEXT:    lui a0, 61681
1973; RV32-NEXT:    addi a0, a0, -241
1974; RV32-NEXT:    vand.vx v8, v8, a0
1975; RV32-NEXT:    lui a0, 4112
1976; RV32-NEXT:    addi a0, a0, 257
1977; RV32-NEXT:    vmul.vx v8, v8, a0
1978; RV32-NEXT:    vsrl.vi v8, v8, 24
1979; RV32-NEXT:    ret
1980;
1981; RV64-LABEL: cttz_zero_undef_nxv4i32:
1982; RV64:       # %bb.0:
1983; RV64-NEXT:    addi a0, zero, 1
1984; RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
1985; RV64-NEXT:    vsub.vx v10, v8, a0
1986; RV64-NEXT:    vxor.vi v8, v8, -1
1987; RV64-NEXT:    vand.vv v8, v8, v10
1988; RV64-NEXT:    vsrl.vi v10, v8, 1
1989; RV64-NEXT:    lui a0, 349525
1990; RV64-NEXT:    addiw a0, a0, 1365
1991; RV64-NEXT:    vand.vx v10, v10, a0
1992; RV64-NEXT:    vsub.vv v8, v8, v10
1993; RV64-NEXT:    lui a0, 209715
1994; RV64-NEXT:    addiw a0, a0, 819
1995; RV64-NEXT:    vand.vx v10, v8, a0
1996; RV64-NEXT:    vsrl.vi v8, v8, 2
1997; RV64-NEXT:    vand.vx v8, v8, a0
1998; RV64-NEXT:    vadd.vv v8, v10, v8
1999; RV64-NEXT:    vsrl.vi v10, v8, 4
2000; RV64-NEXT:    vadd.vv v8, v8, v10
2001; RV64-NEXT:    lui a0, 61681
2002; RV64-NEXT:    addiw a0, a0, -241
2003; RV64-NEXT:    vand.vx v8, v8, a0
2004; RV64-NEXT:    lui a0, 4112
2005; RV64-NEXT:    addiw a0, a0, 257
2006; RV64-NEXT:    vmul.vx v8, v8, a0
2007; RV64-NEXT:    vsrl.vi v8, v8, 24
2008; RV64-NEXT:    ret
2009  %a = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 true)
2010  ret <vscale x 4 x i32> %a
2011}
2012
2013define <vscale x 8 x i32> @cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
2014; RV32-LABEL: cttz_zero_undef_nxv8i32:
2015; RV32:       # %bb.0:
2016; RV32-NEXT:    addi a0, zero, 1
2017; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
2018; RV32-NEXT:    vsub.vx v12, v8, a0
2019; RV32-NEXT:    vxor.vi v8, v8, -1
2020; RV32-NEXT:    vand.vv v8, v8, v12
2021; RV32-NEXT:    vsrl.vi v12, v8, 1
2022; RV32-NEXT:    lui a0, 349525
2023; RV32-NEXT:    addi a0, a0, 1365
2024; RV32-NEXT:    vand.vx v12, v12, a0
2025; RV32-NEXT:    vsub.vv v8, v8, v12
2026; RV32-NEXT:    lui a0, 209715
2027; RV32-NEXT:    addi a0, a0, 819
2028; RV32-NEXT:    vand.vx v12, v8, a0
2029; RV32-NEXT:    vsrl.vi v8, v8, 2
2030; RV32-NEXT:    vand.vx v8, v8, a0
2031; RV32-NEXT:    vadd.vv v8, v12, v8
2032; RV32-NEXT:    vsrl.vi v12, v8, 4
2033; RV32-NEXT:    vadd.vv v8, v8, v12
2034; RV32-NEXT:    lui a0, 61681
2035; RV32-NEXT:    addi a0, a0, -241
2036; RV32-NEXT:    vand.vx v8, v8, a0
2037; RV32-NEXT:    lui a0, 4112
2038; RV32-NEXT:    addi a0, a0, 257
2039; RV32-NEXT:    vmul.vx v8, v8, a0
2040; RV32-NEXT:    vsrl.vi v8, v8, 24
2041; RV32-NEXT:    ret
2042;
2043; RV64-LABEL: cttz_zero_undef_nxv8i32:
2044; RV64:       # %bb.0:
2045; RV64-NEXT:    addi a0, zero, 1
2046; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
2047; RV64-NEXT:    vsub.vx v12, v8, a0
2048; RV64-NEXT:    vxor.vi v8, v8, -1
2049; RV64-NEXT:    vand.vv v8, v8, v12
2050; RV64-NEXT:    vsrl.vi v12, v8, 1
2051; RV64-NEXT:    lui a0, 349525
2052; RV64-NEXT:    addiw a0, a0, 1365
2053; RV64-NEXT:    vand.vx v12, v12, a0
2054; RV64-NEXT:    vsub.vv v8, v8, v12
2055; RV64-NEXT:    lui a0, 209715
2056; RV64-NEXT:    addiw a0, a0, 819
2057; RV64-NEXT:    vand.vx v12, v8, a0
2058; RV64-NEXT:    vsrl.vi v8, v8, 2
2059; RV64-NEXT:    vand.vx v8, v8, a0
2060; RV64-NEXT:    vadd.vv v8, v12, v8
2061; RV64-NEXT:    vsrl.vi v12, v8, 4
2062; RV64-NEXT:    vadd.vv v8, v8, v12
2063; RV64-NEXT:    lui a0, 61681
2064; RV64-NEXT:    addiw a0, a0, -241
2065; RV64-NEXT:    vand.vx v8, v8, a0
2066; RV64-NEXT:    lui a0, 4112
2067; RV64-NEXT:    addiw a0, a0, 257
2068; RV64-NEXT:    vmul.vx v8, v8, a0
2069; RV64-NEXT:    vsrl.vi v8, v8, 24
2070; RV64-NEXT:    ret
2071  %a = call <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 true)
2072  ret <vscale x 8 x i32> %a
2073}
2074
2075define <vscale x 16 x i32> @cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) {
2076; RV32-LABEL: cttz_zero_undef_nxv16i32:
2077; RV32:       # %bb.0:
2078; RV32-NEXT:    addi a0, zero, 1
2079; RV32-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
2080; RV32-NEXT:    vsub.vx v16, v8, a0
2081; RV32-NEXT:    vxor.vi v8, v8, -1
2082; RV32-NEXT:    vand.vv v8, v8, v16
2083; RV32-NEXT:    vsrl.vi v16, v8, 1
2084; RV32-NEXT:    lui a0, 349525
2085; RV32-NEXT:    addi a0, a0, 1365
2086; RV32-NEXT:    vand.vx v16, v16, a0
2087; RV32-NEXT:    vsub.vv v8, v8, v16
2088; RV32-NEXT:    lui a0, 209715
2089; RV32-NEXT:    addi a0, a0, 819
2090; RV32-NEXT:    vand.vx v16, v8, a0
2091; RV32-NEXT:    vsrl.vi v8, v8, 2
2092; RV32-NEXT:    vand.vx v8, v8, a0
2093; RV32-NEXT:    vadd.vv v8, v16, v8
2094; RV32-NEXT:    vsrl.vi v16, v8, 4
2095; RV32-NEXT:    vadd.vv v8, v8, v16
2096; RV32-NEXT:    lui a0, 61681
2097; RV32-NEXT:    addi a0, a0, -241
2098; RV32-NEXT:    vand.vx v8, v8, a0
2099; RV32-NEXT:    lui a0, 4112
2100; RV32-NEXT:    addi a0, a0, 257
2101; RV32-NEXT:    vmul.vx v8, v8, a0
2102; RV32-NEXT:    vsrl.vi v8, v8, 24
2103; RV32-NEXT:    ret
2104;
2105; RV64-LABEL: cttz_zero_undef_nxv16i32:
2106; RV64:       # %bb.0:
2107; RV64-NEXT:    addi a0, zero, 1
2108; RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
2109; RV64-NEXT:    vsub.vx v16, v8, a0
2110; RV64-NEXT:    vxor.vi v8, v8, -1
2111; RV64-NEXT:    vand.vv v8, v8, v16
2112; RV64-NEXT:    vsrl.vi v16, v8, 1
2113; RV64-NEXT:    lui a0, 349525
2114; RV64-NEXT:    addiw a0, a0, 1365
2115; RV64-NEXT:    vand.vx v16, v16, a0
2116; RV64-NEXT:    vsub.vv v8, v8, v16
2117; RV64-NEXT:    lui a0, 209715
2118; RV64-NEXT:    addiw a0, a0, 819
2119; RV64-NEXT:    vand.vx v16, v8, a0
2120; RV64-NEXT:    vsrl.vi v8, v8, 2
2121; RV64-NEXT:    vand.vx v8, v8, a0
2122; RV64-NEXT:    vadd.vv v8, v16, v8
2123; RV64-NEXT:    vsrl.vi v16, v8, 4
2124; RV64-NEXT:    vadd.vv v8, v8, v16
2125; RV64-NEXT:    lui a0, 61681
2126; RV64-NEXT:    addiw a0, a0, -241
2127; RV64-NEXT:    vand.vx v8, v8, a0
2128; RV64-NEXT:    lui a0, 4112
2129; RV64-NEXT:    addiw a0, a0, 257
2130; RV64-NEXT:    vmul.vx v8, v8, a0
2131; RV64-NEXT:    vsrl.vi v8, v8, 24
2132; RV64-NEXT:    ret
2133  %a = call <vscale x 16 x i32> @llvm.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 true)
2134  ret <vscale x 16 x i32> %a
2135}
2136
2137define <vscale x 1 x i64> @cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
2138; RV32-LABEL: cttz_zero_undef_nxv1i64:
2139; RV32:       # %bb.0:
2140; RV32-NEXT:    addi sp, sp, -16
2141; RV32-NEXT:    .cfi_def_cfa_offset 16
2142; RV32-NEXT:    lui a0, 349525
2143; RV32-NEXT:    addi a0, a0, 1365
2144; RV32-NEXT:    sw a0, 12(sp)
2145; RV32-NEXT:    sw a0, 8(sp)
2146; RV32-NEXT:    lui a0, 209715
2147; RV32-NEXT:    addi a0, a0, 819
2148; RV32-NEXT:    sw a0, 12(sp)
2149; RV32-NEXT:    sw a0, 8(sp)
2150; RV32-NEXT:    lui a0, 61681
2151; RV32-NEXT:    addi a0, a0, -241
2152; RV32-NEXT:    sw a0, 12(sp)
2153; RV32-NEXT:    sw a0, 8(sp)
2154; RV32-NEXT:    lui a0, 4112
2155; RV32-NEXT:    addi a0, a0, 257
2156; RV32-NEXT:    sw a0, 12(sp)
2157; RV32-NEXT:    sw a0, 8(sp)
2158; RV32-NEXT:    addi a0, zero, 1
2159; RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
2160; RV32-NEXT:    vsub.vx v9, v8, a0
2161; RV32-NEXT:    vxor.vi v8, v8, -1
2162; RV32-NEXT:    addi a0, sp, 8
2163; RV32-NEXT:    vlse64.v v10, (a0), zero
2164; RV32-NEXT:    vand.vv v8, v8, v9
2165; RV32-NEXT:    addi a0, sp, 8
2166; RV32-NEXT:    vlse64.v v9, (a0), zero
2167; RV32-NEXT:    vsrl.vi v11, v8, 1
2168; RV32-NEXT:    vand.vv v10, v11, v10
2169; RV32-NEXT:    vsub.vv v8, v8, v10
2170; RV32-NEXT:    vand.vv v10, v8, v9
2171; RV32-NEXT:    vsrl.vi v8, v8, 2
2172; RV32-NEXT:    vand.vv v8, v8, v9
2173; RV32-NEXT:    vadd.vv v8, v10, v8
2174; RV32-NEXT:    addi a0, sp, 8
2175; RV32-NEXT:    vlse64.v v9, (a0), zero
2176; RV32-NEXT:    addi a0, sp, 8
2177; RV32-NEXT:    vlse64.v v10, (a0), zero
2178; RV32-NEXT:    vsrl.vi v11, v8, 4
2179; RV32-NEXT:    vadd.vv v8, v8, v11
2180; RV32-NEXT:    vand.vv v8, v8, v9
2181; RV32-NEXT:    vmul.vv v8, v8, v10
2182; RV32-NEXT:    addi a0, zero, 56
2183; RV32-NEXT:    vsrl.vx v8, v8, a0
2184; RV32-NEXT:    addi sp, sp, 16
2185; RV32-NEXT:    ret
2186;
2187; RV64-LABEL: cttz_zero_undef_nxv1i64:
2188; RV64:       # %bb.0:
2189; RV64-NEXT:    addi a0, zero, 1
2190; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
2191; RV64-NEXT:    vsub.vx v9, v8, a0
2192; RV64-NEXT:    vxor.vi v8, v8, -1
2193; RV64-NEXT:    vand.vv v8, v8, v9
2194; RV64-NEXT:    vsrl.vi v9, v8, 1
2195; RV64-NEXT:    lui a0, 21845
2196; RV64-NEXT:    addiw a0, a0, 1365
2197; RV64-NEXT:    slli a0, a0, 12
2198; RV64-NEXT:    addi a0, a0, 1365
2199; RV64-NEXT:    slli a0, a0, 12
2200; RV64-NEXT:    addi a0, a0, 1365
2201; RV64-NEXT:    slli a0, a0, 12
2202; RV64-NEXT:    addi a0, a0, 1365
2203; RV64-NEXT:    vand.vx v9, v9, a0
2204; RV64-NEXT:    vsub.vv v8, v8, v9
2205; RV64-NEXT:    lui a0, 13107
2206; RV64-NEXT:    addiw a0, a0, 819
2207; RV64-NEXT:    slli a0, a0, 12
2208; RV64-NEXT:    addi a0, a0, 819
2209; RV64-NEXT:    slli a0, a0, 12
2210; RV64-NEXT:    addi a0, a0, 819
2211; RV64-NEXT:    slli a0, a0, 12
2212; RV64-NEXT:    addi a0, a0, 819
2213; RV64-NEXT:    vand.vx v9, v8, a0
2214; RV64-NEXT:    vsrl.vi v8, v8, 2
2215; RV64-NEXT:    vand.vx v8, v8, a0
2216; RV64-NEXT:    vadd.vv v8, v9, v8
2217; RV64-NEXT:    vsrl.vi v9, v8, 4
2218; RV64-NEXT:    vadd.vv v8, v8, v9
2219; RV64-NEXT:    lui a0, 3855
2220; RV64-NEXT:    addiw a0, a0, 241
2221; RV64-NEXT:    slli a0, a0, 12
2222; RV64-NEXT:    addi a0, a0, -241
2223; RV64-NEXT:    slli a0, a0, 12
2224; RV64-NEXT:    addi a0, a0, 241
2225; RV64-NEXT:    slli a0, a0, 12
2226; RV64-NEXT:    addi a0, a0, -241
2227; RV64-NEXT:    vand.vx v8, v8, a0
2228; RV64-NEXT:    lui a0, 4112
2229; RV64-NEXT:    addiw a0, a0, 257
2230; RV64-NEXT:    slli a0, a0, 16
2231; RV64-NEXT:    addi a0, a0, 257
2232; RV64-NEXT:    slli a0, a0, 16
2233; RV64-NEXT:    addi a0, a0, 257
2234; RV64-NEXT:    vmul.vx v8, v8, a0
2235; RV64-NEXT:    addi a0, zero, 56
2236; RV64-NEXT:    vsrl.vx v8, v8, a0
2237; RV64-NEXT:    ret
2238  %a = call <vscale x 1 x i64> @llvm.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 true)
2239  ret <vscale x 1 x i64> %a
2240}
2241
2242define <vscale x 2 x i64> @cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
2243; RV32-LABEL: cttz_zero_undef_nxv2i64:
2244; RV32:       # %bb.0:
2245; RV32-NEXT:    addi sp, sp, -16
2246; RV32-NEXT:    .cfi_def_cfa_offset 16
2247; RV32-NEXT:    lui a0, 349525
2248; RV32-NEXT:    addi a0, a0, 1365
2249; RV32-NEXT:    sw a0, 12(sp)
2250; RV32-NEXT:    sw a0, 8(sp)
2251; RV32-NEXT:    lui a0, 209715
2252; RV32-NEXT:    addi a0, a0, 819
2253; RV32-NEXT:    sw a0, 12(sp)
2254; RV32-NEXT:    sw a0, 8(sp)
2255; RV32-NEXT:    lui a0, 61681
2256; RV32-NEXT:    addi a0, a0, -241
2257; RV32-NEXT:    sw a0, 12(sp)
2258; RV32-NEXT:    sw a0, 8(sp)
2259; RV32-NEXT:    lui a0, 4112
2260; RV32-NEXT:    addi a0, a0, 257
2261; RV32-NEXT:    sw a0, 12(sp)
2262; RV32-NEXT:    sw a0, 8(sp)
2263; RV32-NEXT:    addi a0, zero, 1
2264; RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
2265; RV32-NEXT:    vsub.vx v10, v8, a0
2266; RV32-NEXT:    vxor.vi v8, v8, -1
2267; RV32-NEXT:    addi a0, sp, 8
2268; RV32-NEXT:    vlse64.v v12, (a0), zero
2269; RV32-NEXT:    vand.vv v8, v8, v10
2270; RV32-NEXT:    addi a0, sp, 8
2271; RV32-NEXT:    vlse64.v v10, (a0), zero
2272; RV32-NEXT:    vsrl.vi v14, v8, 1
2273; RV32-NEXT:    vand.vv v12, v14, v12
2274; RV32-NEXT:    vsub.vv v8, v8, v12
2275; RV32-NEXT:    vand.vv v12, v8, v10
2276; RV32-NEXT:    vsrl.vi v8, v8, 2
2277; RV32-NEXT:    vand.vv v8, v8, v10
2278; RV32-NEXT:    vadd.vv v8, v12, v8
2279; RV32-NEXT:    addi a0, sp, 8
2280; RV32-NEXT:    vlse64.v v10, (a0), zero
2281; RV32-NEXT:    addi a0, sp, 8
2282; RV32-NEXT:    vlse64.v v12, (a0), zero
2283; RV32-NEXT:    vsrl.vi v14, v8, 4
2284; RV32-NEXT:    vadd.vv v8, v8, v14
2285; RV32-NEXT:    vand.vv v8, v8, v10
2286; RV32-NEXT:    vmul.vv v8, v8, v12
2287; RV32-NEXT:    addi a0, zero, 56
2288; RV32-NEXT:    vsrl.vx v8, v8, a0
2289; RV32-NEXT:    addi sp, sp, 16
2290; RV32-NEXT:    ret
2291;
2292; RV64-LABEL: cttz_zero_undef_nxv2i64:
2293; RV64:       # %bb.0:
2294; RV64-NEXT:    addi a0, zero, 1
2295; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
2296; RV64-NEXT:    vsub.vx v10, v8, a0
2297; RV64-NEXT:    vxor.vi v8, v8, -1
2298; RV64-NEXT:    vand.vv v8, v8, v10
2299; RV64-NEXT:    vsrl.vi v10, v8, 1
2300; RV64-NEXT:    lui a0, 21845
2301; RV64-NEXT:    addiw a0, a0, 1365
2302; RV64-NEXT:    slli a0, a0, 12
2303; RV64-NEXT:    addi a0, a0, 1365
2304; RV64-NEXT:    slli a0, a0, 12
2305; RV64-NEXT:    addi a0, a0, 1365
2306; RV64-NEXT:    slli a0, a0, 12
2307; RV64-NEXT:    addi a0, a0, 1365
2308; RV64-NEXT:    vand.vx v10, v10, a0
2309; RV64-NEXT:    vsub.vv v8, v8, v10
2310; RV64-NEXT:    lui a0, 13107
2311; RV64-NEXT:    addiw a0, a0, 819
2312; RV64-NEXT:    slli a0, a0, 12
2313; RV64-NEXT:    addi a0, a0, 819
2314; RV64-NEXT:    slli a0, a0, 12
2315; RV64-NEXT:    addi a0, a0, 819
2316; RV64-NEXT:    slli a0, a0, 12
2317; RV64-NEXT:    addi a0, a0, 819
2318; RV64-NEXT:    vand.vx v10, v8, a0
2319; RV64-NEXT:    vsrl.vi v8, v8, 2
2320; RV64-NEXT:    vand.vx v8, v8, a0
2321; RV64-NEXT:    vadd.vv v8, v10, v8
2322; RV64-NEXT:    vsrl.vi v10, v8, 4
2323; RV64-NEXT:    vadd.vv v8, v8, v10
2324; RV64-NEXT:    lui a0, 3855
2325; RV64-NEXT:    addiw a0, a0, 241
2326; RV64-NEXT:    slli a0, a0, 12
2327; RV64-NEXT:    addi a0, a0, -241
2328; RV64-NEXT:    slli a0, a0, 12
2329; RV64-NEXT:    addi a0, a0, 241
2330; RV64-NEXT:    slli a0, a0, 12
2331; RV64-NEXT:    addi a0, a0, -241
2332; RV64-NEXT:    vand.vx v8, v8, a0
2333; RV64-NEXT:    lui a0, 4112
2334; RV64-NEXT:    addiw a0, a0, 257
2335; RV64-NEXT:    slli a0, a0, 16
2336; RV64-NEXT:    addi a0, a0, 257
2337; RV64-NEXT:    slli a0, a0, 16
2338; RV64-NEXT:    addi a0, a0, 257
2339; RV64-NEXT:    vmul.vx v8, v8, a0
2340; RV64-NEXT:    addi a0, zero, 56
2341; RV64-NEXT:    vsrl.vx v8, v8, a0
2342; RV64-NEXT:    ret
2343  %a = call <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 true)
2344  ret <vscale x 2 x i64> %a
2345}
2346
2347define <vscale x 4 x i64> @cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
2348; RV32-LABEL: cttz_zero_undef_nxv4i64:
2349; RV32:       # %bb.0:
2350; RV32-NEXT:    addi sp, sp, -16
2351; RV32-NEXT:    .cfi_def_cfa_offset 16
2352; RV32-NEXT:    lui a0, 349525
2353; RV32-NEXT:    addi a0, a0, 1365
2354; RV32-NEXT:    sw a0, 12(sp)
2355; RV32-NEXT:    sw a0, 8(sp)
2356; RV32-NEXT:    lui a0, 209715
2357; RV32-NEXT:    addi a0, a0, 819
2358; RV32-NEXT:    sw a0, 12(sp)
2359; RV32-NEXT:    sw a0, 8(sp)
2360; RV32-NEXT:    lui a0, 61681
2361; RV32-NEXT:    addi a0, a0, -241
2362; RV32-NEXT:    sw a0, 12(sp)
2363; RV32-NEXT:    sw a0, 8(sp)
2364; RV32-NEXT:    lui a0, 4112
2365; RV32-NEXT:    addi a0, a0, 257
2366; RV32-NEXT:    sw a0, 12(sp)
2367; RV32-NEXT:    sw a0, 8(sp)
2368; RV32-NEXT:    addi a0, zero, 1
2369; RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
2370; RV32-NEXT:    vsub.vx v12, v8, a0
2371; RV32-NEXT:    vxor.vi v8, v8, -1
2372; RV32-NEXT:    addi a0, sp, 8
2373; RV32-NEXT:    vlse64.v v16, (a0), zero
2374; RV32-NEXT:    vand.vv v8, v8, v12
2375; RV32-NEXT:    addi a0, sp, 8
2376; RV32-NEXT:    vlse64.v v12, (a0), zero
2377; RV32-NEXT:    vsrl.vi v20, v8, 1
2378; RV32-NEXT:    vand.vv v16, v20, v16
2379; RV32-NEXT:    vsub.vv v8, v8, v16
2380; RV32-NEXT:    vand.vv v16, v8, v12
2381; RV32-NEXT:    vsrl.vi v8, v8, 2
2382; RV32-NEXT:    vand.vv v8, v8, v12
2383; RV32-NEXT:    vadd.vv v8, v16, v8
2384; RV32-NEXT:    addi a0, sp, 8
2385; RV32-NEXT:    vlse64.v v12, (a0), zero
2386; RV32-NEXT:    addi a0, sp, 8
2387; RV32-NEXT:    vlse64.v v16, (a0), zero
2388; RV32-NEXT:    vsrl.vi v20, v8, 4
2389; RV32-NEXT:    vadd.vv v8, v8, v20
2390; RV32-NEXT:    vand.vv v8, v8, v12
2391; RV32-NEXT:    vmul.vv v8, v8, v16
2392; RV32-NEXT:    addi a0, zero, 56
2393; RV32-NEXT:    vsrl.vx v8, v8, a0
2394; RV32-NEXT:    addi sp, sp, 16
2395; RV32-NEXT:    ret
2396;
2397; RV64-LABEL: cttz_zero_undef_nxv4i64:
2398; RV64:       # %bb.0:
2399; RV64-NEXT:    addi a0, zero, 1
2400; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
2401; RV64-NEXT:    vsub.vx v12, v8, a0
2402; RV64-NEXT:    vxor.vi v8, v8, -1
2403; RV64-NEXT:    vand.vv v8, v8, v12
2404; RV64-NEXT:    vsrl.vi v12, v8, 1
2405; RV64-NEXT:    lui a0, 21845
2406; RV64-NEXT:    addiw a0, a0, 1365
2407; RV64-NEXT:    slli a0, a0, 12
2408; RV64-NEXT:    addi a0, a0, 1365
2409; RV64-NEXT:    slli a0, a0, 12
2410; RV64-NEXT:    addi a0, a0, 1365
2411; RV64-NEXT:    slli a0, a0, 12
2412; RV64-NEXT:    addi a0, a0, 1365
2413; RV64-NEXT:    vand.vx v12, v12, a0
2414; RV64-NEXT:    vsub.vv v8, v8, v12
2415; RV64-NEXT:    lui a0, 13107
2416; RV64-NEXT:    addiw a0, a0, 819
2417; RV64-NEXT:    slli a0, a0, 12
2418; RV64-NEXT:    addi a0, a0, 819
2419; RV64-NEXT:    slli a0, a0, 12
2420; RV64-NEXT:    addi a0, a0, 819
2421; RV64-NEXT:    slli a0, a0, 12
2422; RV64-NEXT:    addi a0, a0, 819
2423; RV64-NEXT:    vand.vx v12, v8, a0
2424; RV64-NEXT:    vsrl.vi v8, v8, 2
2425; RV64-NEXT:    vand.vx v8, v8, a0
2426; RV64-NEXT:    vadd.vv v8, v12, v8
2427; RV64-NEXT:    vsrl.vi v12, v8, 4
2428; RV64-NEXT:    vadd.vv v8, v8, v12
2429; RV64-NEXT:    lui a0, 3855
2430; RV64-NEXT:    addiw a0, a0, 241
2431; RV64-NEXT:    slli a0, a0, 12
2432; RV64-NEXT:    addi a0, a0, -241
2433; RV64-NEXT:    slli a0, a0, 12
2434; RV64-NEXT:    addi a0, a0, 241
2435; RV64-NEXT:    slli a0, a0, 12
2436; RV64-NEXT:    addi a0, a0, -241
2437; RV64-NEXT:    vand.vx v8, v8, a0
2438; RV64-NEXT:    lui a0, 4112
2439; RV64-NEXT:    addiw a0, a0, 257
2440; RV64-NEXT:    slli a0, a0, 16
2441; RV64-NEXT:    addi a0, a0, 257
2442; RV64-NEXT:    slli a0, a0, 16
2443; RV64-NEXT:    addi a0, a0, 257
2444; RV64-NEXT:    vmul.vx v8, v8, a0
2445; RV64-NEXT:    addi a0, zero, 56
2446; RV64-NEXT:    vsrl.vx v8, v8, a0
2447; RV64-NEXT:    ret
2448  %a = call <vscale x 4 x i64> @llvm.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 true)
2449  ret <vscale x 4 x i64> %a
2450}
2451
2452define <vscale x 8 x i64> @cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
2453; RV32-LABEL: cttz_zero_undef_nxv8i64:
2454; RV32:       # %bb.0:
2455; RV32-NEXT:    addi sp, sp, -16
2456; RV32-NEXT:    .cfi_def_cfa_offset 16
2457; RV32-NEXT:    lui a0, 349525
2458; RV32-NEXT:    addi a0, a0, 1365
2459; RV32-NEXT:    sw a0, 12(sp)
2460; RV32-NEXT:    sw a0, 8(sp)
2461; RV32-NEXT:    lui a0, 209715
2462; RV32-NEXT:    addi a0, a0, 819
2463; RV32-NEXT:    sw a0, 12(sp)
2464; RV32-NEXT:    sw a0, 8(sp)
2465; RV32-NEXT:    lui a0, 61681
2466; RV32-NEXT:    addi a0, a0, -241
2467; RV32-NEXT:    sw a0, 12(sp)
2468; RV32-NEXT:    sw a0, 8(sp)
2469; RV32-NEXT:    lui a0, 4112
2470; RV32-NEXT:    addi a0, a0, 257
2471; RV32-NEXT:    sw a0, 12(sp)
2472; RV32-NEXT:    sw a0, 8(sp)
2473; RV32-NEXT:    addi a0, zero, 1
2474; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
2475; RV32-NEXT:    vsub.vx v16, v8, a0
2476; RV32-NEXT:    vxor.vi v8, v8, -1
2477; RV32-NEXT:    addi a0, sp, 8
2478; RV32-NEXT:    vlse64.v v24, (a0), zero
2479; RV32-NEXT:    vand.vv v8, v8, v16
2480; RV32-NEXT:    addi a0, sp, 8
2481; RV32-NEXT:    vlse64.v v16, (a0), zero
2482; RV32-NEXT:    vsrl.vi v0, v8, 1
2483; RV32-NEXT:    vand.vv v24, v0, v24
2484; RV32-NEXT:    vsub.vv v8, v8, v24
2485; RV32-NEXT:    vand.vv v24, v8, v16
2486; RV32-NEXT:    vsrl.vi v8, v8, 2
2487; RV32-NEXT:    vand.vv v8, v8, v16
2488; RV32-NEXT:    vadd.vv v8, v24, v8
2489; RV32-NEXT:    addi a0, sp, 8
2490; RV32-NEXT:    vlse64.v v16, (a0), zero
2491; RV32-NEXT:    addi a0, sp, 8
2492; RV32-NEXT:    vlse64.v v24, (a0), zero
2493; RV32-NEXT:    vsrl.vi v0, v8, 4
2494; RV32-NEXT:    vadd.vv v8, v8, v0
2495; RV32-NEXT:    vand.vv v8, v8, v16
2496; RV32-NEXT:    vmul.vv v8, v8, v24
2497; RV32-NEXT:    addi a0, zero, 56
2498; RV32-NEXT:    vsrl.vx v8, v8, a0
2499; RV32-NEXT:    addi sp, sp, 16
2500; RV32-NEXT:    ret
2501;
2502; RV64-LABEL: cttz_zero_undef_nxv8i64:
2503; RV64:       # %bb.0:
2504; RV64-NEXT:    addi a0, zero, 1
2505; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
2506; RV64-NEXT:    vsub.vx v16, v8, a0
2507; RV64-NEXT:    vxor.vi v8, v8, -1
2508; RV64-NEXT:    vand.vv v8, v8, v16
2509; RV64-NEXT:    vsrl.vi v16, v8, 1
2510; RV64-NEXT:    lui a0, 21845
2511; RV64-NEXT:    addiw a0, a0, 1365
2512; RV64-NEXT:    slli a0, a0, 12
2513; RV64-NEXT:    addi a0, a0, 1365
2514; RV64-NEXT:    slli a0, a0, 12
2515; RV64-NEXT:    addi a0, a0, 1365
2516; RV64-NEXT:    slli a0, a0, 12
2517; RV64-NEXT:    addi a0, a0, 1365
2518; RV64-NEXT:    vand.vx v16, v16, a0
2519; RV64-NEXT:    vsub.vv v8, v8, v16
2520; RV64-NEXT:    lui a0, 13107
2521; RV64-NEXT:    addiw a0, a0, 819
2522; RV64-NEXT:    slli a0, a0, 12
2523; RV64-NEXT:    addi a0, a0, 819
2524; RV64-NEXT:    slli a0, a0, 12
2525; RV64-NEXT:    addi a0, a0, 819
2526; RV64-NEXT:    slli a0, a0, 12
2527; RV64-NEXT:    addi a0, a0, 819
2528; RV64-NEXT:    vand.vx v16, v8, a0
2529; RV64-NEXT:    vsrl.vi v8, v8, 2
2530; RV64-NEXT:    vand.vx v8, v8, a0
2531; RV64-NEXT:    vadd.vv v8, v16, v8
2532; RV64-NEXT:    vsrl.vi v16, v8, 4
2533; RV64-NEXT:    vadd.vv v8, v8, v16
2534; RV64-NEXT:    lui a0, 3855
2535; RV64-NEXT:    addiw a0, a0, 241
2536; RV64-NEXT:    slli a0, a0, 12
2537; RV64-NEXT:    addi a0, a0, -241
2538; RV64-NEXT:    slli a0, a0, 12
2539; RV64-NEXT:    addi a0, a0, 241
2540; RV64-NEXT:    slli a0, a0, 12
2541; RV64-NEXT:    addi a0, a0, -241
2542; RV64-NEXT:    vand.vx v8, v8, a0
2543; RV64-NEXT:    lui a0, 4112
2544; RV64-NEXT:    addiw a0, a0, 257
2545; RV64-NEXT:    slli a0, a0, 16
2546; RV64-NEXT:    addi a0, a0, 257
2547; RV64-NEXT:    slli a0, a0, 16
2548; RV64-NEXT:    addi a0, a0, 257
2549; RV64-NEXT:    vmul.vx v8, v8, a0
2550; RV64-NEXT:    addi a0, zero, 56
2551; RV64-NEXT:    vsrl.vx v8, v8, a0
2552; RV64-NEXT:    ret
2553  %a = call <vscale x 8 x i64> @llvm.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 true)
2554  ret <vscale x 8 x i64> %a
2555}
2556