1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32I
3; RUN: llc -mtriple=riscv64 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64I
4; RUN: llc -mtriple=riscv32 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32D
5; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64D
6
7define <vscale x 1 x i8> @cttz_nxv1i8(<vscale x 1 x i8> %va) {
8; RV32I-LABEL: cttz_nxv1i8:
9; RV32I:       # %bb.0:
10; RV32I-NEXT:    li a0, 1
11; RV32I-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
12; RV32I-NEXT:    vsub.vx v9, v8, a0
13; RV32I-NEXT:    vnot.v v8, v8
14; RV32I-NEXT:    vand.vv v8, v8, v9
15; RV32I-NEXT:    vsrl.vi v9, v8, 1
16; RV32I-NEXT:    li a0, 85
17; RV32I-NEXT:    vand.vx v9, v9, a0
18; RV32I-NEXT:    vsub.vv v8, v8, v9
19; RV32I-NEXT:    li a0, 51
20; RV32I-NEXT:    vand.vx v9, v8, a0
21; RV32I-NEXT:    vsrl.vi v8, v8, 2
22; RV32I-NEXT:    vand.vx v8, v8, a0
23; RV32I-NEXT:    vadd.vv v8, v9, v8
24; RV32I-NEXT:    vsrl.vi v9, v8, 4
25; RV32I-NEXT:    vadd.vv v8, v8, v9
26; RV32I-NEXT:    vand.vi v8, v8, 15
27; RV32I-NEXT:    ret
28;
29; RV64I-LABEL: cttz_nxv1i8:
30; RV64I:       # %bb.0:
31; RV64I-NEXT:    li a0, 1
32; RV64I-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
33; RV64I-NEXT:    vsub.vx v9, v8, a0
34; RV64I-NEXT:    vnot.v v8, v8
35; RV64I-NEXT:    vand.vv v8, v8, v9
36; RV64I-NEXT:    vsrl.vi v9, v8, 1
37; RV64I-NEXT:    li a0, 85
38; RV64I-NEXT:    vand.vx v9, v9, a0
39; RV64I-NEXT:    vsub.vv v8, v8, v9
40; RV64I-NEXT:    li a0, 51
41; RV64I-NEXT:    vand.vx v9, v8, a0
42; RV64I-NEXT:    vsrl.vi v8, v8, 2
43; RV64I-NEXT:    vand.vx v8, v8, a0
44; RV64I-NEXT:    vadd.vv v8, v9, v8
45; RV64I-NEXT:    vsrl.vi v9, v8, 4
46; RV64I-NEXT:    vadd.vv v8, v8, v9
47; RV64I-NEXT:    vand.vi v8, v8, 15
48; RV64I-NEXT:    ret
49;
50; RV32D-LABEL: cttz_nxv1i8:
51; RV32D:       # %bb.0:
52; RV32D-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
53; RV32D-NEXT:    vmseq.vx v0, v8, zero
54; RV32D-NEXT:    vrsub.vi v9, v8, 0
55; RV32D-NEXT:    vand.vv v8, v8, v9
56; RV32D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
57; RV32D-NEXT:    vzext.vf4 v9, v8
58; RV32D-NEXT:    vfcvt.f.xu.v v8, v9
59; RV32D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
60; RV32D-NEXT:    vnsrl.wi v8, v8, 23
61; RV32D-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
62; RV32D-NEXT:    vncvt.x.x.w v8, v8
63; RV32D-NEXT:    li a0, 127
64; RV32D-NEXT:    vsub.vx v8, v8, a0
65; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
66; RV32D-NEXT:    ret
67;
68; RV64D-LABEL: cttz_nxv1i8:
69; RV64D:       # %bb.0:
70; RV64D-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
71; RV64D-NEXT:    vmseq.vx v0, v8, zero
72; RV64D-NEXT:    vrsub.vi v9, v8, 0
73; RV64D-NEXT:    vand.vv v8, v8, v9
74; RV64D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
75; RV64D-NEXT:    vzext.vf4 v9, v8
76; RV64D-NEXT:    vfcvt.f.xu.v v8, v9
77; RV64D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
78; RV64D-NEXT:    vnsrl.wi v8, v8, 23
79; RV64D-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
80; RV64D-NEXT:    vncvt.x.x.w v8, v8
81; RV64D-NEXT:    li a0, 127
82; RV64D-NEXT:    vsub.vx v8, v8, a0
83; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
84; RV64D-NEXT:    ret
85  %a = call <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 false)
86  ret <vscale x 1 x i8> %a
87}
88declare <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8>, i1)
89
90define <vscale x 2 x i8> @cttz_nxv2i8(<vscale x 2 x i8> %va) {
91; RV32I-LABEL: cttz_nxv2i8:
92; RV32I:       # %bb.0:
93; RV32I-NEXT:    li a0, 1
94; RV32I-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
95; RV32I-NEXT:    vsub.vx v9, v8, a0
96; RV32I-NEXT:    vnot.v v8, v8
97; RV32I-NEXT:    vand.vv v8, v8, v9
98; RV32I-NEXT:    vsrl.vi v9, v8, 1
99; RV32I-NEXT:    li a0, 85
100; RV32I-NEXT:    vand.vx v9, v9, a0
101; RV32I-NEXT:    vsub.vv v8, v8, v9
102; RV32I-NEXT:    li a0, 51
103; RV32I-NEXT:    vand.vx v9, v8, a0
104; RV32I-NEXT:    vsrl.vi v8, v8, 2
105; RV32I-NEXT:    vand.vx v8, v8, a0
106; RV32I-NEXT:    vadd.vv v8, v9, v8
107; RV32I-NEXT:    vsrl.vi v9, v8, 4
108; RV32I-NEXT:    vadd.vv v8, v8, v9
109; RV32I-NEXT:    vand.vi v8, v8, 15
110; RV32I-NEXT:    ret
111;
112; RV64I-LABEL: cttz_nxv2i8:
113; RV64I:       # %bb.0:
114; RV64I-NEXT:    li a0, 1
115; RV64I-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
116; RV64I-NEXT:    vsub.vx v9, v8, a0
117; RV64I-NEXT:    vnot.v v8, v8
118; RV64I-NEXT:    vand.vv v8, v8, v9
119; RV64I-NEXT:    vsrl.vi v9, v8, 1
120; RV64I-NEXT:    li a0, 85
121; RV64I-NEXT:    vand.vx v9, v9, a0
122; RV64I-NEXT:    vsub.vv v8, v8, v9
123; RV64I-NEXT:    li a0, 51
124; RV64I-NEXT:    vand.vx v9, v8, a0
125; RV64I-NEXT:    vsrl.vi v8, v8, 2
126; RV64I-NEXT:    vand.vx v8, v8, a0
127; RV64I-NEXT:    vadd.vv v8, v9, v8
128; RV64I-NEXT:    vsrl.vi v9, v8, 4
129; RV64I-NEXT:    vadd.vv v8, v8, v9
130; RV64I-NEXT:    vand.vi v8, v8, 15
131; RV64I-NEXT:    ret
132;
133; RV32D-LABEL: cttz_nxv2i8:
134; RV32D:       # %bb.0:
135; RV32D-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
136; RV32D-NEXT:    vmseq.vx v0, v8, zero
137; RV32D-NEXT:    vrsub.vi v9, v8, 0
138; RV32D-NEXT:    vand.vv v8, v8, v9
139; RV32D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
140; RV32D-NEXT:    vzext.vf4 v9, v8
141; RV32D-NEXT:    vfcvt.f.xu.v v8, v9
142; RV32D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
143; RV32D-NEXT:    vnsrl.wi v8, v8, 23
144; RV32D-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
145; RV32D-NEXT:    vncvt.x.x.w v8, v8
146; RV32D-NEXT:    li a0, 127
147; RV32D-NEXT:    vsub.vx v8, v8, a0
148; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
149; RV32D-NEXT:    ret
150;
151; RV64D-LABEL: cttz_nxv2i8:
152; RV64D:       # %bb.0:
153; RV64D-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
154; RV64D-NEXT:    vmseq.vx v0, v8, zero
155; RV64D-NEXT:    vrsub.vi v9, v8, 0
156; RV64D-NEXT:    vand.vv v8, v8, v9
157; RV64D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
158; RV64D-NEXT:    vzext.vf4 v9, v8
159; RV64D-NEXT:    vfcvt.f.xu.v v8, v9
160; RV64D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
161; RV64D-NEXT:    vnsrl.wi v8, v8, 23
162; RV64D-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
163; RV64D-NEXT:    vncvt.x.x.w v8, v8
164; RV64D-NEXT:    li a0, 127
165; RV64D-NEXT:    vsub.vx v8, v8, a0
166; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
167; RV64D-NEXT:    ret
168  %a = call <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 false)
169  ret <vscale x 2 x i8> %a
170}
171declare <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8>, i1)
172
173define <vscale x 4 x i8> @cttz_nxv4i8(<vscale x 4 x i8> %va) {
174; RV32I-LABEL: cttz_nxv4i8:
175; RV32I:       # %bb.0:
176; RV32I-NEXT:    li a0, 1
177; RV32I-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
178; RV32I-NEXT:    vsub.vx v9, v8, a0
179; RV32I-NEXT:    vnot.v v8, v8
180; RV32I-NEXT:    vand.vv v8, v8, v9
181; RV32I-NEXT:    vsrl.vi v9, v8, 1
182; RV32I-NEXT:    li a0, 85
183; RV32I-NEXT:    vand.vx v9, v9, a0
184; RV32I-NEXT:    vsub.vv v8, v8, v9
185; RV32I-NEXT:    li a0, 51
186; RV32I-NEXT:    vand.vx v9, v8, a0
187; RV32I-NEXT:    vsrl.vi v8, v8, 2
188; RV32I-NEXT:    vand.vx v8, v8, a0
189; RV32I-NEXT:    vadd.vv v8, v9, v8
190; RV32I-NEXT:    vsrl.vi v9, v8, 4
191; RV32I-NEXT:    vadd.vv v8, v8, v9
192; RV32I-NEXT:    vand.vi v8, v8, 15
193; RV32I-NEXT:    ret
194;
195; RV64I-LABEL: cttz_nxv4i8:
196; RV64I:       # %bb.0:
197; RV64I-NEXT:    li a0, 1
198; RV64I-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
199; RV64I-NEXT:    vsub.vx v9, v8, a0
200; RV64I-NEXT:    vnot.v v8, v8
201; RV64I-NEXT:    vand.vv v8, v8, v9
202; RV64I-NEXT:    vsrl.vi v9, v8, 1
203; RV64I-NEXT:    li a0, 85
204; RV64I-NEXT:    vand.vx v9, v9, a0
205; RV64I-NEXT:    vsub.vv v8, v8, v9
206; RV64I-NEXT:    li a0, 51
207; RV64I-NEXT:    vand.vx v9, v8, a0
208; RV64I-NEXT:    vsrl.vi v8, v8, 2
209; RV64I-NEXT:    vand.vx v8, v8, a0
210; RV64I-NEXT:    vadd.vv v8, v9, v8
211; RV64I-NEXT:    vsrl.vi v9, v8, 4
212; RV64I-NEXT:    vadd.vv v8, v8, v9
213; RV64I-NEXT:    vand.vi v8, v8, 15
214; RV64I-NEXT:    ret
215;
216; RV32D-LABEL: cttz_nxv4i8:
217; RV32D:       # %bb.0:
218; RV32D-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
219; RV32D-NEXT:    vmseq.vx v0, v8, zero
220; RV32D-NEXT:    vrsub.vi v9, v8, 0
221; RV32D-NEXT:    vand.vv v8, v8, v9
222; RV32D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
223; RV32D-NEXT:    vzext.vf4 v10, v8
224; RV32D-NEXT:    vfcvt.f.xu.v v8, v10
225; RV32D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
226; RV32D-NEXT:    vnsrl.wi v10, v8, 23
227; RV32D-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
228; RV32D-NEXT:    vncvt.x.x.w v8, v10
229; RV32D-NEXT:    li a0, 127
230; RV32D-NEXT:    vsub.vx v8, v8, a0
231; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
232; RV32D-NEXT:    ret
233;
234; RV64D-LABEL: cttz_nxv4i8:
235; RV64D:       # %bb.0:
236; RV64D-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
237; RV64D-NEXT:    vmseq.vx v0, v8, zero
238; RV64D-NEXT:    vrsub.vi v9, v8, 0
239; RV64D-NEXT:    vand.vv v8, v8, v9
240; RV64D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
241; RV64D-NEXT:    vzext.vf4 v10, v8
242; RV64D-NEXT:    vfcvt.f.xu.v v8, v10
243; RV64D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
244; RV64D-NEXT:    vnsrl.wi v10, v8, 23
245; RV64D-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
246; RV64D-NEXT:    vncvt.x.x.w v8, v10
247; RV64D-NEXT:    li a0, 127
248; RV64D-NEXT:    vsub.vx v8, v8, a0
249; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
250; RV64D-NEXT:    ret
251  %a = call <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 false)
252  ret <vscale x 4 x i8> %a
253}
254declare <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8>, i1)
255
256define <vscale x 8 x i8> @cttz_nxv8i8(<vscale x 8 x i8> %va) {
257; RV32I-LABEL: cttz_nxv8i8:
258; RV32I:       # %bb.0:
259; RV32I-NEXT:    li a0, 1
260; RV32I-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
261; RV32I-NEXT:    vsub.vx v9, v8, a0
262; RV32I-NEXT:    vnot.v v8, v8
263; RV32I-NEXT:    vand.vv v8, v8, v9
264; RV32I-NEXT:    vsrl.vi v9, v8, 1
265; RV32I-NEXT:    li a0, 85
266; RV32I-NEXT:    vand.vx v9, v9, a0
267; RV32I-NEXT:    vsub.vv v8, v8, v9
268; RV32I-NEXT:    li a0, 51
269; RV32I-NEXT:    vand.vx v9, v8, a0
270; RV32I-NEXT:    vsrl.vi v8, v8, 2
271; RV32I-NEXT:    vand.vx v8, v8, a0
272; RV32I-NEXT:    vadd.vv v8, v9, v8
273; RV32I-NEXT:    vsrl.vi v9, v8, 4
274; RV32I-NEXT:    vadd.vv v8, v8, v9
275; RV32I-NEXT:    vand.vi v8, v8, 15
276; RV32I-NEXT:    ret
277;
278; RV64I-LABEL: cttz_nxv8i8:
279; RV64I:       # %bb.0:
280; RV64I-NEXT:    li a0, 1
281; RV64I-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
282; RV64I-NEXT:    vsub.vx v9, v8, a0
283; RV64I-NEXT:    vnot.v v8, v8
284; RV64I-NEXT:    vand.vv v8, v8, v9
285; RV64I-NEXT:    vsrl.vi v9, v8, 1
286; RV64I-NEXT:    li a0, 85
287; RV64I-NEXT:    vand.vx v9, v9, a0
288; RV64I-NEXT:    vsub.vv v8, v8, v9
289; RV64I-NEXT:    li a0, 51
290; RV64I-NEXT:    vand.vx v9, v8, a0
291; RV64I-NEXT:    vsrl.vi v8, v8, 2
292; RV64I-NEXT:    vand.vx v8, v8, a0
293; RV64I-NEXT:    vadd.vv v8, v9, v8
294; RV64I-NEXT:    vsrl.vi v9, v8, 4
295; RV64I-NEXT:    vadd.vv v8, v8, v9
296; RV64I-NEXT:    vand.vi v8, v8, 15
297; RV64I-NEXT:    ret
298;
299; RV32D-LABEL: cttz_nxv8i8:
300; RV32D:       # %bb.0:
301; RV32D-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
302; RV32D-NEXT:    vmseq.vx v0, v8, zero
303; RV32D-NEXT:    vrsub.vi v9, v8, 0
304; RV32D-NEXT:    vand.vv v8, v8, v9
305; RV32D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
306; RV32D-NEXT:    vzext.vf4 v12, v8
307; RV32D-NEXT:    vfcvt.f.xu.v v8, v12
308; RV32D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
309; RV32D-NEXT:    vnsrl.wi v12, v8, 23
310; RV32D-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
311; RV32D-NEXT:    vncvt.x.x.w v8, v12
312; RV32D-NEXT:    li a0, 127
313; RV32D-NEXT:    vsub.vx v8, v8, a0
314; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
315; RV32D-NEXT:    ret
316;
317; RV64D-LABEL: cttz_nxv8i8:
318; RV64D:       # %bb.0:
319; RV64D-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
320; RV64D-NEXT:    vmseq.vx v0, v8, zero
321; RV64D-NEXT:    vrsub.vi v9, v8, 0
322; RV64D-NEXT:    vand.vv v8, v8, v9
323; RV64D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
324; RV64D-NEXT:    vzext.vf4 v12, v8
325; RV64D-NEXT:    vfcvt.f.xu.v v8, v12
326; RV64D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
327; RV64D-NEXT:    vnsrl.wi v12, v8, 23
328; RV64D-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
329; RV64D-NEXT:    vncvt.x.x.w v8, v12
330; RV64D-NEXT:    li a0, 127
331; RV64D-NEXT:    vsub.vx v8, v8, a0
332; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
333; RV64D-NEXT:    ret
334  %a = call <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 false)
335  ret <vscale x 8 x i8> %a
336}
337declare <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8>, i1)
338
339define <vscale x 16 x i8> @cttz_nxv16i8(<vscale x 16 x i8> %va) {
340; RV32I-LABEL: cttz_nxv16i8:
341; RV32I:       # %bb.0:
342; RV32I-NEXT:    li a0, 1
343; RV32I-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
344; RV32I-NEXT:    vsub.vx v10, v8, a0
345; RV32I-NEXT:    vnot.v v8, v8
346; RV32I-NEXT:    vand.vv v8, v8, v10
347; RV32I-NEXT:    vsrl.vi v10, v8, 1
348; RV32I-NEXT:    li a0, 85
349; RV32I-NEXT:    vand.vx v10, v10, a0
350; RV32I-NEXT:    vsub.vv v8, v8, v10
351; RV32I-NEXT:    li a0, 51
352; RV32I-NEXT:    vand.vx v10, v8, a0
353; RV32I-NEXT:    vsrl.vi v8, v8, 2
354; RV32I-NEXT:    vand.vx v8, v8, a0
355; RV32I-NEXT:    vadd.vv v8, v10, v8
356; RV32I-NEXT:    vsrl.vi v10, v8, 4
357; RV32I-NEXT:    vadd.vv v8, v8, v10
358; RV32I-NEXT:    vand.vi v8, v8, 15
359; RV32I-NEXT:    ret
360;
361; RV64I-LABEL: cttz_nxv16i8:
362; RV64I:       # %bb.0:
363; RV64I-NEXT:    li a0, 1
364; RV64I-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
365; RV64I-NEXT:    vsub.vx v10, v8, a0
366; RV64I-NEXT:    vnot.v v8, v8
367; RV64I-NEXT:    vand.vv v8, v8, v10
368; RV64I-NEXT:    vsrl.vi v10, v8, 1
369; RV64I-NEXT:    li a0, 85
370; RV64I-NEXT:    vand.vx v10, v10, a0
371; RV64I-NEXT:    vsub.vv v8, v8, v10
372; RV64I-NEXT:    li a0, 51
373; RV64I-NEXT:    vand.vx v10, v8, a0
374; RV64I-NEXT:    vsrl.vi v8, v8, 2
375; RV64I-NEXT:    vand.vx v8, v8, a0
376; RV64I-NEXT:    vadd.vv v8, v10, v8
377; RV64I-NEXT:    vsrl.vi v10, v8, 4
378; RV64I-NEXT:    vadd.vv v8, v8, v10
379; RV64I-NEXT:    vand.vi v8, v8, 15
380; RV64I-NEXT:    ret
381;
382; RV32D-LABEL: cttz_nxv16i8:
383; RV32D:       # %bb.0:
384; RV32D-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
385; RV32D-NEXT:    vmseq.vx v0, v8, zero
386; RV32D-NEXT:    vrsub.vi v10, v8, 0
387; RV32D-NEXT:    vand.vv v8, v8, v10
388; RV32D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
389; RV32D-NEXT:    vzext.vf4 v16, v8
390; RV32D-NEXT:    vfcvt.f.xu.v v8, v16
391; RV32D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
392; RV32D-NEXT:    vnsrl.wi v16, v8, 23
393; RV32D-NEXT:    vsetvli zero, zero, e8, m2, ta, mu
394; RV32D-NEXT:    vncvt.x.x.w v8, v16
395; RV32D-NEXT:    li a0, 127
396; RV32D-NEXT:    vsub.vx v8, v8, a0
397; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
398; RV32D-NEXT:    ret
399;
400; RV64D-LABEL: cttz_nxv16i8:
401; RV64D:       # %bb.0:
402; RV64D-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
403; RV64D-NEXT:    vmseq.vx v0, v8, zero
404; RV64D-NEXT:    vrsub.vi v10, v8, 0
405; RV64D-NEXT:    vand.vv v8, v8, v10
406; RV64D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
407; RV64D-NEXT:    vzext.vf4 v16, v8
408; RV64D-NEXT:    vfcvt.f.xu.v v8, v16
409; RV64D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
410; RV64D-NEXT:    vnsrl.wi v16, v8, 23
411; RV64D-NEXT:    vsetvli zero, zero, e8, m2, ta, mu
412; RV64D-NEXT:    vncvt.x.x.w v8, v16
413; RV64D-NEXT:    li a0, 127
414; RV64D-NEXT:    vsub.vx v8, v8, a0
415; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
416; RV64D-NEXT:    ret
417  %a = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 false)
418  ret <vscale x 16 x i8> %a
419}
420declare <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8>, i1)
421
422define <vscale x 32 x i8> @cttz_nxv32i8(<vscale x 32 x i8> %va) {
423; CHECK-LABEL: cttz_nxv32i8:
424; CHECK:       # %bb.0:
425; CHECK-NEXT:    li a0, 1
426; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
427; CHECK-NEXT:    vsub.vx v12, v8, a0
428; CHECK-NEXT:    vnot.v v8, v8
429; CHECK-NEXT:    vand.vv v8, v8, v12
430; CHECK-NEXT:    vsrl.vi v12, v8, 1
431; CHECK-NEXT:    li a0, 85
432; CHECK-NEXT:    vand.vx v12, v12, a0
433; CHECK-NEXT:    vsub.vv v8, v8, v12
434; CHECK-NEXT:    li a0, 51
435; CHECK-NEXT:    vand.vx v12, v8, a0
436; CHECK-NEXT:    vsrl.vi v8, v8, 2
437; CHECK-NEXT:    vand.vx v8, v8, a0
438; CHECK-NEXT:    vadd.vv v8, v12, v8
439; CHECK-NEXT:    vsrl.vi v12, v8, 4
440; CHECK-NEXT:    vadd.vv v8, v8, v12
441; CHECK-NEXT:    vand.vi v8, v8, 15
442; CHECK-NEXT:    ret
443  %a = call <vscale x 32 x i8> @llvm.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 false)
444  ret <vscale x 32 x i8> %a
445}
446declare <vscale x 32 x i8> @llvm.cttz.nxv32i8(<vscale x 32 x i8>, i1)
447
448define <vscale x 64 x i8> @cttz_nxv64i8(<vscale x 64 x i8> %va) {
449; CHECK-LABEL: cttz_nxv64i8:
450; CHECK:       # %bb.0:
451; CHECK-NEXT:    li a0, 1
452; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
453; CHECK-NEXT:    vsub.vx v16, v8, a0
454; CHECK-NEXT:    vnot.v v8, v8
455; CHECK-NEXT:    vand.vv v8, v8, v16
456; CHECK-NEXT:    vsrl.vi v16, v8, 1
457; CHECK-NEXT:    li a0, 85
458; CHECK-NEXT:    vand.vx v16, v16, a0
459; CHECK-NEXT:    vsub.vv v8, v8, v16
460; CHECK-NEXT:    li a0, 51
461; CHECK-NEXT:    vand.vx v16, v8, a0
462; CHECK-NEXT:    vsrl.vi v8, v8, 2
463; CHECK-NEXT:    vand.vx v8, v8, a0
464; CHECK-NEXT:    vadd.vv v8, v16, v8
465; CHECK-NEXT:    vsrl.vi v16, v8, 4
466; CHECK-NEXT:    vadd.vv v8, v8, v16
467; CHECK-NEXT:    vand.vi v8, v8, 15
468; CHECK-NEXT:    ret
469  %a = call <vscale x 64 x i8> @llvm.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 false)
470  ret <vscale x 64 x i8> %a
471}
472declare <vscale x 64 x i8> @llvm.cttz.nxv64i8(<vscale x 64 x i8>, i1)
473
474define <vscale x 1 x i16> @cttz_nxv1i16(<vscale x 1 x i16> %va) {
475; RV32I-LABEL: cttz_nxv1i16:
476; RV32I:       # %bb.0:
477; RV32I-NEXT:    li a0, 1
478; RV32I-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
479; RV32I-NEXT:    vsub.vx v9, v8, a0
480; RV32I-NEXT:    vnot.v v8, v8
481; RV32I-NEXT:    vand.vv v8, v8, v9
482; RV32I-NEXT:    vsrl.vi v9, v8, 1
483; RV32I-NEXT:    lui a0, 5
484; RV32I-NEXT:    addi a0, a0, 1365
485; RV32I-NEXT:    vand.vx v9, v9, a0
486; RV32I-NEXT:    vsub.vv v8, v8, v9
487; RV32I-NEXT:    lui a0, 3
488; RV32I-NEXT:    addi a0, a0, 819
489; RV32I-NEXT:    vand.vx v9, v8, a0
490; RV32I-NEXT:    vsrl.vi v8, v8, 2
491; RV32I-NEXT:    vand.vx v8, v8, a0
492; RV32I-NEXT:    vadd.vv v8, v9, v8
493; RV32I-NEXT:    vsrl.vi v9, v8, 4
494; RV32I-NEXT:    vadd.vv v8, v8, v9
495; RV32I-NEXT:    lui a0, 1
496; RV32I-NEXT:    addi a0, a0, -241
497; RV32I-NEXT:    vand.vx v8, v8, a0
498; RV32I-NEXT:    li a0, 257
499; RV32I-NEXT:    vmul.vx v8, v8, a0
500; RV32I-NEXT:    vsrl.vi v8, v8, 8
501; RV32I-NEXT:    ret
502;
503; RV64I-LABEL: cttz_nxv1i16:
504; RV64I:       # %bb.0:
505; RV64I-NEXT:    li a0, 1
506; RV64I-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
507; RV64I-NEXT:    vsub.vx v9, v8, a0
508; RV64I-NEXT:    vnot.v v8, v8
509; RV64I-NEXT:    vand.vv v8, v8, v9
510; RV64I-NEXT:    vsrl.vi v9, v8, 1
511; RV64I-NEXT:    lui a0, 5
512; RV64I-NEXT:    addiw a0, a0, 1365
513; RV64I-NEXT:    vand.vx v9, v9, a0
514; RV64I-NEXT:    vsub.vv v8, v8, v9
515; RV64I-NEXT:    lui a0, 3
516; RV64I-NEXT:    addiw a0, a0, 819
517; RV64I-NEXT:    vand.vx v9, v8, a0
518; RV64I-NEXT:    vsrl.vi v8, v8, 2
519; RV64I-NEXT:    vand.vx v8, v8, a0
520; RV64I-NEXT:    vadd.vv v8, v9, v8
521; RV64I-NEXT:    vsrl.vi v9, v8, 4
522; RV64I-NEXT:    vadd.vv v8, v8, v9
523; RV64I-NEXT:    lui a0, 1
524; RV64I-NEXT:    addiw a0, a0, -241
525; RV64I-NEXT:    vand.vx v8, v8, a0
526; RV64I-NEXT:    li a0, 257
527; RV64I-NEXT:    vmul.vx v8, v8, a0
528; RV64I-NEXT:    vsrl.vi v8, v8, 8
529; RV64I-NEXT:    ret
530;
531; RV32D-LABEL: cttz_nxv1i16:
532; RV32D:       # %bb.0:
533; RV32D-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
534; RV32D-NEXT:    vmseq.vx v0, v8, zero
535; RV32D-NEXT:    vrsub.vi v9, v8, 0
536; RV32D-NEXT:    vand.vv v8, v8, v9
537; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
538; RV32D-NEXT:    vnsrl.wi v8, v9, 23
539; RV32D-NEXT:    li a0, 127
540; RV32D-NEXT:    vsub.vx v8, v8, a0
541; RV32D-NEXT:    li a0, 16
542; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
543; RV32D-NEXT:    ret
544;
545; RV64D-LABEL: cttz_nxv1i16:
546; RV64D:       # %bb.0:
547; RV64D-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
548; RV64D-NEXT:    vmseq.vx v0, v8, zero
549; RV64D-NEXT:    vrsub.vi v9, v8, 0
550; RV64D-NEXT:    vand.vv v8, v8, v9
551; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
552; RV64D-NEXT:    vnsrl.wi v8, v9, 23
553; RV64D-NEXT:    li a0, 127
554; RV64D-NEXT:    vsub.vx v8, v8, a0
555; RV64D-NEXT:    li a0, 16
556; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
557; RV64D-NEXT:    ret
558  %a = call <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 false)
559  ret <vscale x 1 x i16> %a
560}
561declare <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16>, i1)
562
563define <vscale x 2 x i16> @cttz_nxv2i16(<vscale x 2 x i16> %va) {
564; RV32I-LABEL: cttz_nxv2i16:
565; RV32I:       # %bb.0:
566; RV32I-NEXT:    li a0, 1
567; RV32I-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
568; RV32I-NEXT:    vsub.vx v9, v8, a0
569; RV32I-NEXT:    vnot.v v8, v8
570; RV32I-NEXT:    vand.vv v8, v8, v9
571; RV32I-NEXT:    vsrl.vi v9, v8, 1
572; RV32I-NEXT:    lui a0, 5
573; RV32I-NEXT:    addi a0, a0, 1365
574; RV32I-NEXT:    vand.vx v9, v9, a0
575; RV32I-NEXT:    vsub.vv v8, v8, v9
576; RV32I-NEXT:    lui a0, 3
577; RV32I-NEXT:    addi a0, a0, 819
578; RV32I-NEXT:    vand.vx v9, v8, a0
579; RV32I-NEXT:    vsrl.vi v8, v8, 2
580; RV32I-NEXT:    vand.vx v8, v8, a0
581; RV32I-NEXT:    vadd.vv v8, v9, v8
582; RV32I-NEXT:    vsrl.vi v9, v8, 4
583; RV32I-NEXT:    vadd.vv v8, v8, v9
584; RV32I-NEXT:    lui a0, 1
585; RV32I-NEXT:    addi a0, a0, -241
586; RV32I-NEXT:    vand.vx v8, v8, a0
587; RV32I-NEXT:    li a0, 257
588; RV32I-NEXT:    vmul.vx v8, v8, a0
589; RV32I-NEXT:    vsrl.vi v8, v8, 8
590; RV32I-NEXT:    ret
591;
592; RV64I-LABEL: cttz_nxv2i16:
593; RV64I:       # %bb.0:
594; RV64I-NEXT:    li a0, 1
595; RV64I-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
596; RV64I-NEXT:    vsub.vx v9, v8, a0
597; RV64I-NEXT:    vnot.v v8, v8
598; RV64I-NEXT:    vand.vv v8, v8, v9
599; RV64I-NEXT:    vsrl.vi v9, v8, 1
600; RV64I-NEXT:    lui a0, 5
601; RV64I-NEXT:    addiw a0, a0, 1365
602; RV64I-NEXT:    vand.vx v9, v9, a0
603; RV64I-NEXT:    vsub.vv v8, v8, v9
604; RV64I-NEXT:    lui a0, 3
605; RV64I-NEXT:    addiw a0, a0, 819
606; RV64I-NEXT:    vand.vx v9, v8, a0
607; RV64I-NEXT:    vsrl.vi v8, v8, 2
608; RV64I-NEXT:    vand.vx v8, v8, a0
609; RV64I-NEXT:    vadd.vv v8, v9, v8
610; RV64I-NEXT:    vsrl.vi v9, v8, 4
611; RV64I-NEXT:    vadd.vv v8, v8, v9
612; RV64I-NEXT:    lui a0, 1
613; RV64I-NEXT:    addiw a0, a0, -241
614; RV64I-NEXT:    vand.vx v8, v8, a0
615; RV64I-NEXT:    li a0, 257
616; RV64I-NEXT:    vmul.vx v8, v8, a0
617; RV64I-NEXT:    vsrl.vi v8, v8, 8
618; RV64I-NEXT:    ret
619;
620; RV32D-LABEL: cttz_nxv2i16:
621; RV32D:       # %bb.0:
622; RV32D-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
623; RV32D-NEXT:    vmseq.vx v0, v8, zero
624; RV32D-NEXT:    vrsub.vi v9, v8, 0
625; RV32D-NEXT:    vand.vv v8, v8, v9
626; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
627; RV32D-NEXT:    vnsrl.wi v8, v9, 23
628; RV32D-NEXT:    li a0, 127
629; RV32D-NEXT:    vsub.vx v8, v8, a0
630; RV32D-NEXT:    li a0, 16
631; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
632; RV32D-NEXT:    ret
633;
634; RV64D-LABEL: cttz_nxv2i16:
635; RV64D:       # %bb.0:
636; RV64D-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
637; RV64D-NEXT:    vmseq.vx v0, v8, zero
638; RV64D-NEXT:    vrsub.vi v9, v8, 0
639; RV64D-NEXT:    vand.vv v8, v8, v9
640; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
641; RV64D-NEXT:    vnsrl.wi v8, v9, 23
642; RV64D-NEXT:    li a0, 127
643; RV64D-NEXT:    vsub.vx v8, v8, a0
644; RV64D-NEXT:    li a0, 16
645; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
646; RV64D-NEXT:    ret
647  %a = call <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 false)
648  ret <vscale x 2 x i16> %a
649}
650declare <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16>, i1)
651
652define <vscale x 4 x i16> @cttz_nxv4i16(<vscale x 4 x i16> %va) {
653; RV32I-LABEL: cttz_nxv4i16:
654; RV32I:       # %bb.0:
655; RV32I-NEXT:    li a0, 1
656; RV32I-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
657; RV32I-NEXT:    vsub.vx v9, v8, a0
658; RV32I-NEXT:    vnot.v v8, v8
659; RV32I-NEXT:    vand.vv v8, v8, v9
660; RV32I-NEXT:    vsrl.vi v9, v8, 1
661; RV32I-NEXT:    lui a0, 5
662; RV32I-NEXT:    addi a0, a0, 1365
663; RV32I-NEXT:    vand.vx v9, v9, a0
664; RV32I-NEXT:    vsub.vv v8, v8, v9
665; RV32I-NEXT:    lui a0, 3
666; RV32I-NEXT:    addi a0, a0, 819
667; RV32I-NEXT:    vand.vx v9, v8, a0
668; RV32I-NEXT:    vsrl.vi v8, v8, 2
669; RV32I-NEXT:    vand.vx v8, v8, a0
670; RV32I-NEXT:    vadd.vv v8, v9, v8
671; RV32I-NEXT:    vsrl.vi v9, v8, 4
672; RV32I-NEXT:    vadd.vv v8, v8, v9
673; RV32I-NEXT:    lui a0, 1
674; RV32I-NEXT:    addi a0, a0, -241
675; RV32I-NEXT:    vand.vx v8, v8, a0
676; RV32I-NEXT:    li a0, 257
677; RV32I-NEXT:    vmul.vx v8, v8, a0
678; RV32I-NEXT:    vsrl.vi v8, v8, 8
679; RV32I-NEXT:    ret
680;
681; RV64I-LABEL: cttz_nxv4i16:
682; RV64I:       # %bb.0:
683; RV64I-NEXT:    li a0, 1
684; RV64I-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
685; RV64I-NEXT:    vsub.vx v9, v8, a0
686; RV64I-NEXT:    vnot.v v8, v8
687; RV64I-NEXT:    vand.vv v8, v8, v9
688; RV64I-NEXT:    vsrl.vi v9, v8, 1
689; RV64I-NEXT:    lui a0, 5
690; RV64I-NEXT:    addiw a0, a0, 1365
691; RV64I-NEXT:    vand.vx v9, v9, a0
692; RV64I-NEXT:    vsub.vv v8, v8, v9
693; RV64I-NEXT:    lui a0, 3
694; RV64I-NEXT:    addiw a0, a0, 819
695; RV64I-NEXT:    vand.vx v9, v8, a0
696; RV64I-NEXT:    vsrl.vi v8, v8, 2
697; RV64I-NEXT:    vand.vx v8, v8, a0
698; RV64I-NEXT:    vadd.vv v8, v9, v8
699; RV64I-NEXT:    vsrl.vi v9, v8, 4
700; RV64I-NEXT:    vadd.vv v8, v8, v9
701; RV64I-NEXT:    lui a0, 1
702; RV64I-NEXT:    addiw a0, a0, -241
703; RV64I-NEXT:    vand.vx v8, v8, a0
704; RV64I-NEXT:    li a0, 257
705; RV64I-NEXT:    vmul.vx v8, v8, a0
706; RV64I-NEXT:    vsrl.vi v8, v8, 8
707; RV64I-NEXT:    ret
708;
709; RV32D-LABEL: cttz_nxv4i16:
710; RV32D:       # %bb.0:
711; RV32D-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
712; RV32D-NEXT:    vmseq.vx v0, v8, zero
713; RV32D-NEXT:    vrsub.vi v9, v8, 0
714; RV32D-NEXT:    vand.vv v8, v8, v9
715; RV32D-NEXT:    vfwcvt.f.xu.v v10, v8
716; RV32D-NEXT:    vnsrl.wi v8, v10, 23
717; RV32D-NEXT:    li a0, 127
718; RV32D-NEXT:    vsub.vx v8, v8, a0
719; RV32D-NEXT:    li a0, 16
720; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
721; RV32D-NEXT:    ret
722;
723; RV64D-LABEL: cttz_nxv4i16:
724; RV64D:       # %bb.0:
725; RV64D-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
726; RV64D-NEXT:    vmseq.vx v0, v8, zero
727; RV64D-NEXT:    vrsub.vi v9, v8, 0
728; RV64D-NEXT:    vand.vv v8, v8, v9
729; RV64D-NEXT:    vfwcvt.f.xu.v v10, v8
730; RV64D-NEXT:    vnsrl.wi v8, v10, 23
731; RV64D-NEXT:    li a0, 127
732; RV64D-NEXT:    vsub.vx v8, v8, a0
733; RV64D-NEXT:    li a0, 16
734; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
735; RV64D-NEXT:    ret
736  %a = call <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 false)
737  ret <vscale x 4 x i16> %a
738}
739declare <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16>, i1)
740
741define <vscale x 8 x i16> @cttz_nxv8i16(<vscale x 8 x i16> %va) {
742; RV32I-LABEL: cttz_nxv8i16:
743; RV32I:       # %bb.0:
744; RV32I-NEXT:    li a0, 1
745; RV32I-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
746; RV32I-NEXT:    vsub.vx v10, v8, a0
747; RV32I-NEXT:    vnot.v v8, v8
748; RV32I-NEXT:    vand.vv v8, v8, v10
749; RV32I-NEXT:    vsrl.vi v10, v8, 1
750; RV32I-NEXT:    lui a0, 5
751; RV32I-NEXT:    addi a0, a0, 1365
752; RV32I-NEXT:    vand.vx v10, v10, a0
753; RV32I-NEXT:    vsub.vv v8, v8, v10
754; RV32I-NEXT:    lui a0, 3
755; RV32I-NEXT:    addi a0, a0, 819
756; RV32I-NEXT:    vand.vx v10, v8, a0
757; RV32I-NEXT:    vsrl.vi v8, v8, 2
758; RV32I-NEXT:    vand.vx v8, v8, a0
759; RV32I-NEXT:    vadd.vv v8, v10, v8
760; RV32I-NEXT:    vsrl.vi v10, v8, 4
761; RV32I-NEXT:    vadd.vv v8, v8, v10
762; RV32I-NEXT:    lui a0, 1
763; RV32I-NEXT:    addi a0, a0, -241
764; RV32I-NEXT:    vand.vx v8, v8, a0
765; RV32I-NEXT:    li a0, 257
766; RV32I-NEXT:    vmul.vx v8, v8, a0
767; RV32I-NEXT:    vsrl.vi v8, v8, 8
768; RV32I-NEXT:    ret
769;
770; RV64I-LABEL: cttz_nxv8i16:
771; RV64I:       # %bb.0:
772; RV64I-NEXT:    li a0, 1
773; RV64I-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
774; RV64I-NEXT:    vsub.vx v10, v8, a0
775; RV64I-NEXT:    vnot.v v8, v8
776; RV64I-NEXT:    vand.vv v8, v8, v10
777; RV64I-NEXT:    vsrl.vi v10, v8, 1
778; RV64I-NEXT:    lui a0, 5
779; RV64I-NEXT:    addiw a0, a0, 1365
780; RV64I-NEXT:    vand.vx v10, v10, a0
781; RV64I-NEXT:    vsub.vv v8, v8, v10
782; RV64I-NEXT:    lui a0, 3
783; RV64I-NEXT:    addiw a0, a0, 819
784; RV64I-NEXT:    vand.vx v10, v8, a0
785; RV64I-NEXT:    vsrl.vi v8, v8, 2
786; RV64I-NEXT:    vand.vx v8, v8, a0
787; RV64I-NEXT:    vadd.vv v8, v10, v8
788; RV64I-NEXT:    vsrl.vi v10, v8, 4
789; RV64I-NEXT:    vadd.vv v8, v8, v10
790; RV64I-NEXT:    lui a0, 1
791; RV64I-NEXT:    addiw a0, a0, -241
792; RV64I-NEXT:    vand.vx v8, v8, a0
793; RV64I-NEXT:    li a0, 257
794; RV64I-NEXT:    vmul.vx v8, v8, a0
795; RV64I-NEXT:    vsrl.vi v8, v8, 8
796; RV64I-NEXT:    ret
797;
798; RV32D-LABEL: cttz_nxv8i16:
799; RV32D:       # %bb.0:
800; RV32D-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
801; RV32D-NEXT:    vmseq.vx v0, v8, zero
802; RV32D-NEXT:    vrsub.vi v10, v8, 0
803; RV32D-NEXT:    vand.vv v8, v8, v10
804; RV32D-NEXT:    vfwcvt.f.xu.v v12, v8
805; RV32D-NEXT:    vnsrl.wi v8, v12, 23
806; RV32D-NEXT:    li a0, 127
807; RV32D-NEXT:    vsub.vx v8, v8, a0
808; RV32D-NEXT:    li a0, 16
809; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
810; RV32D-NEXT:    ret
811;
812; RV64D-LABEL: cttz_nxv8i16:
813; RV64D:       # %bb.0:
814; RV64D-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
815; RV64D-NEXT:    vmseq.vx v0, v8, zero
816; RV64D-NEXT:    vrsub.vi v10, v8, 0
817; RV64D-NEXT:    vand.vv v8, v8, v10
818; RV64D-NEXT:    vfwcvt.f.xu.v v12, v8
819; RV64D-NEXT:    vnsrl.wi v8, v12, 23
820; RV64D-NEXT:    li a0, 127
821; RV64D-NEXT:    vsub.vx v8, v8, a0
822; RV64D-NEXT:    li a0, 16
823; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
824; RV64D-NEXT:    ret
825  %a = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 false)
826  ret <vscale x 8 x i16> %a
827}
828declare <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16>, i1)
829
830define <vscale x 16 x i16> @cttz_nxv16i16(<vscale x 16 x i16> %va) {
831; RV32I-LABEL: cttz_nxv16i16:
832; RV32I:       # %bb.0:
833; RV32I-NEXT:    li a0, 1
834; RV32I-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
835; RV32I-NEXT:    vsub.vx v12, v8, a0
836; RV32I-NEXT:    vnot.v v8, v8
837; RV32I-NEXT:    vand.vv v8, v8, v12
838; RV32I-NEXT:    vsrl.vi v12, v8, 1
839; RV32I-NEXT:    lui a0, 5
840; RV32I-NEXT:    addi a0, a0, 1365
841; RV32I-NEXT:    vand.vx v12, v12, a0
842; RV32I-NEXT:    vsub.vv v8, v8, v12
843; RV32I-NEXT:    lui a0, 3
844; RV32I-NEXT:    addi a0, a0, 819
845; RV32I-NEXT:    vand.vx v12, v8, a0
846; RV32I-NEXT:    vsrl.vi v8, v8, 2
847; RV32I-NEXT:    vand.vx v8, v8, a0
848; RV32I-NEXT:    vadd.vv v8, v12, v8
849; RV32I-NEXT:    vsrl.vi v12, v8, 4
850; RV32I-NEXT:    vadd.vv v8, v8, v12
851; RV32I-NEXT:    lui a0, 1
852; RV32I-NEXT:    addi a0, a0, -241
853; RV32I-NEXT:    vand.vx v8, v8, a0
854; RV32I-NEXT:    li a0, 257
855; RV32I-NEXT:    vmul.vx v8, v8, a0
856; RV32I-NEXT:    vsrl.vi v8, v8, 8
857; RV32I-NEXT:    ret
858;
859; RV64I-LABEL: cttz_nxv16i16:
860; RV64I:       # %bb.0:
861; RV64I-NEXT:    li a0, 1
862; RV64I-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
863; RV64I-NEXT:    vsub.vx v12, v8, a0
864; RV64I-NEXT:    vnot.v v8, v8
865; RV64I-NEXT:    vand.vv v8, v8, v12
866; RV64I-NEXT:    vsrl.vi v12, v8, 1
867; RV64I-NEXT:    lui a0, 5
868; RV64I-NEXT:    addiw a0, a0, 1365
869; RV64I-NEXT:    vand.vx v12, v12, a0
870; RV64I-NEXT:    vsub.vv v8, v8, v12
871; RV64I-NEXT:    lui a0, 3
872; RV64I-NEXT:    addiw a0, a0, 819
873; RV64I-NEXT:    vand.vx v12, v8, a0
874; RV64I-NEXT:    vsrl.vi v8, v8, 2
875; RV64I-NEXT:    vand.vx v8, v8, a0
876; RV64I-NEXT:    vadd.vv v8, v12, v8
877; RV64I-NEXT:    vsrl.vi v12, v8, 4
878; RV64I-NEXT:    vadd.vv v8, v8, v12
879; RV64I-NEXT:    lui a0, 1
880; RV64I-NEXT:    addiw a0, a0, -241
881; RV64I-NEXT:    vand.vx v8, v8, a0
882; RV64I-NEXT:    li a0, 257
883; RV64I-NEXT:    vmul.vx v8, v8, a0
884; RV64I-NEXT:    vsrl.vi v8, v8, 8
885; RV64I-NEXT:    ret
886;
887; RV32D-LABEL: cttz_nxv16i16:
888; RV32D:       # %bb.0:
889; RV32D-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
890; RV32D-NEXT:    vmseq.vx v0, v8, zero
891; RV32D-NEXT:    vrsub.vi v12, v8, 0
892; RV32D-NEXT:    vand.vv v8, v8, v12
893; RV32D-NEXT:    vfwcvt.f.xu.v v16, v8
894; RV32D-NEXT:    vnsrl.wi v8, v16, 23
895; RV32D-NEXT:    li a0, 127
896; RV32D-NEXT:    vsub.vx v8, v8, a0
897; RV32D-NEXT:    li a0, 16
898; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
899; RV32D-NEXT:    ret
900;
901; RV64D-LABEL: cttz_nxv16i16:
902; RV64D:       # %bb.0:
903; RV64D-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
904; RV64D-NEXT:    vmseq.vx v0, v8, zero
905; RV64D-NEXT:    vrsub.vi v12, v8, 0
906; RV64D-NEXT:    vand.vv v8, v8, v12
907; RV64D-NEXT:    vfwcvt.f.xu.v v16, v8
908; RV64D-NEXT:    vnsrl.wi v8, v16, 23
909; RV64D-NEXT:    li a0, 127
910; RV64D-NEXT:    vsub.vx v8, v8, a0
911; RV64D-NEXT:    li a0, 16
912; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
913; RV64D-NEXT:    ret
914  %a = call <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 false)
915  ret <vscale x 16 x i16> %a
916}
917declare <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16>, i1)
918
919define <vscale x 32 x i16> @cttz_nxv32i16(<vscale x 32 x i16> %va) {
920; RV32-LABEL: cttz_nxv32i16:
921; RV32:       # %bb.0:
922; RV32-NEXT:    li a0, 1
923; RV32-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
924; RV32-NEXT:    vsub.vx v16, v8, a0
925; RV32-NEXT:    vnot.v v8, v8
926; RV32-NEXT:    vand.vv v8, v8, v16
927; RV32-NEXT:    vsrl.vi v16, v8, 1
928; RV32-NEXT:    lui a0, 5
929; RV32-NEXT:    addi a0, a0, 1365
930; RV32-NEXT:    vand.vx v16, v16, a0
931; RV32-NEXT:    vsub.vv v8, v8, v16
932; RV32-NEXT:    lui a0, 3
933; RV32-NEXT:    addi a0, a0, 819
934; RV32-NEXT:    vand.vx v16, v8, a0
935; RV32-NEXT:    vsrl.vi v8, v8, 2
936; RV32-NEXT:    vand.vx v8, v8, a0
937; RV32-NEXT:    vadd.vv v8, v16, v8
938; RV32-NEXT:    vsrl.vi v16, v8, 4
939; RV32-NEXT:    vadd.vv v8, v8, v16
940; RV32-NEXT:    lui a0, 1
941; RV32-NEXT:    addi a0, a0, -241
942; RV32-NEXT:    vand.vx v8, v8, a0
943; RV32-NEXT:    li a0, 257
944; RV32-NEXT:    vmul.vx v8, v8, a0
945; RV32-NEXT:    vsrl.vi v8, v8, 8
946; RV32-NEXT:    ret
947;
948; RV64-LABEL: cttz_nxv32i16:
949; RV64:       # %bb.0:
950; RV64-NEXT:    li a0, 1
951; RV64-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
952; RV64-NEXT:    vsub.vx v16, v8, a0
953; RV64-NEXT:    vnot.v v8, v8
954; RV64-NEXT:    vand.vv v8, v8, v16
955; RV64-NEXT:    vsrl.vi v16, v8, 1
956; RV64-NEXT:    lui a0, 5
957; RV64-NEXT:    addiw a0, a0, 1365
958; RV64-NEXT:    vand.vx v16, v16, a0
959; RV64-NEXT:    vsub.vv v8, v8, v16
960; RV64-NEXT:    lui a0, 3
961; RV64-NEXT:    addiw a0, a0, 819
962; RV64-NEXT:    vand.vx v16, v8, a0
963; RV64-NEXT:    vsrl.vi v8, v8, 2
964; RV64-NEXT:    vand.vx v8, v8, a0
965; RV64-NEXT:    vadd.vv v8, v16, v8
966; RV64-NEXT:    vsrl.vi v16, v8, 4
967; RV64-NEXT:    vadd.vv v8, v8, v16
968; RV64-NEXT:    lui a0, 1
969; RV64-NEXT:    addiw a0, a0, -241
970; RV64-NEXT:    vand.vx v8, v8, a0
971; RV64-NEXT:    li a0, 257
972; RV64-NEXT:    vmul.vx v8, v8, a0
973; RV64-NEXT:    vsrl.vi v8, v8, 8
974; RV64-NEXT:    ret
975  %a = call <vscale x 32 x i16> @llvm.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 false)
976  ret <vscale x 32 x i16> %a
977}
978declare <vscale x 32 x i16> @llvm.cttz.nxv32i16(<vscale x 32 x i16>, i1)
979
980define <vscale x 1 x i32> @cttz_nxv1i32(<vscale x 1 x i32> %va) {
981; RV32I-LABEL: cttz_nxv1i32:
982; RV32I:       # %bb.0:
983; RV32I-NEXT:    li a0, 1
984; RV32I-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
985; RV32I-NEXT:    vsub.vx v9, v8, a0
986; RV32I-NEXT:    vnot.v v8, v8
987; RV32I-NEXT:    vand.vv v8, v8, v9
988; RV32I-NEXT:    vsrl.vi v9, v8, 1
989; RV32I-NEXT:    lui a0, 349525
990; RV32I-NEXT:    addi a0, a0, 1365
991; RV32I-NEXT:    vand.vx v9, v9, a0
992; RV32I-NEXT:    vsub.vv v8, v8, v9
993; RV32I-NEXT:    lui a0, 209715
994; RV32I-NEXT:    addi a0, a0, 819
995; RV32I-NEXT:    vand.vx v9, v8, a0
996; RV32I-NEXT:    vsrl.vi v8, v8, 2
997; RV32I-NEXT:    vand.vx v8, v8, a0
998; RV32I-NEXT:    vadd.vv v8, v9, v8
999; RV32I-NEXT:    vsrl.vi v9, v8, 4
1000; RV32I-NEXT:    vadd.vv v8, v8, v9
1001; RV32I-NEXT:    lui a0, 61681
1002; RV32I-NEXT:    addi a0, a0, -241
1003; RV32I-NEXT:    vand.vx v8, v8, a0
1004; RV32I-NEXT:    lui a0, 4112
1005; RV32I-NEXT:    addi a0, a0, 257
1006; RV32I-NEXT:    vmul.vx v8, v8, a0
1007; RV32I-NEXT:    vsrl.vi v8, v8, 24
1008; RV32I-NEXT:    ret
1009;
1010; RV64I-LABEL: cttz_nxv1i32:
1011; RV64I:       # %bb.0:
1012; RV64I-NEXT:    li a0, 1
1013; RV64I-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
1014; RV64I-NEXT:    vsub.vx v9, v8, a0
1015; RV64I-NEXT:    vnot.v v8, v8
1016; RV64I-NEXT:    vand.vv v8, v8, v9
1017; RV64I-NEXT:    vsrl.vi v9, v8, 1
1018; RV64I-NEXT:    lui a0, 349525
1019; RV64I-NEXT:    addiw a0, a0, 1365
1020; RV64I-NEXT:    vand.vx v9, v9, a0
1021; RV64I-NEXT:    vsub.vv v8, v8, v9
1022; RV64I-NEXT:    lui a0, 209715
1023; RV64I-NEXT:    addiw a0, a0, 819
1024; RV64I-NEXT:    vand.vx v9, v8, a0
1025; RV64I-NEXT:    vsrl.vi v8, v8, 2
1026; RV64I-NEXT:    vand.vx v8, v8, a0
1027; RV64I-NEXT:    vadd.vv v8, v9, v8
1028; RV64I-NEXT:    vsrl.vi v9, v8, 4
1029; RV64I-NEXT:    vadd.vv v8, v8, v9
1030; RV64I-NEXT:    lui a0, 61681
1031; RV64I-NEXT:    addiw a0, a0, -241
1032; RV64I-NEXT:    vand.vx v8, v8, a0
1033; RV64I-NEXT:    lui a0, 4112
1034; RV64I-NEXT:    addiw a0, a0, 257
1035; RV64I-NEXT:    vmul.vx v8, v8, a0
1036; RV64I-NEXT:    vsrl.vi v8, v8, 24
1037; RV64I-NEXT:    ret
1038;
1039; RV32D-LABEL: cttz_nxv1i32:
1040; RV32D:       # %bb.0:
1041; RV32D-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
1042; RV32D-NEXT:    vrsub.vi v9, v8, 0
1043; RV32D-NEXT:    vand.vv v9, v8, v9
1044; RV32D-NEXT:    vfwcvt.f.xu.v v10, v9
1045; RV32D-NEXT:    li a0, 52
1046; RV32D-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
1047; RV32D-NEXT:    vsrl.vx v9, v10, a0
1048; RV32D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
1049; RV32D-NEXT:    vncvt.x.x.w v9, v9
1050; RV32D-NEXT:    li a0, 1023
1051; RV32D-NEXT:    vsub.vx v9, v9, a0
1052; RV32D-NEXT:    vmseq.vi v0, v8, 0
1053; RV32D-NEXT:    li a0, 32
1054; RV32D-NEXT:    vmerge.vxm v8, v9, a0, v0
1055; RV32D-NEXT:    ret
1056;
1057; RV64D-LABEL: cttz_nxv1i32:
1058; RV64D:       # %bb.0:
1059; RV64D-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
1060; RV64D-NEXT:    vmseq.vx v0, v8, zero
1061; RV64D-NEXT:    vrsub.vi v9, v8, 0
1062; RV64D-NEXT:    vand.vv v8, v8, v9
1063; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
1064; RV64D-NEXT:    li a0, 52
1065; RV64D-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
1066; RV64D-NEXT:    vsrl.vx v8, v9, a0
1067; RV64D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
1068; RV64D-NEXT:    vncvt.x.x.w v8, v8
1069; RV64D-NEXT:    li a0, 1023
1070; RV64D-NEXT:    vsub.vx v8, v8, a0
1071; RV64D-NEXT:    li a0, 32
1072; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
1073; RV64D-NEXT:    ret
1074  %a = call <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 false)
1075  ret <vscale x 1 x i32> %a
1076}
1077declare <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32>, i1)
1078
1079define <vscale x 2 x i32> @cttz_nxv2i32(<vscale x 2 x i32> %va) {
1080; RV32I-LABEL: cttz_nxv2i32:
1081; RV32I:       # %bb.0:
1082; RV32I-NEXT:    li a0, 1
1083; RV32I-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
1084; RV32I-NEXT:    vsub.vx v9, v8, a0
1085; RV32I-NEXT:    vnot.v v8, v8
1086; RV32I-NEXT:    vand.vv v8, v8, v9
1087; RV32I-NEXT:    vsrl.vi v9, v8, 1
1088; RV32I-NEXT:    lui a0, 349525
1089; RV32I-NEXT:    addi a0, a0, 1365
1090; RV32I-NEXT:    vand.vx v9, v9, a0
1091; RV32I-NEXT:    vsub.vv v8, v8, v9
1092; RV32I-NEXT:    lui a0, 209715
1093; RV32I-NEXT:    addi a0, a0, 819
1094; RV32I-NEXT:    vand.vx v9, v8, a0
1095; RV32I-NEXT:    vsrl.vi v8, v8, 2
1096; RV32I-NEXT:    vand.vx v8, v8, a0
1097; RV32I-NEXT:    vadd.vv v8, v9, v8
1098; RV32I-NEXT:    vsrl.vi v9, v8, 4
1099; RV32I-NEXT:    vadd.vv v8, v8, v9
1100; RV32I-NEXT:    lui a0, 61681
1101; RV32I-NEXT:    addi a0, a0, -241
1102; RV32I-NEXT:    vand.vx v8, v8, a0
1103; RV32I-NEXT:    lui a0, 4112
1104; RV32I-NEXT:    addi a0, a0, 257
1105; RV32I-NEXT:    vmul.vx v8, v8, a0
1106; RV32I-NEXT:    vsrl.vi v8, v8, 24
1107; RV32I-NEXT:    ret
1108;
1109; RV64I-LABEL: cttz_nxv2i32:
1110; RV64I:       # %bb.0:
1111; RV64I-NEXT:    li a0, 1
1112; RV64I-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
1113; RV64I-NEXT:    vsub.vx v9, v8, a0
1114; RV64I-NEXT:    vnot.v v8, v8
1115; RV64I-NEXT:    vand.vv v8, v8, v9
1116; RV64I-NEXT:    vsrl.vi v9, v8, 1
1117; RV64I-NEXT:    lui a0, 349525
1118; RV64I-NEXT:    addiw a0, a0, 1365
1119; RV64I-NEXT:    vand.vx v9, v9, a0
1120; RV64I-NEXT:    vsub.vv v8, v8, v9
1121; RV64I-NEXT:    lui a0, 209715
1122; RV64I-NEXT:    addiw a0, a0, 819
1123; RV64I-NEXT:    vand.vx v9, v8, a0
1124; RV64I-NEXT:    vsrl.vi v8, v8, 2
1125; RV64I-NEXT:    vand.vx v8, v8, a0
1126; RV64I-NEXT:    vadd.vv v8, v9, v8
1127; RV64I-NEXT:    vsrl.vi v9, v8, 4
1128; RV64I-NEXT:    vadd.vv v8, v8, v9
1129; RV64I-NEXT:    lui a0, 61681
1130; RV64I-NEXT:    addiw a0, a0, -241
1131; RV64I-NEXT:    vand.vx v8, v8, a0
1132; RV64I-NEXT:    lui a0, 4112
1133; RV64I-NEXT:    addiw a0, a0, 257
1134; RV64I-NEXT:    vmul.vx v8, v8, a0
1135; RV64I-NEXT:    vsrl.vi v8, v8, 24
1136; RV64I-NEXT:    ret
1137;
1138; RV32D-LABEL: cttz_nxv2i32:
1139; RV32D:       # %bb.0:
1140; RV32D-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
1141; RV32D-NEXT:    vrsub.vi v9, v8, 0
1142; RV32D-NEXT:    vand.vv v9, v8, v9
1143; RV32D-NEXT:    vfwcvt.f.xu.v v10, v9
1144; RV32D-NEXT:    li a0, 52
1145; RV32D-NEXT:    vsetvli zero, zero, e64, m2, ta, mu
1146; RV32D-NEXT:    vsrl.vx v10, v10, a0
1147; RV32D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
1148; RV32D-NEXT:    vncvt.x.x.w v9, v10
1149; RV32D-NEXT:    li a0, 1023
1150; RV32D-NEXT:    vsub.vx v9, v9, a0
1151; RV32D-NEXT:    vmseq.vi v0, v8, 0
1152; RV32D-NEXT:    li a0, 32
1153; RV32D-NEXT:    vmerge.vxm v8, v9, a0, v0
1154; RV32D-NEXT:    ret
1155;
1156; RV64D-LABEL: cttz_nxv2i32:
1157; RV64D:       # %bb.0:
1158; RV64D-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
1159; RV64D-NEXT:    vmseq.vx v0, v8, zero
1160; RV64D-NEXT:    vrsub.vi v9, v8, 0
1161; RV64D-NEXT:    vand.vv v8, v8, v9
1162; RV64D-NEXT:    vfwcvt.f.xu.v v10, v8
1163; RV64D-NEXT:    li a0, 52
1164; RV64D-NEXT:    vsetvli zero, zero, e64, m2, ta, mu
1165; RV64D-NEXT:    vsrl.vx v8, v10, a0
1166; RV64D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
1167; RV64D-NEXT:    vncvt.x.x.w v10, v8
1168; RV64D-NEXT:    li a0, 1023
1169; RV64D-NEXT:    vsub.vx v8, v10, a0
1170; RV64D-NEXT:    li a0, 32
1171; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
1172; RV64D-NEXT:    ret
1173  %a = call <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 false)
1174  ret <vscale x 2 x i32> %a
1175}
1176declare <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32>, i1)
1177
1178define <vscale x 4 x i32> @cttz_nxv4i32(<vscale x 4 x i32> %va) {
1179; RV32I-LABEL: cttz_nxv4i32:
1180; RV32I:       # %bb.0:
1181; RV32I-NEXT:    li a0, 1
1182; RV32I-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
1183; RV32I-NEXT:    vsub.vx v10, v8, a0
1184; RV32I-NEXT:    vnot.v v8, v8
1185; RV32I-NEXT:    vand.vv v8, v8, v10
1186; RV32I-NEXT:    vsrl.vi v10, v8, 1
1187; RV32I-NEXT:    lui a0, 349525
1188; RV32I-NEXT:    addi a0, a0, 1365
1189; RV32I-NEXT:    vand.vx v10, v10, a0
1190; RV32I-NEXT:    vsub.vv v8, v8, v10
1191; RV32I-NEXT:    lui a0, 209715
1192; RV32I-NEXT:    addi a0, a0, 819
1193; RV32I-NEXT:    vand.vx v10, v8, a0
1194; RV32I-NEXT:    vsrl.vi v8, v8, 2
1195; RV32I-NEXT:    vand.vx v8, v8, a0
1196; RV32I-NEXT:    vadd.vv v8, v10, v8
1197; RV32I-NEXT:    vsrl.vi v10, v8, 4
1198; RV32I-NEXT:    vadd.vv v8, v8, v10
1199; RV32I-NEXT:    lui a0, 61681
1200; RV32I-NEXT:    addi a0, a0, -241
1201; RV32I-NEXT:    vand.vx v8, v8, a0
1202; RV32I-NEXT:    lui a0, 4112
1203; RV32I-NEXT:    addi a0, a0, 257
1204; RV32I-NEXT:    vmul.vx v8, v8, a0
1205; RV32I-NEXT:    vsrl.vi v8, v8, 24
1206; RV32I-NEXT:    ret
1207;
1208; RV64I-LABEL: cttz_nxv4i32:
1209; RV64I:       # %bb.0:
1210; RV64I-NEXT:    li a0, 1
1211; RV64I-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
1212; RV64I-NEXT:    vsub.vx v10, v8, a0
1213; RV64I-NEXT:    vnot.v v8, v8
1214; RV64I-NEXT:    vand.vv v8, v8, v10
1215; RV64I-NEXT:    vsrl.vi v10, v8, 1
1216; RV64I-NEXT:    lui a0, 349525
1217; RV64I-NEXT:    addiw a0, a0, 1365
1218; RV64I-NEXT:    vand.vx v10, v10, a0
1219; RV64I-NEXT:    vsub.vv v8, v8, v10
1220; RV64I-NEXT:    lui a0, 209715
1221; RV64I-NEXT:    addiw a0, a0, 819
1222; RV64I-NEXT:    vand.vx v10, v8, a0
1223; RV64I-NEXT:    vsrl.vi v8, v8, 2
1224; RV64I-NEXT:    vand.vx v8, v8, a0
1225; RV64I-NEXT:    vadd.vv v8, v10, v8
1226; RV64I-NEXT:    vsrl.vi v10, v8, 4
1227; RV64I-NEXT:    vadd.vv v8, v8, v10
1228; RV64I-NEXT:    lui a0, 61681
1229; RV64I-NEXT:    addiw a0, a0, -241
1230; RV64I-NEXT:    vand.vx v8, v8, a0
1231; RV64I-NEXT:    lui a0, 4112
1232; RV64I-NEXT:    addiw a0, a0, 257
1233; RV64I-NEXT:    vmul.vx v8, v8, a0
1234; RV64I-NEXT:    vsrl.vi v8, v8, 24
1235; RV64I-NEXT:    ret
1236;
1237; RV32D-LABEL: cttz_nxv4i32:
1238; RV32D:       # %bb.0:
1239; RV32D-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
1240; RV32D-NEXT:    vrsub.vi v10, v8, 0
1241; RV32D-NEXT:    vand.vv v10, v8, v10
1242; RV32D-NEXT:    vfwcvt.f.xu.v v12, v10
1243; RV32D-NEXT:    li a0, 52
1244; RV32D-NEXT:    vsetvli zero, zero, e64, m4, ta, mu
1245; RV32D-NEXT:    vsrl.vx v12, v12, a0
1246; RV32D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
1247; RV32D-NEXT:    vncvt.x.x.w v10, v12
1248; RV32D-NEXT:    li a0, 1023
1249; RV32D-NEXT:    vsub.vx v10, v10, a0
1250; RV32D-NEXT:    vmseq.vi v0, v8, 0
1251; RV32D-NEXT:    li a0, 32
1252; RV32D-NEXT:    vmerge.vxm v8, v10, a0, v0
1253; RV32D-NEXT:    ret
1254;
1255; RV64D-LABEL: cttz_nxv4i32:
1256; RV64D:       # %bb.0:
1257; RV64D-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
1258; RV64D-NEXT:    vmseq.vx v0, v8, zero
1259; RV64D-NEXT:    vrsub.vi v10, v8, 0
1260; RV64D-NEXT:    vand.vv v8, v8, v10
1261; RV64D-NEXT:    vfwcvt.f.xu.v v12, v8
1262; RV64D-NEXT:    li a0, 52
1263; RV64D-NEXT:    vsetvli zero, zero, e64, m4, ta, mu
1264; RV64D-NEXT:    vsrl.vx v8, v12, a0
1265; RV64D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
1266; RV64D-NEXT:    vncvt.x.x.w v12, v8
1267; RV64D-NEXT:    li a0, 1023
1268; RV64D-NEXT:    vsub.vx v8, v12, a0
1269; RV64D-NEXT:    li a0, 32
1270; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
1271; RV64D-NEXT:    ret
1272  %a = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 false)
1273  ret <vscale x 4 x i32> %a
1274}
1275declare <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32>, i1)
1276
1277define <vscale x 8 x i32> @cttz_nxv8i32(<vscale x 8 x i32> %va) {
1278; RV32I-LABEL: cttz_nxv8i32:
1279; RV32I:       # %bb.0:
1280; RV32I-NEXT:    li a0, 1
1281; RV32I-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1282; RV32I-NEXT:    vsub.vx v12, v8, a0
1283; RV32I-NEXT:    vnot.v v8, v8
1284; RV32I-NEXT:    vand.vv v8, v8, v12
1285; RV32I-NEXT:    vsrl.vi v12, v8, 1
1286; RV32I-NEXT:    lui a0, 349525
1287; RV32I-NEXT:    addi a0, a0, 1365
1288; RV32I-NEXT:    vand.vx v12, v12, a0
1289; RV32I-NEXT:    vsub.vv v8, v8, v12
1290; RV32I-NEXT:    lui a0, 209715
1291; RV32I-NEXT:    addi a0, a0, 819
1292; RV32I-NEXT:    vand.vx v12, v8, a0
1293; RV32I-NEXT:    vsrl.vi v8, v8, 2
1294; RV32I-NEXT:    vand.vx v8, v8, a0
1295; RV32I-NEXT:    vadd.vv v8, v12, v8
1296; RV32I-NEXT:    vsrl.vi v12, v8, 4
1297; RV32I-NEXT:    vadd.vv v8, v8, v12
1298; RV32I-NEXT:    lui a0, 61681
1299; RV32I-NEXT:    addi a0, a0, -241
1300; RV32I-NEXT:    vand.vx v8, v8, a0
1301; RV32I-NEXT:    lui a0, 4112
1302; RV32I-NEXT:    addi a0, a0, 257
1303; RV32I-NEXT:    vmul.vx v8, v8, a0
1304; RV32I-NEXT:    vsrl.vi v8, v8, 24
1305; RV32I-NEXT:    ret
1306;
1307; RV64I-LABEL: cttz_nxv8i32:
1308; RV64I:       # %bb.0:
1309; RV64I-NEXT:    li a0, 1
1310; RV64I-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1311; RV64I-NEXT:    vsub.vx v12, v8, a0
1312; RV64I-NEXT:    vnot.v v8, v8
1313; RV64I-NEXT:    vand.vv v8, v8, v12
1314; RV64I-NEXT:    vsrl.vi v12, v8, 1
1315; RV64I-NEXT:    lui a0, 349525
1316; RV64I-NEXT:    addiw a0, a0, 1365
1317; RV64I-NEXT:    vand.vx v12, v12, a0
1318; RV64I-NEXT:    vsub.vv v8, v8, v12
1319; RV64I-NEXT:    lui a0, 209715
1320; RV64I-NEXT:    addiw a0, a0, 819
1321; RV64I-NEXT:    vand.vx v12, v8, a0
1322; RV64I-NEXT:    vsrl.vi v8, v8, 2
1323; RV64I-NEXT:    vand.vx v8, v8, a0
1324; RV64I-NEXT:    vadd.vv v8, v12, v8
1325; RV64I-NEXT:    vsrl.vi v12, v8, 4
1326; RV64I-NEXT:    vadd.vv v8, v8, v12
1327; RV64I-NEXT:    lui a0, 61681
1328; RV64I-NEXT:    addiw a0, a0, -241
1329; RV64I-NEXT:    vand.vx v8, v8, a0
1330; RV64I-NEXT:    lui a0, 4112
1331; RV64I-NEXT:    addiw a0, a0, 257
1332; RV64I-NEXT:    vmul.vx v8, v8, a0
1333; RV64I-NEXT:    vsrl.vi v8, v8, 24
1334; RV64I-NEXT:    ret
1335;
1336; RV32D-LABEL: cttz_nxv8i32:
1337; RV32D:       # %bb.0:
1338; RV32D-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1339; RV32D-NEXT:    vrsub.vi v12, v8, 0
1340; RV32D-NEXT:    vand.vv v12, v8, v12
1341; RV32D-NEXT:    vfwcvt.f.xu.v v16, v12
1342; RV32D-NEXT:    li a0, 52
1343; RV32D-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
1344; RV32D-NEXT:    vsrl.vx v16, v16, a0
1345; RV32D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
1346; RV32D-NEXT:    vncvt.x.x.w v12, v16
1347; RV32D-NEXT:    li a0, 1023
1348; RV32D-NEXT:    vsub.vx v12, v12, a0
1349; RV32D-NEXT:    vmseq.vi v0, v8, 0
1350; RV32D-NEXT:    li a0, 32
1351; RV32D-NEXT:    vmerge.vxm v8, v12, a0, v0
1352; RV32D-NEXT:    ret
1353;
1354; RV64D-LABEL: cttz_nxv8i32:
1355; RV64D:       # %bb.0:
1356; RV64D-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1357; RV64D-NEXT:    vmseq.vx v0, v8, zero
1358; RV64D-NEXT:    vrsub.vi v12, v8, 0
1359; RV64D-NEXT:    vand.vv v8, v8, v12
1360; RV64D-NEXT:    vfwcvt.f.xu.v v16, v8
1361; RV64D-NEXT:    li a0, 52
1362; RV64D-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
1363; RV64D-NEXT:    vsrl.vx v8, v16, a0
1364; RV64D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
1365; RV64D-NEXT:    vncvt.x.x.w v16, v8
1366; RV64D-NEXT:    li a0, 1023
1367; RV64D-NEXT:    vsub.vx v8, v16, a0
1368; RV64D-NEXT:    li a0, 32
1369; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
1370; RV64D-NEXT:    ret
1371  %a = call <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 false)
1372  ret <vscale x 8 x i32> %a
1373}
1374declare <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32>, i1)
1375
1376define <vscale x 16 x i32> @cttz_nxv16i32(<vscale x 16 x i32> %va) {
1377; RV32-LABEL: cttz_nxv16i32:
1378; RV32:       # %bb.0:
1379; RV32-NEXT:    li a0, 1
1380; RV32-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
1381; RV32-NEXT:    vsub.vx v16, v8, a0
1382; RV32-NEXT:    vnot.v v8, v8
1383; RV32-NEXT:    vand.vv v8, v8, v16
1384; RV32-NEXT:    vsrl.vi v16, v8, 1
1385; RV32-NEXT:    lui a0, 349525
1386; RV32-NEXT:    addi a0, a0, 1365
1387; RV32-NEXT:    vand.vx v16, v16, a0
1388; RV32-NEXT:    vsub.vv v8, v8, v16
1389; RV32-NEXT:    lui a0, 209715
1390; RV32-NEXT:    addi a0, a0, 819
1391; RV32-NEXT:    vand.vx v16, v8, a0
1392; RV32-NEXT:    vsrl.vi v8, v8, 2
1393; RV32-NEXT:    vand.vx v8, v8, a0
1394; RV32-NEXT:    vadd.vv v8, v16, v8
1395; RV32-NEXT:    vsrl.vi v16, v8, 4
1396; RV32-NEXT:    vadd.vv v8, v8, v16
1397; RV32-NEXT:    lui a0, 61681
1398; RV32-NEXT:    addi a0, a0, -241
1399; RV32-NEXT:    vand.vx v8, v8, a0
1400; RV32-NEXT:    lui a0, 4112
1401; RV32-NEXT:    addi a0, a0, 257
1402; RV32-NEXT:    vmul.vx v8, v8, a0
1403; RV32-NEXT:    vsrl.vi v8, v8, 24
1404; RV32-NEXT:    ret
1405;
1406; RV64-LABEL: cttz_nxv16i32:
1407; RV64:       # %bb.0:
1408; RV64-NEXT:    li a0, 1
1409; RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
1410; RV64-NEXT:    vsub.vx v16, v8, a0
1411; RV64-NEXT:    vnot.v v8, v8
1412; RV64-NEXT:    vand.vv v8, v8, v16
1413; RV64-NEXT:    vsrl.vi v16, v8, 1
1414; RV64-NEXT:    lui a0, 349525
1415; RV64-NEXT:    addiw a0, a0, 1365
1416; RV64-NEXT:    vand.vx v16, v16, a0
1417; RV64-NEXT:    vsub.vv v8, v8, v16
1418; RV64-NEXT:    lui a0, 209715
1419; RV64-NEXT:    addiw a0, a0, 819
1420; RV64-NEXT:    vand.vx v16, v8, a0
1421; RV64-NEXT:    vsrl.vi v8, v8, 2
1422; RV64-NEXT:    vand.vx v8, v8, a0
1423; RV64-NEXT:    vadd.vv v8, v16, v8
1424; RV64-NEXT:    vsrl.vi v16, v8, 4
1425; RV64-NEXT:    vadd.vv v8, v8, v16
1426; RV64-NEXT:    lui a0, 61681
1427; RV64-NEXT:    addiw a0, a0, -241
1428; RV64-NEXT:    vand.vx v8, v8, a0
1429; RV64-NEXT:    lui a0, 4112
1430; RV64-NEXT:    addiw a0, a0, 257
1431; RV64-NEXT:    vmul.vx v8, v8, a0
1432; RV64-NEXT:    vsrl.vi v8, v8, 24
1433; RV64-NEXT:    ret
1434  %a = call <vscale x 16 x i32> @llvm.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 false)
1435  ret <vscale x 16 x i32> %a
1436}
1437declare <vscale x 16 x i32> @llvm.cttz.nxv16i32(<vscale x 16 x i32>, i1)
1438
1439define <vscale x 1 x i64> @cttz_nxv1i64(<vscale x 1 x i64> %va) {
1440; RV32-LABEL: cttz_nxv1i64:
1441; RV32:       # %bb.0:
1442; RV32-NEXT:    addi sp, sp, -16
1443; RV32-NEXT:    .cfi_def_cfa_offset 16
1444; RV32-NEXT:    lui a0, 349525
1445; RV32-NEXT:    addi a0, a0, 1365
1446; RV32-NEXT:    sw a0, 12(sp)
1447; RV32-NEXT:    sw a0, 8(sp)
1448; RV32-NEXT:    lui a0, 209715
1449; RV32-NEXT:    addi a0, a0, 819
1450; RV32-NEXT:    sw a0, 12(sp)
1451; RV32-NEXT:    sw a0, 8(sp)
1452; RV32-NEXT:    lui a0, 61681
1453; RV32-NEXT:    addi a0, a0, -241
1454; RV32-NEXT:    sw a0, 12(sp)
1455; RV32-NEXT:    sw a0, 8(sp)
1456; RV32-NEXT:    lui a0, 4112
1457; RV32-NEXT:    addi a0, a0, 257
1458; RV32-NEXT:    sw a0, 12(sp)
1459; RV32-NEXT:    sw a0, 8(sp)
1460; RV32-NEXT:    li a0, 1
1461; RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
1462; RV32-NEXT:    vsub.vx v9, v8, a0
1463; RV32-NEXT:    vnot.v v8, v8
1464; RV32-NEXT:    addi a0, sp, 8
1465; RV32-NEXT:    vlse64.v v10, (a0), zero
1466; RV32-NEXT:    vand.vv v8, v8, v9
1467; RV32-NEXT:    addi a0, sp, 8
1468; RV32-NEXT:    vlse64.v v9, (a0), zero
1469; RV32-NEXT:    vsrl.vi v11, v8, 1
1470; RV32-NEXT:    vand.vv v10, v11, v10
1471; RV32-NEXT:    vsub.vv v8, v8, v10
1472; RV32-NEXT:    vand.vv v10, v8, v9
1473; RV32-NEXT:    vsrl.vi v8, v8, 2
1474; RV32-NEXT:    vand.vv v8, v8, v9
1475; RV32-NEXT:    vadd.vv v8, v10, v8
1476; RV32-NEXT:    addi a0, sp, 8
1477; RV32-NEXT:    vlse64.v v9, (a0), zero
1478; RV32-NEXT:    addi a0, sp, 8
1479; RV32-NEXT:    vlse64.v v10, (a0), zero
1480; RV32-NEXT:    vsrl.vi v11, v8, 4
1481; RV32-NEXT:    vadd.vv v8, v8, v11
1482; RV32-NEXT:    vand.vv v8, v8, v9
1483; RV32-NEXT:    vmul.vv v8, v8, v10
1484; RV32-NEXT:    li a0, 56
1485; RV32-NEXT:    vsrl.vx v8, v8, a0
1486; RV32-NEXT:    addi sp, sp, 16
1487; RV32-NEXT:    ret
1488;
1489; RV64-LABEL: cttz_nxv1i64:
1490; RV64:       # %bb.0:
1491; RV64-NEXT:    li a0, 1
1492; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
1493; RV64-NEXT:    vsub.vx v9, v8, a0
1494; RV64-NEXT:    vnot.v v8, v8
1495; RV64-NEXT:    vand.vv v8, v8, v9
1496; RV64-NEXT:    lui a0, %hi(.LCPI18_0)
1497; RV64-NEXT:    ld a0, %lo(.LCPI18_0)(a0)
1498; RV64-NEXT:    lui a1, %hi(.LCPI18_1)
1499; RV64-NEXT:    ld a1, %lo(.LCPI18_1)(a1)
1500; RV64-NEXT:    vsrl.vi v9, v8, 1
1501; RV64-NEXT:    vand.vx v9, v9, a0
1502; RV64-NEXT:    vsub.vv v8, v8, v9
1503; RV64-NEXT:    vand.vx v9, v8, a1
1504; RV64-NEXT:    vsrl.vi v8, v8, 2
1505; RV64-NEXT:    vand.vx v8, v8, a1
1506; RV64-NEXT:    vadd.vv v8, v9, v8
1507; RV64-NEXT:    lui a0, %hi(.LCPI18_2)
1508; RV64-NEXT:    ld a0, %lo(.LCPI18_2)(a0)
1509; RV64-NEXT:    lui a1, %hi(.LCPI18_3)
1510; RV64-NEXT:    ld a1, %lo(.LCPI18_3)(a1)
1511; RV64-NEXT:    vsrl.vi v9, v8, 4
1512; RV64-NEXT:    vadd.vv v8, v8, v9
1513; RV64-NEXT:    vand.vx v8, v8, a0
1514; RV64-NEXT:    vmul.vx v8, v8, a1
1515; RV64-NEXT:    li a0, 56
1516; RV64-NEXT:    vsrl.vx v8, v8, a0
1517; RV64-NEXT:    ret
1518  %a = call <vscale x 1 x i64> @llvm.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 false)
1519  ret <vscale x 1 x i64> %a
1520}
1521declare <vscale x 1 x i64> @llvm.cttz.nxv1i64(<vscale x 1 x i64>, i1)
1522
1523define <vscale x 2 x i64> @cttz_nxv2i64(<vscale x 2 x i64> %va) {
1524; RV32-LABEL: cttz_nxv2i64:
1525; RV32:       # %bb.0:
1526; RV32-NEXT:    addi sp, sp, -16
1527; RV32-NEXT:    .cfi_def_cfa_offset 16
1528; RV32-NEXT:    lui a0, 349525
1529; RV32-NEXT:    addi a0, a0, 1365
1530; RV32-NEXT:    sw a0, 12(sp)
1531; RV32-NEXT:    sw a0, 8(sp)
1532; RV32-NEXT:    lui a0, 209715
1533; RV32-NEXT:    addi a0, a0, 819
1534; RV32-NEXT:    sw a0, 12(sp)
1535; RV32-NEXT:    sw a0, 8(sp)
1536; RV32-NEXT:    lui a0, 61681
1537; RV32-NEXT:    addi a0, a0, -241
1538; RV32-NEXT:    sw a0, 12(sp)
1539; RV32-NEXT:    sw a0, 8(sp)
1540; RV32-NEXT:    lui a0, 4112
1541; RV32-NEXT:    addi a0, a0, 257
1542; RV32-NEXT:    sw a0, 12(sp)
1543; RV32-NEXT:    sw a0, 8(sp)
1544; RV32-NEXT:    li a0, 1
1545; RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
1546; RV32-NEXT:    vsub.vx v10, v8, a0
1547; RV32-NEXT:    vnot.v v8, v8
1548; RV32-NEXT:    addi a0, sp, 8
1549; RV32-NEXT:    vlse64.v v12, (a0), zero
1550; RV32-NEXT:    vand.vv v8, v8, v10
1551; RV32-NEXT:    addi a0, sp, 8
1552; RV32-NEXT:    vlse64.v v10, (a0), zero
1553; RV32-NEXT:    vsrl.vi v14, v8, 1
1554; RV32-NEXT:    vand.vv v12, v14, v12
1555; RV32-NEXT:    vsub.vv v8, v8, v12
1556; RV32-NEXT:    vand.vv v12, v8, v10
1557; RV32-NEXT:    vsrl.vi v8, v8, 2
1558; RV32-NEXT:    vand.vv v8, v8, v10
1559; RV32-NEXT:    vadd.vv v8, v12, v8
1560; RV32-NEXT:    addi a0, sp, 8
1561; RV32-NEXT:    vlse64.v v10, (a0), zero
1562; RV32-NEXT:    addi a0, sp, 8
1563; RV32-NEXT:    vlse64.v v12, (a0), zero
1564; RV32-NEXT:    vsrl.vi v14, v8, 4
1565; RV32-NEXT:    vadd.vv v8, v8, v14
1566; RV32-NEXT:    vand.vv v8, v8, v10
1567; RV32-NEXT:    vmul.vv v8, v8, v12
1568; RV32-NEXT:    li a0, 56
1569; RV32-NEXT:    vsrl.vx v8, v8, a0
1570; RV32-NEXT:    addi sp, sp, 16
1571; RV32-NEXT:    ret
1572;
1573; RV64-LABEL: cttz_nxv2i64:
1574; RV64:       # %bb.0:
1575; RV64-NEXT:    li a0, 1
1576; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
1577; RV64-NEXT:    vsub.vx v10, v8, a0
1578; RV64-NEXT:    vnot.v v8, v8
1579; RV64-NEXT:    vand.vv v8, v8, v10
1580; RV64-NEXT:    lui a0, %hi(.LCPI19_0)
1581; RV64-NEXT:    ld a0, %lo(.LCPI19_0)(a0)
1582; RV64-NEXT:    lui a1, %hi(.LCPI19_1)
1583; RV64-NEXT:    ld a1, %lo(.LCPI19_1)(a1)
1584; RV64-NEXT:    vsrl.vi v10, v8, 1
1585; RV64-NEXT:    vand.vx v10, v10, a0
1586; RV64-NEXT:    vsub.vv v8, v8, v10
1587; RV64-NEXT:    vand.vx v10, v8, a1
1588; RV64-NEXT:    vsrl.vi v8, v8, 2
1589; RV64-NEXT:    vand.vx v8, v8, a1
1590; RV64-NEXT:    vadd.vv v8, v10, v8
1591; RV64-NEXT:    lui a0, %hi(.LCPI19_2)
1592; RV64-NEXT:    ld a0, %lo(.LCPI19_2)(a0)
1593; RV64-NEXT:    lui a1, %hi(.LCPI19_3)
1594; RV64-NEXT:    ld a1, %lo(.LCPI19_3)(a1)
1595; RV64-NEXT:    vsrl.vi v10, v8, 4
1596; RV64-NEXT:    vadd.vv v8, v8, v10
1597; RV64-NEXT:    vand.vx v8, v8, a0
1598; RV64-NEXT:    vmul.vx v8, v8, a1
1599; RV64-NEXT:    li a0, 56
1600; RV64-NEXT:    vsrl.vx v8, v8, a0
1601; RV64-NEXT:    ret
1602  %a = call <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 false)
1603  ret <vscale x 2 x i64> %a
1604}
1605declare <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64>, i1)
1606
1607define <vscale x 4 x i64> @cttz_nxv4i64(<vscale x 4 x i64> %va) {
1608; RV32-LABEL: cttz_nxv4i64:
1609; RV32:       # %bb.0:
1610; RV32-NEXT:    addi sp, sp, -16
1611; RV32-NEXT:    .cfi_def_cfa_offset 16
1612; RV32-NEXT:    lui a0, 349525
1613; RV32-NEXT:    addi a0, a0, 1365
1614; RV32-NEXT:    sw a0, 12(sp)
1615; RV32-NEXT:    sw a0, 8(sp)
1616; RV32-NEXT:    lui a0, 209715
1617; RV32-NEXT:    addi a0, a0, 819
1618; RV32-NEXT:    sw a0, 12(sp)
1619; RV32-NEXT:    sw a0, 8(sp)
1620; RV32-NEXT:    lui a0, 61681
1621; RV32-NEXT:    addi a0, a0, -241
1622; RV32-NEXT:    sw a0, 12(sp)
1623; RV32-NEXT:    sw a0, 8(sp)
1624; RV32-NEXT:    lui a0, 4112
1625; RV32-NEXT:    addi a0, a0, 257
1626; RV32-NEXT:    sw a0, 12(sp)
1627; RV32-NEXT:    sw a0, 8(sp)
1628; RV32-NEXT:    li a0, 1
1629; RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1630; RV32-NEXT:    vsub.vx v12, v8, a0
1631; RV32-NEXT:    vnot.v v8, v8
1632; RV32-NEXT:    addi a0, sp, 8
1633; RV32-NEXT:    vlse64.v v16, (a0), zero
1634; RV32-NEXT:    vand.vv v8, v8, v12
1635; RV32-NEXT:    addi a0, sp, 8
1636; RV32-NEXT:    vlse64.v v12, (a0), zero
1637; RV32-NEXT:    vsrl.vi v20, v8, 1
1638; RV32-NEXT:    vand.vv v16, v20, v16
1639; RV32-NEXT:    vsub.vv v8, v8, v16
1640; RV32-NEXT:    vand.vv v16, v8, v12
1641; RV32-NEXT:    vsrl.vi v8, v8, 2
1642; RV32-NEXT:    vand.vv v8, v8, v12
1643; RV32-NEXT:    vadd.vv v8, v16, v8
1644; RV32-NEXT:    addi a0, sp, 8
1645; RV32-NEXT:    vlse64.v v12, (a0), zero
1646; RV32-NEXT:    addi a0, sp, 8
1647; RV32-NEXT:    vlse64.v v16, (a0), zero
1648; RV32-NEXT:    vsrl.vi v20, v8, 4
1649; RV32-NEXT:    vadd.vv v8, v8, v20
1650; RV32-NEXT:    vand.vv v8, v8, v12
1651; RV32-NEXT:    vmul.vv v8, v8, v16
1652; RV32-NEXT:    li a0, 56
1653; RV32-NEXT:    vsrl.vx v8, v8, a0
1654; RV32-NEXT:    addi sp, sp, 16
1655; RV32-NEXT:    ret
1656;
1657; RV64-LABEL: cttz_nxv4i64:
1658; RV64:       # %bb.0:
1659; RV64-NEXT:    li a0, 1
1660; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1661; RV64-NEXT:    vsub.vx v12, v8, a0
1662; RV64-NEXT:    vnot.v v8, v8
1663; RV64-NEXT:    vand.vv v8, v8, v12
1664; RV64-NEXT:    lui a0, %hi(.LCPI20_0)
1665; RV64-NEXT:    ld a0, %lo(.LCPI20_0)(a0)
1666; RV64-NEXT:    lui a1, %hi(.LCPI20_1)
1667; RV64-NEXT:    ld a1, %lo(.LCPI20_1)(a1)
1668; RV64-NEXT:    vsrl.vi v12, v8, 1
1669; RV64-NEXT:    vand.vx v12, v12, a0
1670; RV64-NEXT:    vsub.vv v8, v8, v12
1671; RV64-NEXT:    vand.vx v12, v8, a1
1672; RV64-NEXT:    vsrl.vi v8, v8, 2
1673; RV64-NEXT:    vand.vx v8, v8, a1
1674; RV64-NEXT:    vadd.vv v8, v12, v8
1675; RV64-NEXT:    lui a0, %hi(.LCPI20_2)
1676; RV64-NEXT:    ld a0, %lo(.LCPI20_2)(a0)
1677; RV64-NEXT:    lui a1, %hi(.LCPI20_3)
1678; RV64-NEXT:    ld a1, %lo(.LCPI20_3)(a1)
1679; RV64-NEXT:    vsrl.vi v12, v8, 4
1680; RV64-NEXT:    vadd.vv v8, v8, v12
1681; RV64-NEXT:    vand.vx v8, v8, a0
1682; RV64-NEXT:    vmul.vx v8, v8, a1
1683; RV64-NEXT:    li a0, 56
1684; RV64-NEXT:    vsrl.vx v8, v8, a0
1685; RV64-NEXT:    ret
1686  %a = call <vscale x 4 x i64> @llvm.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 false)
1687  ret <vscale x 4 x i64> %a
1688}
1689declare <vscale x 4 x i64> @llvm.cttz.nxv4i64(<vscale x 4 x i64>, i1)
1690
1691define <vscale x 8 x i64> @cttz_nxv8i64(<vscale x 8 x i64> %va) {
1692; RV32-LABEL: cttz_nxv8i64:
1693; RV32:       # %bb.0:
1694; RV32-NEXT:    addi sp, sp, -16
1695; RV32-NEXT:    .cfi_def_cfa_offset 16
1696; RV32-NEXT:    lui a0, 349525
1697; RV32-NEXT:    addi a0, a0, 1365
1698; RV32-NEXT:    sw a0, 12(sp)
1699; RV32-NEXT:    sw a0, 8(sp)
1700; RV32-NEXT:    lui a0, 209715
1701; RV32-NEXT:    addi a0, a0, 819
1702; RV32-NEXT:    sw a0, 12(sp)
1703; RV32-NEXT:    sw a0, 8(sp)
1704; RV32-NEXT:    lui a0, 61681
1705; RV32-NEXT:    addi a0, a0, -241
1706; RV32-NEXT:    sw a0, 12(sp)
1707; RV32-NEXT:    sw a0, 8(sp)
1708; RV32-NEXT:    lui a0, 4112
1709; RV32-NEXT:    addi a0, a0, 257
1710; RV32-NEXT:    sw a0, 12(sp)
1711; RV32-NEXT:    sw a0, 8(sp)
1712; RV32-NEXT:    li a0, 1
1713; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1714; RV32-NEXT:    vsub.vx v16, v8, a0
1715; RV32-NEXT:    vnot.v v8, v8
1716; RV32-NEXT:    addi a0, sp, 8
1717; RV32-NEXT:    vlse64.v v24, (a0), zero
1718; RV32-NEXT:    vand.vv v8, v8, v16
1719; RV32-NEXT:    addi a0, sp, 8
1720; RV32-NEXT:    vlse64.v v16, (a0), zero
1721; RV32-NEXT:    vsrl.vi v0, v8, 1
1722; RV32-NEXT:    vand.vv v24, v0, v24
1723; RV32-NEXT:    vsub.vv v8, v8, v24
1724; RV32-NEXT:    vand.vv v24, v8, v16
1725; RV32-NEXT:    vsrl.vi v8, v8, 2
1726; RV32-NEXT:    vand.vv v8, v8, v16
1727; RV32-NEXT:    vadd.vv v8, v24, v8
1728; RV32-NEXT:    addi a0, sp, 8
1729; RV32-NEXT:    vlse64.v v16, (a0), zero
1730; RV32-NEXT:    addi a0, sp, 8
1731; RV32-NEXT:    vlse64.v v24, (a0), zero
1732; RV32-NEXT:    vsrl.vi v0, v8, 4
1733; RV32-NEXT:    vadd.vv v8, v8, v0
1734; RV32-NEXT:    vand.vv v8, v8, v16
1735; RV32-NEXT:    vmul.vv v8, v8, v24
1736; RV32-NEXT:    li a0, 56
1737; RV32-NEXT:    vsrl.vx v8, v8, a0
1738; RV32-NEXT:    addi sp, sp, 16
1739; RV32-NEXT:    ret
1740;
1741; RV64-LABEL: cttz_nxv8i64:
1742; RV64:       # %bb.0:
1743; RV64-NEXT:    li a0, 1
1744; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1745; RV64-NEXT:    vsub.vx v16, v8, a0
1746; RV64-NEXT:    vnot.v v8, v8
1747; RV64-NEXT:    vand.vv v8, v8, v16
1748; RV64-NEXT:    lui a0, %hi(.LCPI21_0)
1749; RV64-NEXT:    ld a0, %lo(.LCPI21_0)(a0)
1750; RV64-NEXT:    lui a1, %hi(.LCPI21_1)
1751; RV64-NEXT:    ld a1, %lo(.LCPI21_1)(a1)
1752; RV64-NEXT:    vsrl.vi v16, v8, 1
1753; RV64-NEXT:    vand.vx v16, v16, a0
1754; RV64-NEXT:    vsub.vv v8, v8, v16
1755; RV64-NEXT:    vand.vx v16, v8, a1
1756; RV64-NEXT:    vsrl.vi v8, v8, 2
1757; RV64-NEXT:    vand.vx v8, v8, a1
1758; RV64-NEXT:    vadd.vv v8, v16, v8
1759; RV64-NEXT:    lui a0, %hi(.LCPI21_2)
1760; RV64-NEXT:    ld a0, %lo(.LCPI21_2)(a0)
1761; RV64-NEXT:    lui a1, %hi(.LCPI21_3)
1762; RV64-NEXT:    ld a1, %lo(.LCPI21_3)(a1)
1763; RV64-NEXT:    vsrl.vi v16, v8, 4
1764; RV64-NEXT:    vadd.vv v8, v8, v16
1765; RV64-NEXT:    vand.vx v8, v8, a0
1766; RV64-NEXT:    vmul.vx v8, v8, a1
1767; RV64-NEXT:    li a0, 56
1768; RV64-NEXT:    vsrl.vx v8, v8, a0
1769; RV64-NEXT:    ret
1770  %a = call <vscale x 8 x i64> @llvm.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 false)
1771  ret <vscale x 8 x i64> %a
1772}
1773declare <vscale x 8 x i64> @llvm.cttz.nxv8i64(<vscale x 8 x i64>, i1)
1774
1775define <vscale x 1 x i8> @cttz_zero_undef_nxv1i8(<vscale x 1 x i8> %va) {
1776; RV32I-LABEL: cttz_zero_undef_nxv1i8:
1777; RV32I:       # %bb.0:
1778; RV32I-NEXT:    li a0, 1
1779; RV32I-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
1780; RV32I-NEXT:    vsub.vx v9, v8, a0
1781; RV32I-NEXT:    vnot.v v8, v8
1782; RV32I-NEXT:    vand.vv v8, v8, v9
1783; RV32I-NEXT:    vsrl.vi v9, v8, 1
1784; RV32I-NEXT:    li a0, 85
1785; RV32I-NEXT:    vand.vx v9, v9, a0
1786; RV32I-NEXT:    vsub.vv v8, v8, v9
1787; RV32I-NEXT:    li a0, 51
1788; RV32I-NEXT:    vand.vx v9, v8, a0
1789; RV32I-NEXT:    vsrl.vi v8, v8, 2
1790; RV32I-NEXT:    vand.vx v8, v8, a0
1791; RV32I-NEXT:    vadd.vv v8, v9, v8
1792; RV32I-NEXT:    vsrl.vi v9, v8, 4
1793; RV32I-NEXT:    vadd.vv v8, v8, v9
1794; RV32I-NEXT:    vand.vi v8, v8, 15
1795; RV32I-NEXT:    ret
1796;
1797; RV64I-LABEL: cttz_zero_undef_nxv1i8:
1798; RV64I:       # %bb.0:
1799; RV64I-NEXT:    li a0, 1
1800; RV64I-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
1801; RV64I-NEXT:    vsub.vx v9, v8, a0
1802; RV64I-NEXT:    vnot.v v8, v8
1803; RV64I-NEXT:    vand.vv v8, v8, v9
1804; RV64I-NEXT:    vsrl.vi v9, v8, 1
1805; RV64I-NEXT:    li a0, 85
1806; RV64I-NEXT:    vand.vx v9, v9, a0
1807; RV64I-NEXT:    vsub.vv v8, v8, v9
1808; RV64I-NEXT:    li a0, 51
1809; RV64I-NEXT:    vand.vx v9, v8, a0
1810; RV64I-NEXT:    vsrl.vi v8, v8, 2
1811; RV64I-NEXT:    vand.vx v8, v8, a0
1812; RV64I-NEXT:    vadd.vv v8, v9, v8
1813; RV64I-NEXT:    vsrl.vi v9, v8, 4
1814; RV64I-NEXT:    vadd.vv v8, v8, v9
1815; RV64I-NEXT:    vand.vi v8, v8, 15
1816; RV64I-NEXT:    ret
1817;
1818; RV32D-LABEL: cttz_zero_undef_nxv1i8:
1819; RV32D:       # %bb.0:
1820; RV32D-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
1821; RV32D-NEXT:    vrsub.vi v9, v8, 0
1822; RV32D-NEXT:    vand.vv v8, v8, v9
1823; RV32D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
1824; RV32D-NEXT:    vzext.vf4 v9, v8
1825; RV32D-NEXT:    vfcvt.f.xu.v v8, v9
1826; RV32D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
1827; RV32D-NEXT:    vnsrl.wi v8, v8, 23
1828; RV32D-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
1829; RV32D-NEXT:    vncvt.x.x.w v8, v8
1830; RV32D-NEXT:    li a0, 127
1831; RV32D-NEXT:    vsub.vx v8, v8, a0
1832; RV32D-NEXT:    ret
1833;
1834; RV64D-LABEL: cttz_zero_undef_nxv1i8:
1835; RV64D:       # %bb.0:
1836; RV64D-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
1837; RV64D-NEXT:    vrsub.vi v9, v8, 0
1838; RV64D-NEXT:    vand.vv v8, v8, v9
1839; RV64D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
1840; RV64D-NEXT:    vzext.vf4 v9, v8
1841; RV64D-NEXT:    vfcvt.f.xu.v v8, v9
1842; RV64D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
1843; RV64D-NEXT:    vnsrl.wi v8, v8, 23
1844; RV64D-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
1845; RV64D-NEXT:    vncvt.x.x.w v8, v8
1846; RV64D-NEXT:    li a0, 127
1847; RV64D-NEXT:    vsub.vx v8, v8, a0
1848; RV64D-NEXT:    ret
1849  %a = call <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 true)
1850  ret <vscale x 1 x i8> %a
1851}
1852
1853define <vscale x 2 x i8> @cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va) {
1854; RV32I-LABEL: cttz_zero_undef_nxv2i8:
1855; RV32I:       # %bb.0:
1856; RV32I-NEXT:    li a0, 1
1857; RV32I-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
1858; RV32I-NEXT:    vsub.vx v9, v8, a0
1859; RV32I-NEXT:    vnot.v v8, v8
1860; RV32I-NEXT:    vand.vv v8, v8, v9
1861; RV32I-NEXT:    vsrl.vi v9, v8, 1
1862; RV32I-NEXT:    li a0, 85
1863; RV32I-NEXT:    vand.vx v9, v9, a0
1864; RV32I-NEXT:    vsub.vv v8, v8, v9
1865; RV32I-NEXT:    li a0, 51
1866; RV32I-NEXT:    vand.vx v9, v8, a0
1867; RV32I-NEXT:    vsrl.vi v8, v8, 2
1868; RV32I-NEXT:    vand.vx v8, v8, a0
1869; RV32I-NEXT:    vadd.vv v8, v9, v8
1870; RV32I-NEXT:    vsrl.vi v9, v8, 4
1871; RV32I-NEXT:    vadd.vv v8, v8, v9
1872; RV32I-NEXT:    vand.vi v8, v8, 15
1873; RV32I-NEXT:    ret
1874;
1875; RV64I-LABEL: cttz_zero_undef_nxv2i8:
1876; RV64I:       # %bb.0:
1877; RV64I-NEXT:    li a0, 1
1878; RV64I-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
1879; RV64I-NEXT:    vsub.vx v9, v8, a0
1880; RV64I-NEXT:    vnot.v v8, v8
1881; RV64I-NEXT:    vand.vv v8, v8, v9
1882; RV64I-NEXT:    vsrl.vi v9, v8, 1
1883; RV64I-NEXT:    li a0, 85
1884; RV64I-NEXT:    vand.vx v9, v9, a0
1885; RV64I-NEXT:    vsub.vv v8, v8, v9
1886; RV64I-NEXT:    li a0, 51
1887; RV64I-NEXT:    vand.vx v9, v8, a0
1888; RV64I-NEXT:    vsrl.vi v8, v8, 2
1889; RV64I-NEXT:    vand.vx v8, v8, a0
1890; RV64I-NEXT:    vadd.vv v8, v9, v8
1891; RV64I-NEXT:    vsrl.vi v9, v8, 4
1892; RV64I-NEXT:    vadd.vv v8, v8, v9
1893; RV64I-NEXT:    vand.vi v8, v8, 15
1894; RV64I-NEXT:    ret
1895;
1896; RV32D-LABEL: cttz_zero_undef_nxv2i8:
1897; RV32D:       # %bb.0:
1898; RV32D-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
1899; RV32D-NEXT:    vrsub.vi v9, v8, 0
1900; RV32D-NEXT:    vand.vv v8, v8, v9
1901; RV32D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
1902; RV32D-NEXT:    vzext.vf4 v9, v8
1903; RV32D-NEXT:    vfcvt.f.xu.v v8, v9
1904; RV32D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
1905; RV32D-NEXT:    vnsrl.wi v8, v8, 23
1906; RV32D-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
1907; RV32D-NEXT:    vncvt.x.x.w v8, v8
1908; RV32D-NEXT:    li a0, 127
1909; RV32D-NEXT:    vsub.vx v8, v8, a0
1910; RV32D-NEXT:    ret
1911;
1912; RV64D-LABEL: cttz_zero_undef_nxv2i8:
1913; RV64D:       # %bb.0:
1914; RV64D-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
1915; RV64D-NEXT:    vrsub.vi v9, v8, 0
1916; RV64D-NEXT:    vand.vv v8, v8, v9
1917; RV64D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
1918; RV64D-NEXT:    vzext.vf4 v9, v8
1919; RV64D-NEXT:    vfcvt.f.xu.v v8, v9
1920; RV64D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
1921; RV64D-NEXT:    vnsrl.wi v8, v8, 23
1922; RV64D-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
1923; RV64D-NEXT:    vncvt.x.x.w v8, v8
1924; RV64D-NEXT:    li a0, 127
1925; RV64D-NEXT:    vsub.vx v8, v8, a0
1926; RV64D-NEXT:    ret
1927  %a = call <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 true)
1928  ret <vscale x 2 x i8> %a
1929}
1930
1931define <vscale x 4 x i8> @cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va) {
1932; RV32I-LABEL: cttz_zero_undef_nxv4i8:
1933; RV32I:       # %bb.0:
1934; RV32I-NEXT:    li a0, 1
1935; RV32I-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
1936; RV32I-NEXT:    vsub.vx v9, v8, a0
1937; RV32I-NEXT:    vnot.v v8, v8
1938; RV32I-NEXT:    vand.vv v8, v8, v9
1939; RV32I-NEXT:    vsrl.vi v9, v8, 1
1940; RV32I-NEXT:    li a0, 85
1941; RV32I-NEXT:    vand.vx v9, v9, a0
1942; RV32I-NEXT:    vsub.vv v8, v8, v9
1943; RV32I-NEXT:    li a0, 51
1944; RV32I-NEXT:    vand.vx v9, v8, a0
1945; RV32I-NEXT:    vsrl.vi v8, v8, 2
1946; RV32I-NEXT:    vand.vx v8, v8, a0
1947; RV32I-NEXT:    vadd.vv v8, v9, v8
1948; RV32I-NEXT:    vsrl.vi v9, v8, 4
1949; RV32I-NEXT:    vadd.vv v8, v8, v9
1950; RV32I-NEXT:    vand.vi v8, v8, 15
1951; RV32I-NEXT:    ret
1952;
1953; RV64I-LABEL: cttz_zero_undef_nxv4i8:
1954; RV64I:       # %bb.0:
1955; RV64I-NEXT:    li a0, 1
1956; RV64I-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
1957; RV64I-NEXT:    vsub.vx v9, v8, a0
1958; RV64I-NEXT:    vnot.v v8, v8
1959; RV64I-NEXT:    vand.vv v8, v8, v9
1960; RV64I-NEXT:    vsrl.vi v9, v8, 1
1961; RV64I-NEXT:    li a0, 85
1962; RV64I-NEXT:    vand.vx v9, v9, a0
1963; RV64I-NEXT:    vsub.vv v8, v8, v9
1964; RV64I-NEXT:    li a0, 51
1965; RV64I-NEXT:    vand.vx v9, v8, a0
1966; RV64I-NEXT:    vsrl.vi v8, v8, 2
1967; RV64I-NEXT:    vand.vx v8, v8, a0
1968; RV64I-NEXT:    vadd.vv v8, v9, v8
1969; RV64I-NEXT:    vsrl.vi v9, v8, 4
1970; RV64I-NEXT:    vadd.vv v8, v8, v9
1971; RV64I-NEXT:    vand.vi v8, v8, 15
1972; RV64I-NEXT:    ret
1973;
1974; RV32D-LABEL: cttz_zero_undef_nxv4i8:
1975; RV32D:       # %bb.0:
1976; RV32D-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
1977; RV32D-NEXT:    vrsub.vi v9, v8, 0
1978; RV32D-NEXT:    vand.vv v8, v8, v9
1979; RV32D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
1980; RV32D-NEXT:    vzext.vf4 v10, v8
1981; RV32D-NEXT:    vfcvt.f.xu.v v8, v10
1982; RV32D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
1983; RV32D-NEXT:    vnsrl.wi v10, v8, 23
1984; RV32D-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
1985; RV32D-NEXT:    vncvt.x.x.w v8, v10
1986; RV32D-NEXT:    li a0, 127
1987; RV32D-NEXT:    vsub.vx v8, v8, a0
1988; RV32D-NEXT:    ret
1989;
1990; RV64D-LABEL: cttz_zero_undef_nxv4i8:
1991; RV64D:       # %bb.0:
1992; RV64D-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
1993; RV64D-NEXT:    vrsub.vi v9, v8, 0
1994; RV64D-NEXT:    vand.vv v8, v8, v9
1995; RV64D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
1996; RV64D-NEXT:    vzext.vf4 v10, v8
1997; RV64D-NEXT:    vfcvt.f.xu.v v8, v10
1998; RV64D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
1999; RV64D-NEXT:    vnsrl.wi v10, v8, 23
2000; RV64D-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
2001; RV64D-NEXT:    vncvt.x.x.w v8, v10
2002; RV64D-NEXT:    li a0, 127
2003; RV64D-NEXT:    vsub.vx v8, v8, a0
2004; RV64D-NEXT:    ret
2005  %a = call <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 true)
2006  ret <vscale x 4 x i8> %a
2007}
2008
2009define <vscale x 8 x i8> @cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va) {
2010; RV32I-LABEL: cttz_zero_undef_nxv8i8:
2011; RV32I:       # %bb.0:
2012; RV32I-NEXT:    li a0, 1
2013; RV32I-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
2014; RV32I-NEXT:    vsub.vx v9, v8, a0
2015; RV32I-NEXT:    vnot.v v8, v8
2016; RV32I-NEXT:    vand.vv v8, v8, v9
2017; RV32I-NEXT:    vsrl.vi v9, v8, 1
2018; RV32I-NEXT:    li a0, 85
2019; RV32I-NEXT:    vand.vx v9, v9, a0
2020; RV32I-NEXT:    vsub.vv v8, v8, v9
2021; RV32I-NEXT:    li a0, 51
2022; RV32I-NEXT:    vand.vx v9, v8, a0
2023; RV32I-NEXT:    vsrl.vi v8, v8, 2
2024; RV32I-NEXT:    vand.vx v8, v8, a0
2025; RV32I-NEXT:    vadd.vv v8, v9, v8
2026; RV32I-NEXT:    vsrl.vi v9, v8, 4
2027; RV32I-NEXT:    vadd.vv v8, v8, v9
2028; RV32I-NEXT:    vand.vi v8, v8, 15
2029; RV32I-NEXT:    ret
2030;
2031; RV64I-LABEL: cttz_zero_undef_nxv8i8:
2032; RV64I:       # %bb.0:
2033; RV64I-NEXT:    li a0, 1
2034; RV64I-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
2035; RV64I-NEXT:    vsub.vx v9, v8, a0
2036; RV64I-NEXT:    vnot.v v8, v8
2037; RV64I-NEXT:    vand.vv v8, v8, v9
2038; RV64I-NEXT:    vsrl.vi v9, v8, 1
2039; RV64I-NEXT:    li a0, 85
2040; RV64I-NEXT:    vand.vx v9, v9, a0
2041; RV64I-NEXT:    vsub.vv v8, v8, v9
2042; RV64I-NEXT:    li a0, 51
2043; RV64I-NEXT:    vand.vx v9, v8, a0
2044; RV64I-NEXT:    vsrl.vi v8, v8, 2
2045; RV64I-NEXT:    vand.vx v8, v8, a0
2046; RV64I-NEXT:    vadd.vv v8, v9, v8
2047; RV64I-NEXT:    vsrl.vi v9, v8, 4
2048; RV64I-NEXT:    vadd.vv v8, v8, v9
2049; RV64I-NEXT:    vand.vi v8, v8, 15
2050; RV64I-NEXT:    ret
2051;
2052; RV32D-LABEL: cttz_zero_undef_nxv8i8:
2053; RV32D:       # %bb.0:
2054; RV32D-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
2055; RV32D-NEXT:    vrsub.vi v9, v8, 0
2056; RV32D-NEXT:    vand.vv v8, v8, v9
2057; RV32D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
2058; RV32D-NEXT:    vzext.vf4 v12, v8
2059; RV32D-NEXT:    vfcvt.f.xu.v v8, v12
2060; RV32D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
2061; RV32D-NEXT:    vnsrl.wi v12, v8, 23
2062; RV32D-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
2063; RV32D-NEXT:    vncvt.x.x.w v8, v12
2064; RV32D-NEXT:    li a0, 127
2065; RV32D-NEXT:    vsub.vx v8, v8, a0
2066; RV32D-NEXT:    ret
2067;
2068; RV64D-LABEL: cttz_zero_undef_nxv8i8:
2069; RV64D:       # %bb.0:
2070; RV64D-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
2071; RV64D-NEXT:    vrsub.vi v9, v8, 0
2072; RV64D-NEXT:    vand.vv v8, v8, v9
2073; RV64D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
2074; RV64D-NEXT:    vzext.vf4 v12, v8
2075; RV64D-NEXT:    vfcvt.f.xu.v v8, v12
2076; RV64D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
2077; RV64D-NEXT:    vnsrl.wi v12, v8, 23
2078; RV64D-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
2079; RV64D-NEXT:    vncvt.x.x.w v8, v12
2080; RV64D-NEXT:    li a0, 127
2081; RV64D-NEXT:    vsub.vx v8, v8, a0
2082; RV64D-NEXT:    ret
2083  %a = call <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 true)
2084  ret <vscale x 8 x i8> %a
2085}
2086
2087define <vscale x 16 x i8> @cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) {
2088; RV32I-LABEL: cttz_zero_undef_nxv16i8:
2089; RV32I:       # %bb.0:
2090; RV32I-NEXT:    li a0, 1
2091; RV32I-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
2092; RV32I-NEXT:    vsub.vx v10, v8, a0
2093; RV32I-NEXT:    vnot.v v8, v8
2094; RV32I-NEXT:    vand.vv v8, v8, v10
2095; RV32I-NEXT:    vsrl.vi v10, v8, 1
2096; RV32I-NEXT:    li a0, 85
2097; RV32I-NEXT:    vand.vx v10, v10, a0
2098; RV32I-NEXT:    vsub.vv v8, v8, v10
2099; RV32I-NEXT:    li a0, 51
2100; RV32I-NEXT:    vand.vx v10, v8, a0
2101; RV32I-NEXT:    vsrl.vi v8, v8, 2
2102; RV32I-NEXT:    vand.vx v8, v8, a0
2103; RV32I-NEXT:    vadd.vv v8, v10, v8
2104; RV32I-NEXT:    vsrl.vi v10, v8, 4
2105; RV32I-NEXT:    vadd.vv v8, v8, v10
2106; RV32I-NEXT:    vand.vi v8, v8, 15
2107; RV32I-NEXT:    ret
2108;
2109; RV64I-LABEL: cttz_zero_undef_nxv16i8:
2110; RV64I:       # %bb.0:
2111; RV64I-NEXT:    li a0, 1
2112; RV64I-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
2113; RV64I-NEXT:    vsub.vx v10, v8, a0
2114; RV64I-NEXT:    vnot.v v8, v8
2115; RV64I-NEXT:    vand.vv v8, v8, v10
2116; RV64I-NEXT:    vsrl.vi v10, v8, 1
2117; RV64I-NEXT:    li a0, 85
2118; RV64I-NEXT:    vand.vx v10, v10, a0
2119; RV64I-NEXT:    vsub.vv v8, v8, v10
2120; RV64I-NEXT:    li a0, 51
2121; RV64I-NEXT:    vand.vx v10, v8, a0
2122; RV64I-NEXT:    vsrl.vi v8, v8, 2
2123; RV64I-NEXT:    vand.vx v8, v8, a0
2124; RV64I-NEXT:    vadd.vv v8, v10, v8
2125; RV64I-NEXT:    vsrl.vi v10, v8, 4
2126; RV64I-NEXT:    vadd.vv v8, v8, v10
2127; RV64I-NEXT:    vand.vi v8, v8, 15
2128; RV64I-NEXT:    ret
2129;
2130; RV32D-LABEL: cttz_zero_undef_nxv16i8:
2131; RV32D:       # %bb.0:
2132; RV32D-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
2133; RV32D-NEXT:    vrsub.vi v10, v8, 0
2134; RV32D-NEXT:    vand.vv v8, v8, v10
2135; RV32D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
2136; RV32D-NEXT:    vzext.vf4 v16, v8
2137; RV32D-NEXT:    vfcvt.f.xu.v v8, v16
2138; RV32D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
2139; RV32D-NEXT:    vnsrl.wi v16, v8, 23
2140; RV32D-NEXT:    vsetvli zero, zero, e8, m2, ta, mu
2141; RV32D-NEXT:    vncvt.x.x.w v8, v16
2142; RV32D-NEXT:    li a0, 127
2143; RV32D-NEXT:    vsub.vx v8, v8, a0
2144; RV32D-NEXT:    ret
2145;
2146; RV64D-LABEL: cttz_zero_undef_nxv16i8:
2147; RV64D:       # %bb.0:
2148; RV64D-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
2149; RV64D-NEXT:    vrsub.vi v10, v8, 0
2150; RV64D-NEXT:    vand.vv v8, v8, v10
2151; RV64D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
2152; RV64D-NEXT:    vzext.vf4 v16, v8
2153; RV64D-NEXT:    vfcvt.f.xu.v v8, v16
2154; RV64D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
2155; RV64D-NEXT:    vnsrl.wi v16, v8, 23
2156; RV64D-NEXT:    vsetvli zero, zero, e8, m2, ta, mu
2157; RV64D-NEXT:    vncvt.x.x.w v8, v16
2158; RV64D-NEXT:    li a0, 127
2159; RV64D-NEXT:    vsub.vx v8, v8, a0
2160; RV64D-NEXT:    ret
2161  %a = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 true)
2162  ret <vscale x 16 x i8> %a
2163}
2164
2165define <vscale x 32 x i8> @cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va) {
2166; CHECK-LABEL: cttz_zero_undef_nxv32i8:
2167; CHECK:       # %bb.0:
2168; CHECK-NEXT:    li a0, 1
2169; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
2170; CHECK-NEXT:    vsub.vx v12, v8, a0
2171; CHECK-NEXT:    vnot.v v8, v8
2172; CHECK-NEXT:    vand.vv v8, v8, v12
2173; CHECK-NEXT:    vsrl.vi v12, v8, 1
2174; CHECK-NEXT:    li a0, 85
2175; CHECK-NEXT:    vand.vx v12, v12, a0
2176; CHECK-NEXT:    vsub.vv v8, v8, v12
2177; CHECK-NEXT:    li a0, 51
2178; CHECK-NEXT:    vand.vx v12, v8, a0
2179; CHECK-NEXT:    vsrl.vi v8, v8, 2
2180; CHECK-NEXT:    vand.vx v8, v8, a0
2181; CHECK-NEXT:    vadd.vv v8, v12, v8
2182; CHECK-NEXT:    vsrl.vi v12, v8, 4
2183; CHECK-NEXT:    vadd.vv v8, v8, v12
2184; CHECK-NEXT:    vand.vi v8, v8, 15
2185; CHECK-NEXT:    ret
2186  %a = call <vscale x 32 x i8> @llvm.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 true)
2187  ret <vscale x 32 x i8> %a
2188}
2189
2190define <vscale x 64 x i8> @cttz_zero_undef_nxv64i8(<vscale x 64 x i8> %va) {
2191; CHECK-LABEL: cttz_zero_undef_nxv64i8:
2192; CHECK:       # %bb.0:
2193; CHECK-NEXT:    li a0, 1
2194; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
2195; CHECK-NEXT:    vsub.vx v16, v8, a0
2196; CHECK-NEXT:    vnot.v v8, v8
2197; CHECK-NEXT:    vand.vv v8, v8, v16
2198; CHECK-NEXT:    vsrl.vi v16, v8, 1
2199; CHECK-NEXT:    li a0, 85
2200; CHECK-NEXT:    vand.vx v16, v16, a0
2201; CHECK-NEXT:    vsub.vv v8, v8, v16
2202; CHECK-NEXT:    li a0, 51
2203; CHECK-NEXT:    vand.vx v16, v8, a0
2204; CHECK-NEXT:    vsrl.vi v8, v8, 2
2205; CHECK-NEXT:    vand.vx v8, v8, a0
2206; CHECK-NEXT:    vadd.vv v8, v16, v8
2207; CHECK-NEXT:    vsrl.vi v16, v8, 4
2208; CHECK-NEXT:    vadd.vv v8, v8, v16
2209; CHECK-NEXT:    vand.vi v8, v8, 15
2210; CHECK-NEXT:    ret
2211  %a = call <vscale x 64 x i8> @llvm.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 true)
2212  ret <vscale x 64 x i8> %a
2213}
2214
2215define <vscale x 1 x i16> @cttz_zero_undef_nxv1i16(<vscale x 1 x i16> %va) {
2216; RV32I-LABEL: cttz_zero_undef_nxv1i16:
2217; RV32I:       # %bb.0:
2218; RV32I-NEXT:    li a0, 1
2219; RV32I-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
2220; RV32I-NEXT:    vsub.vx v9, v8, a0
2221; RV32I-NEXT:    vnot.v v8, v8
2222; RV32I-NEXT:    vand.vv v8, v8, v9
2223; RV32I-NEXT:    vsrl.vi v9, v8, 1
2224; RV32I-NEXT:    lui a0, 5
2225; RV32I-NEXT:    addi a0, a0, 1365
2226; RV32I-NEXT:    vand.vx v9, v9, a0
2227; RV32I-NEXT:    vsub.vv v8, v8, v9
2228; RV32I-NEXT:    lui a0, 3
2229; RV32I-NEXT:    addi a0, a0, 819
2230; RV32I-NEXT:    vand.vx v9, v8, a0
2231; RV32I-NEXT:    vsrl.vi v8, v8, 2
2232; RV32I-NEXT:    vand.vx v8, v8, a0
2233; RV32I-NEXT:    vadd.vv v8, v9, v8
2234; RV32I-NEXT:    vsrl.vi v9, v8, 4
2235; RV32I-NEXT:    vadd.vv v8, v8, v9
2236; RV32I-NEXT:    lui a0, 1
2237; RV32I-NEXT:    addi a0, a0, -241
2238; RV32I-NEXT:    vand.vx v8, v8, a0
2239; RV32I-NEXT:    li a0, 257
2240; RV32I-NEXT:    vmul.vx v8, v8, a0
2241; RV32I-NEXT:    vsrl.vi v8, v8, 8
2242; RV32I-NEXT:    ret
2243;
2244; RV64I-LABEL: cttz_zero_undef_nxv1i16:
2245; RV64I:       # %bb.0:
2246; RV64I-NEXT:    li a0, 1
2247; RV64I-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
2248; RV64I-NEXT:    vsub.vx v9, v8, a0
2249; RV64I-NEXT:    vnot.v v8, v8
2250; RV64I-NEXT:    vand.vv v8, v8, v9
2251; RV64I-NEXT:    vsrl.vi v9, v8, 1
2252; RV64I-NEXT:    lui a0, 5
2253; RV64I-NEXT:    addiw a0, a0, 1365
2254; RV64I-NEXT:    vand.vx v9, v9, a0
2255; RV64I-NEXT:    vsub.vv v8, v8, v9
2256; RV64I-NEXT:    lui a0, 3
2257; RV64I-NEXT:    addiw a0, a0, 819
2258; RV64I-NEXT:    vand.vx v9, v8, a0
2259; RV64I-NEXT:    vsrl.vi v8, v8, 2
2260; RV64I-NEXT:    vand.vx v8, v8, a0
2261; RV64I-NEXT:    vadd.vv v8, v9, v8
2262; RV64I-NEXT:    vsrl.vi v9, v8, 4
2263; RV64I-NEXT:    vadd.vv v8, v8, v9
2264; RV64I-NEXT:    lui a0, 1
2265; RV64I-NEXT:    addiw a0, a0, -241
2266; RV64I-NEXT:    vand.vx v8, v8, a0
2267; RV64I-NEXT:    li a0, 257
2268; RV64I-NEXT:    vmul.vx v8, v8, a0
2269; RV64I-NEXT:    vsrl.vi v8, v8, 8
2270; RV64I-NEXT:    ret
2271;
2272; RV32D-LABEL: cttz_zero_undef_nxv1i16:
2273; RV32D:       # %bb.0:
2274; RV32D-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
2275; RV32D-NEXT:    vrsub.vi v9, v8, 0
2276; RV32D-NEXT:    vand.vv v8, v8, v9
2277; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
2278; RV32D-NEXT:    vnsrl.wi v8, v9, 23
2279; RV32D-NEXT:    li a0, 127
2280; RV32D-NEXT:    vsub.vx v8, v8, a0
2281; RV32D-NEXT:    ret
2282;
2283; RV64D-LABEL: cttz_zero_undef_nxv1i16:
2284; RV64D:       # %bb.0:
2285; RV64D-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
2286; RV64D-NEXT:    vrsub.vi v9, v8, 0
2287; RV64D-NEXT:    vand.vv v8, v8, v9
2288; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
2289; RV64D-NEXT:    vnsrl.wi v8, v9, 23
2290; RV64D-NEXT:    li a0, 127
2291; RV64D-NEXT:    vsub.vx v8, v8, a0
2292; RV64D-NEXT:    ret
2293  %a = call <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 true)
2294  ret <vscale x 1 x i16> %a
2295}
2296
2297define <vscale x 2 x i16> @cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) {
2298; RV32I-LABEL: cttz_zero_undef_nxv2i16:
2299; RV32I:       # %bb.0:
2300; RV32I-NEXT:    li a0, 1
2301; RV32I-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
2302; RV32I-NEXT:    vsub.vx v9, v8, a0
2303; RV32I-NEXT:    vnot.v v8, v8
2304; RV32I-NEXT:    vand.vv v8, v8, v9
2305; RV32I-NEXT:    vsrl.vi v9, v8, 1
2306; RV32I-NEXT:    lui a0, 5
2307; RV32I-NEXT:    addi a0, a0, 1365
2308; RV32I-NEXT:    vand.vx v9, v9, a0
2309; RV32I-NEXT:    vsub.vv v8, v8, v9
2310; RV32I-NEXT:    lui a0, 3
2311; RV32I-NEXT:    addi a0, a0, 819
2312; RV32I-NEXT:    vand.vx v9, v8, a0
2313; RV32I-NEXT:    vsrl.vi v8, v8, 2
2314; RV32I-NEXT:    vand.vx v8, v8, a0
2315; RV32I-NEXT:    vadd.vv v8, v9, v8
2316; RV32I-NEXT:    vsrl.vi v9, v8, 4
2317; RV32I-NEXT:    vadd.vv v8, v8, v9
2318; RV32I-NEXT:    lui a0, 1
2319; RV32I-NEXT:    addi a0, a0, -241
2320; RV32I-NEXT:    vand.vx v8, v8, a0
2321; RV32I-NEXT:    li a0, 257
2322; RV32I-NEXT:    vmul.vx v8, v8, a0
2323; RV32I-NEXT:    vsrl.vi v8, v8, 8
2324; RV32I-NEXT:    ret
2325;
2326; RV64I-LABEL: cttz_zero_undef_nxv2i16:
2327; RV64I:       # %bb.0:
2328; RV64I-NEXT:    li a0, 1
2329; RV64I-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
2330; RV64I-NEXT:    vsub.vx v9, v8, a0
2331; RV64I-NEXT:    vnot.v v8, v8
2332; RV64I-NEXT:    vand.vv v8, v8, v9
2333; RV64I-NEXT:    vsrl.vi v9, v8, 1
2334; RV64I-NEXT:    lui a0, 5
2335; RV64I-NEXT:    addiw a0, a0, 1365
2336; RV64I-NEXT:    vand.vx v9, v9, a0
2337; RV64I-NEXT:    vsub.vv v8, v8, v9
2338; RV64I-NEXT:    lui a0, 3
2339; RV64I-NEXT:    addiw a0, a0, 819
2340; RV64I-NEXT:    vand.vx v9, v8, a0
2341; RV64I-NEXT:    vsrl.vi v8, v8, 2
2342; RV64I-NEXT:    vand.vx v8, v8, a0
2343; RV64I-NEXT:    vadd.vv v8, v9, v8
2344; RV64I-NEXT:    vsrl.vi v9, v8, 4
2345; RV64I-NEXT:    vadd.vv v8, v8, v9
2346; RV64I-NEXT:    lui a0, 1
2347; RV64I-NEXT:    addiw a0, a0, -241
2348; RV64I-NEXT:    vand.vx v8, v8, a0
2349; RV64I-NEXT:    li a0, 257
2350; RV64I-NEXT:    vmul.vx v8, v8, a0
2351; RV64I-NEXT:    vsrl.vi v8, v8, 8
2352; RV64I-NEXT:    ret
2353;
2354; RV32D-LABEL: cttz_zero_undef_nxv2i16:
2355; RV32D:       # %bb.0:
2356; RV32D-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
2357; RV32D-NEXT:    vrsub.vi v9, v8, 0
2358; RV32D-NEXT:    vand.vv v8, v8, v9
2359; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
2360; RV32D-NEXT:    vnsrl.wi v8, v9, 23
2361; RV32D-NEXT:    li a0, 127
2362; RV32D-NEXT:    vsub.vx v8, v8, a0
2363; RV32D-NEXT:    ret
2364;
2365; RV64D-LABEL: cttz_zero_undef_nxv2i16:
2366; RV64D:       # %bb.0:
2367; RV64D-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
2368; RV64D-NEXT:    vrsub.vi v9, v8, 0
2369; RV64D-NEXT:    vand.vv v8, v8, v9
2370; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
2371; RV64D-NEXT:    vnsrl.wi v8, v9, 23
2372; RV64D-NEXT:    li a0, 127
2373; RV64D-NEXT:    vsub.vx v8, v8, a0
2374; RV64D-NEXT:    ret
2375  %a = call <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 true)
2376  ret <vscale x 2 x i16> %a
2377}
2378
2379define <vscale x 4 x i16> @cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) {
2380; RV32I-LABEL: cttz_zero_undef_nxv4i16:
2381; RV32I:       # %bb.0:
2382; RV32I-NEXT:    li a0, 1
2383; RV32I-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
2384; RV32I-NEXT:    vsub.vx v9, v8, a0
2385; RV32I-NEXT:    vnot.v v8, v8
2386; RV32I-NEXT:    vand.vv v8, v8, v9
2387; RV32I-NEXT:    vsrl.vi v9, v8, 1
2388; RV32I-NEXT:    lui a0, 5
2389; RV32I-NEXT:    addi a0, a0, 1365
2390; RV32I-NEXT:    vand.vx v9, v9, a0
2391; RV32I-NEXT:    vsub.vv v8, v8, v9
2392; RV32I-NEXT:    lui a0, 3
2393; RV32I-NEXT:    addi a0, a0, 819
2394; RV32I-NEXT:    vand.vx v9, v8, a0
2395; RV32I-NEXT:    vsrl.vi v8, v8, 2
2396; RV32I-NEXT:    vand.vx v8, v8, a0
2397; RV32I-NEXT:    vadd.vv v8, v9, v8
2398; RV32I-NEXT:    vsrl.vi v9, v8, 4
2399; RV32I-NEXT:    vadd.vv v8, v8, v9
2400; RV32I-NEXT:    lui a0, 1
2401; RV32I-NEXT:    addi a0, a0, -241
2402; RV32I-NEXT:    vand.vx v8, v8, a0
2403; RV32I-NEXT:    li a0, 257
2404; RV32I-NEXT:    vmul.vx v8, v8, a0
2405; RV32I-NEXT:    vsrl.vi v8, v8, 8
2406; RV32I-NEXT:    ret
2407;
2408; RV64I-LABEL: cttz_zero_undef_nxv4i16:
2409; RV64I:       # %bb.0:
2410; RV64I-NEXT:    li a0, 1
2411; RV64I-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
2412; RV64I-NEXT:    vsub.vx v9, v8, a0
2413; RV64I-NEXT:    vnot.v v8, v8
2414; RV64I-NEXT:    vand.vv v8, v8, v9
2415; RV64I-NEXT:    vsrl.vi v9, v8, 1
2416; RV64I-NEXT:    lui a0, 5
2417; RV64I-NEXT:    addiw a0, a0, 1365
2418; RV64I-NEXT:    vand.vx v9, v9, a0
2419; RV64I-NEXT:    vsub.vv v8, v8, v9
2420; RV64I-NEXT:    lui a0, 3
2421; RV64I-NEXT:    addiw a0, a0, 819
2422; RV64I-NEXT:    vand.vx v9, v8, a0
2423; RV64I-NEXT:    vsrl.vi v8, v8, 2
2424; RV64I-NEXT:    vand.vx v8, v8, a0
2425; RV64I-NEXT:    vadd.vv v8, v9, v8
2426; RV64I-NEXT:    vsrl.vi v9, v8, 4
2427; RV64I-NEXT:    vadd.vv v8, v8, v9
2428; RV64I-NEXT:    lui a0, 1
2429; RV64I-NEXT:    addiw a0, a0, -241
2430; RV64I-NEXT:    vand.vx v8, v8, a0
2431; RV64I-NEXT:    li a0, 257
2432; RV64I-NEXT:    vmul.vx v8, v8, a0
2433; RV64I-NEXT:    vsrl.vi v8, v8, 8
2434; RV64I-NEXT:    ret
2435;
2436; RV32D-LABEL: cttz_zero_undef_nxv4i16:
2437; RV32D:       # %bb.0:
2438; RV32D-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
2439; RV32D-NEXT:    vrsub.vi v9, v8, 0
2440; RV32D-NEXT:    vand.vv v8, v8, v9
2441; RV32D-NEXT:    vfwcvt.f.xu.v v10, v8
2442; RV32D-NEXT:    vnsrl.wi v8, v10, 23
2443; RV32D-NEXT:    li a0, 127
2444; RV32D-NEXT:    vsub.vx v8, v8, a0
2445; RV32D-NEXT:    ret
2446;
2447; RV64D-LABEL: cttz_zero_undef_nxv4i16:
2448; RV64D:       # %bb.0:
2449; RV64D-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
2450; RV64D-NEXT:    vrsub.vi v9, v8, 0
2451; RV64D-NEXT:    vand.vv v8, v8, v9
2452; RV64D-NEXT:    vfwcvt.f.xu.v v10, v8
2453; RV64D-NEXT:    vnsrl.wi v8, v10, 23
2454; RV64D-NEXT:    li a0, 127
2455; RV64D-NEXT:    vsub.vx v8, v8, a0
2456; RV64D-NEXT:    ret
2457  %a = call <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 true)
2458  ret <vscale x 4 x i16> %a
2459}
2460
2461define <vscale x 8 x i16> @cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
2462; RV32I-LABEL: cttz_zero_undef_nxv8i16:
2463; RV32I:       # %bb.0:
2464; RV32I-NEXT:    li a0, 1
2465; RV32I-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
2466; RV32I-NEXT:    vsub.vx v10, v8, a0
2467; RV32I-NEXT:    vnot.v v8, v8
2468; RV32I-NEXT:    vand.vv v8, v8, v10
2469; RV32I-NEXT:    vsrl.vi v10, v8, 1
2470; RV32I-NEXT:    lui a0, 5
2471; RV32I-NEXT:    addi a0, a0, 1365
2472; RV32I-NEXT:    vand.vx v10, v10, a0
2473; RV32I-NEXT:    vsub.vv v8, v8, v10
2474; RV32I-NEXT:    lui a0, 3
2475; RV32I-NEXT:    addi a0, a0, 819
2476; RV32I-NEXT:    vand.vx v10, v8, a0
2477; RV32I-NEXT:    vsrl.vi v8, v8, 2
2478; RV32I-NEXT:    vand.vx v8, v8, a0
2479; RV32I-NEXT:    vadd.vv v8, v10, v8
2480; RV32I-NEXT:    vsrl.vi v10, v8, 4
2481; RV32I-NEXT:    vadd.vv v8, v8, v10
2482; RV32I-NEXT:    lui a0, 1
2483; RV32I-NEXT:    addi a0, a0, -241
2484; RV32I-NEXT:    vand.vx v8, v8, a0
2485; RV32I-NEXT:    li a0, 257
2486; RV32I-NEXT:    vmul.vx v8, v8, a0
2487; RV32I-NEXT:    vsrl.vi v8, v8, 8
2488; RV32I-NEXT:    ret
2489;
2490; RV64I-LABEL: cttz_zero_undef_nxv8i16:
2491; RV64I:       # %bb.0:
2492; RV64I-NEXT:    li a0, 1
2493; RV64I-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
2494; RV64I-NEXT:    vsub.vx v10, v8, a0
2495; RV64I-NEXT:    vnot.v v8, v8
2496; RV64I-NEXT:    vand.vv v8, v8, v10
2497; RV64I-NEXT:    vsrl.vi v10, v8, 1
2498; RV64I-NEXT:    lui a0, 5
2499; RV64I-NEXT:    addiw a0, a0, 1365
2500; RV64I-NEXT:    vand.vx v10, v10, a0
2501; RV64I-NEXT:    vsub.vv v8, v8, v10
2502; RV64I-NEXT:    lui a0, 3
2503; RV64I-NEXT:    addiw a0, a0, 819
2504; RV64I-NEXT:    vand.vx v10, v8, a0
2505; RV64I-NEXT:    vsrl.vi v8, v8, 2
2506; RV64I-NEXT:    vand.vx v8, v8, a0
2507; RV64I-NEXT:    vadd.vv v8, v10, v8
2508; RV64I-NEXT:    vsrl.vi v10, v8, 4
2509; RV64I-NEXT:    vadd.vv v8, v8, v10
2510; RV64I-NEXT:    lui a0, 1
2511; RV64I-NEXT:    addiw a0, a0, -241
2512; RV64I-NEXT:    vand.vx v8, v8, a0
2513; RV64I-NEXT:    li a0, 257
2514; RV64I-NEXT:    vmul.vx v8, v8, a0
2515; RV64I-NEXT:    vsrl.vi v8, v8, 8
2516; RV64I-NEXT:    ret
2517;
2518; RV32D-LABEL: cttz_zero_undef_nxv8i16:
2519; RV32D:       # %bb.0:
2520; RV32D-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
2521; RV32D-NEXT:    vrsub.vi v10, v8, 0
2522; RV32D-NEXT:    vand.vv v8, v8, v10
2523; RV32D-NEXT:    vfwcvt.f.xu.v v12, v8
2524; RV32D-NEXT:    vnsrl.wi v8, v12, 23
2525; RV32D-NEXT:    li a0, 127
2526; RV32D-NEXT:    vsub.vx v8, v8, a0
2527; RV32D-NEXT:    ret
2528;
2529; RV64D-LABEL: cttz_zero_undef_nxv8i16:
2530; RV64D:       # %bb.0:
2531; RV64D-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
2532; RV64D-NEXT:    vrsub.vi v10, v8, 0
2533; RV64D-NEXT:    vand.vv v8, v8, v10
2534; RV64D-NEXT:    vfwcvt.f.xu.v v12, v8
2535; RV64D-NEXT:    vnsrl.wi v8, v12, 23
2536; RV64D-NEXT:    li a0, 127
2537; RV64D-NEXT:    vsub.vx v8, v8, a0
2538; RV64D-NEXT:    ret
2539  %a = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 true)
2540  ret <vscale x 8 x i16> %a
2541}
2542
2543define <vscale x 16 x i16> @cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
2544; RV32I-LABEL: cttz_zero_undef_nxv16i16:
2545; RV32I:       # %bb.0:
2546; RV32I-NEXT:    li a0, 1
2547; RV32I-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
2548; RV32I-NEXT:    vsub.vx v12, v8, a0
2549; RV32I-NEXT:    vnot.v v8, v8
2550; RV32I-NEXT:    vand.vv v8, v8, v12
2551; RV32I-NEXT:    vsrl.vi v12, v8, 1
2552; RV32I-NEXT:    lui a0, 5
2553; RV32I-NEXT:    addi a0, a0, 1365
2554; RV32I-NEXT:    vand.vx v12, v12, a0
2555; RV32I-NEXT:    vsub.vv v8, v8, v12
2556; RV32I-NEXT:    lui a0, 3
2557; RV32I-NEXT:    addi a0, a0, 819
2558; RV32I-NEXT:    vand.vx v12, v8, a0
2559; RV32I-NEXT:    vsrl.vi v8, v8, 2
2560; RV32I-NEXT:    vand.vx v8, v8, a0
2561; RV32I-NEXT:    vadd.vv v8, v12, v8
2562; RV32I-NEXT:    vsrl.vi v12, v8, 4
2563; RV32I-NEXT:    vadd.vv v8, v8, v12
2564; RV32I-NEXT:    lui a0, 1
2565; RV32I-NEXT:    addi a0, a0, -241
2566; RV32I-NEXT:    vand.vx v8, v8, a0
2567; RV32I-NEXT:    li a0, 257
2568; RV32I-NEXT:    vmul.vx v8, v8, a0
2569; RV32I-NEXT:    vsrl.vi v8, v8, 8
2570; RV32I-NEXT:    ret
2571;
2572; RV64I-LABEL: cttz_zero_undef_nxv16i16:
2573; RV64I:       # %bb.0:
2574; RV64I-NEXT:    li a0, 1
2575; RV64I-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
2576; RV64I-NEXT:    vsub.vx v12, v8, a0
2577; RV64I-NEXT:    vnot.v v8, v8
2578; RV64I-NEXT:    vand.vv v8, v8, v12
2579; RV64I-NEXT:    vsrl.vi v12, v8, 1
2580; RV64I-NEXT:    lui a0, 5
2581; RV64I-NEXT:    addiw a0, a0, 1365
2582; RV64I-NEXT:    vand.vx v12, v12, a0
2583; RV64I-NEXT:    vsub.vv v8, v8, v12
2584; RV64I-NEXT:    lui a0, 3
2585; RV64I-NEXT:    addiw a0, a0, 819
2586; RV64I-NEXT:    vand.vx v12, v8, a0
2587; RV64I-NEXT:    vsrl.vi v8, v8, 2
2588; RV64I-NEXT:    vand.vx v8, v8, a0
2589; RV64I-NEXT:    vadd.vv v8, v12, v8
2590; RV64I-NEXT:    vsrl.vi v12, v8, 4
2591; RV64I-NEXT:    vadd.vv v8, v8, v12
2592; RV64I-NEXT:    lui a0, 1
2593; RV64I-NEXT:    addiw a0, a0, -241
2594; RV64I-NEXT:    vand.vx v8, v8, a0
2595; RV64I-NEXT:    li a0, 257
2596; RV64I-NEXT:    vmul.vx v8, v8, a0
2597; RV64I-NEXT:    vsrl.vi v8, v8, 8
2598; RV64I-NEXT:    ret
2599;
2600; RV32D-LABEL: cttz_zero_undef_nxv16i16:
2601; RV32D:       # %bb.0:
2602; RV32D-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
2603; RV32D-NEXT:    vrsub.vi v12, v8, 0
2604; RV32D-NEXT:    vand.vv v8, v8, v12
2605; RV32D-NEXT:    vfwcvt.f.xu.v v16, v8
2606; RV32D-NEXT:    vnsrl.wi v8, v16, 23
2607; RV32D-NEXT:    li a0, 127
2608; RV32D-NEXT:    vsub.vx v8, v8, a0
2609; RV32D-NEXT:    ret
2610;
2611; RV64D-LABEL: cttz_zero_undef_nxv16i16:
2612; RV64D:       # %bb.0:
2613; RV64D-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
2614; RV64D-NEXT:    vrsub.vi v12, v8, 0
2615; RV64D-NEXT:    vand.vv v8, v8, v12
2616; RV64D-NEXT:    vfwcvt.f.xu.v v16, v8
2617; RV64D-NEXT:    vnsrl.wi v8, v16, 23
2618; RV64D-NEXT:    li a0, 127
2619; RV64D-NEXT:    vsub.vx v8, v8, a0
2620; RV64D-NEXT:    ret
2621  %a = call <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 true)
2622  ret <vscale x 16 x i16> %a
2623}
2624
2625define <vscale x 32 x i16> @cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va) {
2626; RV32-LABEL: cttz_zero_undef_nxv32i16:
2627; RV32:       # %bb.0:
2628; RV32-NEXT:    li a0, 1
2629; RV32-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
2630; RV32-NEXT:    vsub.vx v16, v8, a0
2631; RV32-NEXT:    vnot.v v8, v8
2632; RV32-NEXT:    vand.vv v8, v8, v16
2633; RV32-NEXT:    vsrl.vi v16, v8, 1
2634; RV32-NEXT:    lui a0, 5
2635; RV32-NEXT:    addi a0, a0, 1365
2636; RV32-NEXT:    vand.vx v16, v16, a0
2637; RV32-NEXT:    vsub.vv v8, v8, v16
2638; RV32-NEXT:    lui a0, 3
2639; RV32-NEXT:    addi a0, a0, 819
2640; RV32-NEXT:    vand.vx v16, v8, a0
2641; RV32-NEXT:    vsrl.vi v8, v8, 2
2642; RV32-NEXT:    vand.vx v8, v8, a0
2643; RV32-NEXT:    vadd.vv v8, v16, v8
2644; RV32-NEXT:    vsrl.vi v16, v8, 4
2645; RV32-NEXT:    vadd.vv v8, v8, v16
2646; RV32-NEXT:    lui a0, 1
2647; RV32-NEXT:    addi a0, a0, -241
2648; RV32-NEXT:    vand.vx v8, v8, a0
2649; RV32-NEXT:    li a0, 257
2650; RV32-NEXT:    vmul.vx v8, v8, a0
2651; RV32-NEXT:    vsrl.vi v8, v8, 8
2652; RV32-NEXT:    ret
2653;
2654; RV64-LABEL: cttz_zero_undef_nxv32i16:
2655; RV64:       # %bb.0:
2656; RV64-NEXT:    li a0, 1
2657; RV64-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
2658; RV64-NEXT:    vsub.vx v16, v8, a0
2659; RV64-NEXT:    vnot.v v8, v8
2660; RV64-NEXT:    vand.vv v8, v8, v16
2661; RV64-NEXT:    vsrl.vi v16, v8, 1
2662; RV64-NEXT:    lui a0, 5
2663; RV64-NEXT:    addiw a0, a0, 1365
2664; RV64-NEXT:    vand.vx v16, v16, a0
2665; RV64-NEXT:    vsub.vv v8, v8, v16
2666; RV64-NEXT:    lui a0, 3
2667; RV64-NEXT:    addiw a0, a0, 819
2668; RV64-NEXT:    vand.vx v16, v8, a0
2669; RV64-NEXT:    vsrl.vi v8, v8, 2
2670; RV64-NEXT:    vand.vx v8, v8, a0
2671; RV64-NEXT:    vadd.vv v8, v16, v8
2672; RV64-NEXT:    vsrl.vi v16, v8, 4
2673; RV64-NEXT:    vadd.vv v8, v8, v16
2674; RV64-NEXT:    lui a0, 1
2675; RV64-NEXT:    addiw a0, a0, -241
2676; RV64-NEXT:    vand.vx v8, v8, a0
2677; RV64-NEXT:    li a0, 257
2678; RV64-NEXT:    vmul.vx v8, v8, a0
2679; RV64-NEXT:    vsrl.vi v8, v8, 8
2680; RV64-NEXT:    ret
2681  %a = call <vscale x 32 x i16> @llvm.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 true)
2682  ret <vscale x 32 x i16> %a
2683}
2684
2685define <vscale x 1 x i32> @cttz_zero_undef_nxv1i32(<vscale x 1 x i32> %va) {
2686; RV32I-LABEL: cttz_zero_undef_nxv1i32:
2687; RV32I:       # %bb.0:
2688; RV32I-NEXT:    li a0, 1
2689; RV32I-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
2690; RV32I-NEXT:    vsub.vx v9, v8, a0
2691; RV32I-NEXT:    vnot.v v8, v8
2692; RV32I-NEXT:    vand.vv v8, v8, v9
2693; RV32I-NEXT:    vsrl.vi v9, v8, 1
2694; RV32I-NEXT:    lui a0, 349525
2695; RV32I-NEXT:    addi a0, a0, 1365
2696; RV32I-NEXT:    vand.vx v9, v9, a0
2697; RV32I-NEXT:    vsub.vv v8, v8, v9
2698; RV32I-NEXT:    lui a0, 209715
2699; RV32I-NEXT:    addi a0, a0, 819
2700; RV32I-NEXT:    vand.vx v9, v8, a0
2701; RV32I-NEXT:    vsrl.vi v8, v8, 2
2702; RV32I-NEXT:    vand.vx v8, v8, a0
2703; RV32I-NEXT:    vadd.vv v8, v9, v8
2704; RV32I-NEXT:    vsrl.vi v9, v8, 4
2705; RV32I-NEXT:    vadd.vv v8, v8, v9
2706; RV32I-NEXT:    lui a0, 61681
2707; RV32I-NEXT:    addi a0, a0, -241
2708; RV32I-NEXT:    vand.vx v8, v8, a0
2709; RV32I-NEXT:    lui a0, 4112
2710; RV32I-NEXT:    addi a0, a0, 257
2711; RV32I-NEXT:    vmul.vx v8, v8, a0
2712; RV32I-NEXT:    vsrl.vi v8, v8, 24
2713; RV32I-NEXT:    ret
2714;
2715; RV64I-LABEL: cttz_zero_undef_nxv1i32:
2716; RV64I:       # %bb.0:
2717; RV64I-NEXT:    li a0, 1
2718; RV64I-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
2719; RV64I-NEXT:    vsub.vx v9, v8, a0
2720; RV64I-NEXT:    vnot.v v8, v8
2721; RV64I-NEXT:    vand.vv v8, v8, v9
2722; RV64I-NEXT:    vsrl.vi v9, v8, 1
2723; RV64I-NEXT:    lui a0, 349525
2724; RV64I-NEXT:    addiw a0, a0, 1365
2725; RV64I-NEXT:    vand.vx v9, v9, a0
2726; RV64I-NEXT:    vsub.vv v8, v8, v9
2727; RV64I-NEXT:    lui a0, 209715
2728; RV64I-NEXT:    addiw a0, a0, 819
2729; RV64I-NEXT:    vand.vx v9, v8, a0
2730; RV64I-NEXT:    vsrl.vi v8, v8, 2
2731; RV64I-NEXT:    vand.vx v8, v8, a0
2732; RV64I-NEXT:    vadd.vv v8, v9, v8
2733; RV64I-NEXT:    vsrl.vi v9, v8, 4
2734; RV64I-NEXT:    vadd.vv v8, v8, v9
2735; RV64I-NEXT:    lui a0, 61681
2736; RV64I-NEXT:    addiw a0, a0, -241
2737; RV64I-NEXT:    vand.vx v8, v8, a0
2738; RV64I-NEXT:    lui a0, 4112
2739; RV64I-NEXT:    addiw a0, a0, 257
2740; RV64I-NEXT:    vmul.vx v8, v8, a0
2741; RV64I-NEXT:    vsrl.vi v8, v8, 24
2742; RV64I-NEXT:    ret
2743;
2744; RV32D-LABEL: cttz_zero_undef_nxv1i32:
2745; RV32D:       # %bb.0:
2746; RV32D-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
2747; RV32D-NEXT:    vrsub.vi v9, v8, 0
2748; RV32D-NEXT:    vand.vv v8, v8, v9
2749; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
2750; RV32D-NEXT:    li a0, 52
2751; RV32D-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
2752; RV32D-NEXT:    vsrl.vx v8, v9, a0
2753; RV32D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
2754; RV32D-NEXT:    vncvt.x.x.w v8, v8
2755; RV32D-NEXT:    li a0, 1023
2756; RV32D-NEXT:    vsub.vx v8, v8, a0
2757; RV32D-NEXT:    ret
2758;
2759; RV64D-LABEL: cttz_zero_undef_nxv1i32:
2760; RV64D:       # %bb.0:
2761; RV64D-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
2762; RV64D-NEXT:    vrsub.vi v9, v8, 0
2763; RV64D-NEXT:    vand.vv v8, v8, v9
2764; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
2765; RV64D-NEXT:    li a0, 52
2766; RV64D-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
2767; RV64D-NEXT:    vsrl.vx v8, v9, a0
2768; RV64D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
2769; RV64D-NEXT:    vncvt.x.x.w v8, v8
2770; RV64D-NEXT:    li a0, 1023
2771; RV64D-NEXT:    vsub.vx v8, v8, a0
2772; RV64D-NEXT:    ret
2773  %a = call <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 true)
2774  ret <vscale x 1 x i32> %a
2775}
2776
2777define <vscale x 2 x i32> @cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) {
2778; RV32I-LABEL: cttz_zero_undef_nxv2i32:
2779; RV32I:       # %bb.0:
2780; RV32I-NEXT:    li a0, 1
2781; RV32I-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
2782; RV32I-NEXT:    vsub.vx v9, v8, a0
2783; RV32I-NEXT:    vnot.v v8, v8
2784; RV32I-NEXT:    vand.vv v8, v8, v9
2785; RV32I-NEXT:    vsrl.vi v9, v8, 1
2786; RV32I-NEXT:    lui a0, 349525
2787; RV32I-NEXT:    addi a0, a0, 1365
2788; RV32I-NEXT:    vand.vx v9, v9, a0
2789; RV32I-NEXT:    vsub.vv v8, v8, v9
2790; RV32I-NEXT:    lui a0, 209715
2791; RV32I-NEXT:    addi a0, a0, 819
2792; RV32I-NEXT:    vand.vx v9, v8, a0
2793; RV32I-NEXT:    vsrl.vi v8, v8, 2
2794; RV32I-NEXT:    vand.vx v8, v8, a0
2795; RV32I-NEXT:    vadd.vv v8, v9, v8
2796; RV32I-NEXT:    vsrl.vi v9, v8, 4
2797; RV32I-NEXT:    vadd.vv v8, v8, v9
2798; RV32I-NEXT:    lui a0, 61681
2799; RV32I-NEXT:    addi a0, a0, -241
2800; RV32I-NEXT:    vand.vx v8, v8, a0
2801; RV32I-NEXT:    lui a0, 4112
2802; RV32I-NEXT:    addi a0, a0, 257
2803; RV32I-NEXT:    vmul.vx v8, v8, a0
2804; RV32I-NEXT:    vsrl.vi v8, v8, 24
2805; RV32I-NEXT:    ret
2806;
2807; RV64I-LABEL: cttz_zero_undef_nxv2i32:
2808; RV64I:       # %bb.0:
2809; RV64I-NEXT:    li a0, 1
2810; RV64I-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
2811; RV64I-NEXT:    vsub.vx v9, v8, a0
2812; RV64I-NEXT:    vnot.v v8, v8
2813; RV64I-NEXT:    vand.vv v8, v8, v9
2814; RV64I-NEXT:    vsrl.vi v9, v8, 1
2815; RV64I-NEXT:    lui a0, 349525
2816; RV64I-NEXT:    addiw a0, a0, 1365
2817; RV64I-NEXT:    vand.vx v9, v9, a0
2818; RV64I-NEXT:    vsub.vv v8, v8, v9
2819; RV64I-NEXT:    lui a0, 209715
2820; RV64I-NEXT:    addiw a0, a0, 819
2821; RV64I-NEXT:    vand.vx v9, v8, a0
2822; RV64I-NEXT:    vsrl.vi v8, v8, 2
2823; RV64I-NEXT:    vand.vx v8, v8, a0
2824; RV64I-NEXT:    vadd.vv v8, v9, v8
2825; RV64I-NEXT:    vsrl.vi v9, v8, 4
2826; RV64I-NEXT:    vadd.vv v8, v8, v9
2827; RV64I-NEXT:    lui a0, 61681
2828; RV64I-NEXT:    addiw a0, a0, -241
2829; RV64I-NEXT:    vand.vx v8, v8, a0
2830; RV64I-NEXT:    lui a0, 4112
2831; RV64I-NEXT:    addiw a0, a0, 257
2832; RV64I-NEXT:    vmul.vx v8, v8, a0
2833; RV64I-NEXT:    vsrl.vi v8, v8, 24
2834; RV64I-NEXT:    ret
2835;
2836; RV32D-LABEL: cttz_zero_undef_nxv2i32:
2837; RV32D:       # %bb.0:
2838; RV32D-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
2839; RV32D-NEXT:    vrsub.vi v9, v8, 0
2840; RV32D-NEXT:    vand.vv v8, v8, v9
2841; RV32D-NEXT:    vfwcvt.f.xu.v v10, v8
2842; RV32D-NEXT:    li a0, 52
2843; RV32D-NEXT:    vsetvli zero, zero, e64, m2, ta, mu
2844; RV32D-NEXT:    vsrl.vx v8, v10, a0
2845; RV32D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
2846; RV32D-NEXT:    vncvt.x.x.w v10, v8
2847; RV32D-NEXT:    li a0, 1023
2848; RV32D-NEXT:    vsub.vx v8, v10, a0
2849; RV32D-NEXT:    ret
2850;
2851; RV64D-LABEL: cttz_zero_undef_nxv2i32:
2852; RV64D:       # %bb.0:
2853; RV64D-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
2854; RV64D-NEXT:    vrsub.vi v9, v8, 0
2855; RV64D-NEXT:    vand.vv v8, v8, v9
2856; RV64D-NEXT:    vfwcvt.f.xu.v v10, v8
2857; RV64D-NEXT:    li a0, 52
2858; RV64D-NEXT:    vsetvli zero, zero, e64, m2, ta, mu
2859; RV64D-NEXT:    vsrl.vx v8, v10, a0
2860; RV64D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
2861; RV64D-NEXT:    vncvt.x.x.w v10, v8
2862; RV64D-NEXT:    li a0, 1023
2863; RV64D-NEXT:    vsub.vx v8, v10, a0
2864; RV64D-NEXT:    ret
2865  %a = call <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 true)
2866  ret <vscale x 2 x i32> %a
2867}
2868
2869define <vscale x 4 x i32> @cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
2870; RV32I-LABEL: cttz_zero_undef_nxv4i32:
2871; RV32I:       # %bb.0:
2872; RV32I-NEXT:    li a0, 1
2873; RV32I-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
2874; RV32I-NEXT:    vsub.vx v10, v8, a0
2875; RV32I-NEXT:    vnot.v v8, v8
2876; RV32I-NEXT:    vand.vv v8, v8, v10
2877; RV32I-NEXT:    vsrl.vi v10, v8, 1
2878; RV32I-NEXT:    lui a0, 349525
2879; RV32I-NEXT:    addi a0, a0, 1365
2880; RV32I-NEXT:    vand.vx v10, v10, a0
2881; RV32I-NEXT:    vsub.vv v8, v8, v10
2882; RV32I-NEXT:    lui a0, 209715
2883; RV32I-NEXT:    addi a0, a0, 819
2884; RV32I-NEXT:    vand.vx v10, v8, a0
2885; RV32I-NEXT:    vsrl.vi v8, v8, 2
2886; RV32I-NEXT:    vand.vx v8, v8, a0
2887; RV32I-NEXT:    vadd.vv v8, v10, v8
2888; RV32I-NEXT:    vsrl.vi v10, v8, 4
2889; RV32I-NEXT:    vadd.vv v8, v8, v10
2890; RV32I-NEXT:    lui a0, 61681
2891; RV32I-NEXT:    addi a0, a0, -241
2892; RV32I-NEXT:    vand.vx v8, v8, a0
2893; RV32I-NEXT:    lui a0, 4112
2894; RV32I-NEXT:    addi a0, a0, 257
2895; RV32I-NEXT:    vmul.vx v8, v8, a0
2896; RV32I-NEXT:    vsrl.vi v8, v8, 24
2897; RV32I-NEXT:    ret
2898;
2899; RV64I-LABEL: cttz_zero_undef_nxv4i32:
2900; RV64I:       # %bb.0:
2901; RV64I-NEXT:    li a0, 1
2902; RV64I-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
2903; RV64I-NEXT:    vsub.vx v10, v8, a0
2904; RV64I-NEXT:    vnot.v v8, v8
2905; RV64I-NEXT:    vand.vv v8, v8, v10
2906; RV64I-NEXT:    vsrl.vi v10, v8, 1
2907; RV64I-NEXT:    lui a0, 349525
2908; RV64I-NEXT:    addiw a0, a0, 1365
2909; RV64I-NEXT:    vand.vx v10, v10, a0
2910; RV64I-NEXT:    vsub.vv v8, v8, v10
2911; RV64I-NEXT:    lui a0, 209715
2912; RV64I-NEXT:    addiw a0, a0, 819
2913; RV64I-NEXT:    vand.vx v10, v8, a0
2914; RV64I-NEXT:    vsrl.vi v8, v8, 2
2915; RV64I-NEXT:    vand.vx v8, v8, a0
2916; RV64I-NEXT:    vadd.vv v8, v10, v8
2917; RV64I-NEXT:    vsrl.vi v10, v8, 4
2918; RV64I-NEXT:    vadd.vv v8, v8, v10
2919; RV64I-NEXT:    lui a0, 61681
2920; RV64I-NEXT:    addiw a0, a0, -241
2921; RV64I-NEXT:    vand.vx v8, v8, a0
2922; RV64I-NEXT:    lui a0, 4112
2923; RV64I-NEXT:    addiw a0, a0, 257
2924; RV64I-NEXT:    vmul.vx v8, v8, a0
2925; RV64I-NEXT:    vsrl.vi v8, v8, 24
2926; RV64I-NEXT:    ret
2927;
2928; RV32D-LABEL: cttz_zero_undef_nxv4i32:
2929; RV32D:       # %bb.0:
2930; RV32D-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
2931; RV32D-NEXT:    vrsub.vi v10, v8, 0
2932; RV32D-NEXT:    vand.vv v8, v8, v10
2933; RV32D-NEXT:    vfwcvt.f.xu.v v12, v8
2934; RV32D-NEXT:    li a0, 52
2935; RV32D-NEXT:    vsetvli zero, zero, e64, m4, ta, mu
2936; RV32D-NEXT:    vsrl.vx v8, v12, a0
2937; RV32D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
2938; RV32D-NEXT:    vncvt.x.x.w v12, v8
2939; RV32D-NEXT:    li a0, 1023
2940; RV32D-NEXT:    vsub.vx v8, v12, a0
2941; RV32D-NEXT:    ret
2942;
2943; RV64D-LABEL: cttz_zero_undef_nxv4i32:
2944; RV64D:       # %bb.0:
2945; RV64D-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
2946; RV64D-NEXT:    vrsub.vi v10, v8, 0
2947; RV64D-NEXT:    vand.vv v8, v8, v10
2948; RV64D-NEXT:    vfwcvt.f.xu.v v12, v8
2949; RV64D-NEXT:    li a0, 52
2950; RV64D-NEXT:    vsetvli zero, zero, e64, m4, ta, mu
2951; RV64D-NEXT:    vsrl.vx v8, v12, a0
2952; RV64D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
2953; RV64D-NEXT:    vncvt.x.x.w v12, v8
2954; RV64D-NEXT:    li a0, 1023
2955; RV64D-NEXT:    vsub.vx v8, v12, a0
2956; RV64D-NEXT:    ret
2957  %a = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 true)
2958  ret <vscale x 4 x i32> %a
2959}
2960
2961define <vscale x 8 x i32> @cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
2962; RV32I-LABEL: cttz_zero_undef_nxv8i32:
2963; RV32I:       # %bb.0:
2964; RV32I-NEXT:    li a0, 1
2965; RV32I-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
2966; RV32I-NEXT:    vsub.vx v12, v8, a0
2967; RV32I-NEXT:    vnot.v v8, v8
2968; RV32I-NEXT:    vand.vv v8, v8, v12
2969; RV32I-NEXT:    vsrl.vi v12, v8, 1
2970; RV32I-NEXT:    lui a0, 349525
2971; RV32I-NEXT:    addi a0, a0, 1365
2972; RV32I-NEXT:    vand.vx v12, v12, a0
2973; RV32I-NEXT:    vsub.vv v8, v8, v12
2974; RV32I-NEXT:    lui a0, 209715
2975; RV32I-NEXT:    addi a0, a0, 819
2976; RV32I-NEXT:    vand.vx v12, v8, a0
2977; RV32I-NEXT:    vsrl.vi v8, v8, 2
2978; RV32I-NEXT:    vand.vx v8, v8, a0
2979; RV32I-NEXT:    vadd.vv v8, v12, v8
2980; RV32I-NEXT:    vsrl.vi v12, v8, 4
2981; RV32I-NEXT:    vadd.vv v8, v8, v12
2982; RV32I-NEXT:    lui a0, 61681
2983; RV32I-NEXT:    addi a0, a0, -241
2984; RV32I-NEXT:    vand.vx v8, v8, a0
2985; RV32I-NEXT:    lui a0, 4112
2986; RV32I-NEXT:    addi a0, a0, 257
2987; RV32I-NEXT:    vmul.vx v8, v8, a0
2988; RV32I-NEXT:    vsrl.vi v8, v8, 24
2989; RV32I-NEXT:    ret
2990;
2991; RV64I-LABEL: cttz_zero_undef_nxv8i32:
2992; RV64I:       # %bb.0:
2993; RV64I-NEXT:    li a0, 1
2994; RV64I-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
2995; RV64I-NEXT:    vsub.vx v12, v8, a0
2996; RV64I-NEXT:    vnot.v v8, v8
2997; RV64I-NEXT:    vand.vv v8, v8, v12
2998; RV64I-NEXT:    vsrl.vi v12, v8, 1
2999; RV64I-NEXT:    lui a0, 349525
3000; RV64I-NEXT:    addiw a0, a0, 1365
3001; RV64I-NEXT:    vand.vx v12, v12, a0
3002; RV64I-NEXT:    vsub.vv v8, v8, v12
3003; RV64I-NEXT:    lui a0, 209715
3004; RV64I-NEXT:    addiw a0, a0, 819
3005; RV64I-NEXT:    vand.vx v12, v8, a0
3006; RV64I-NEXT:    vsrl.vi v8, v8, 2
3007; RV64I-NEXT:    vand.vx v8, v8, a0
3008; RV64I-NEXT:    vadd.vv v8, v12, v8
3009; RV64I-NEXT:    vsrl.vi v12, v8, 4
3010; RV64I-NEXT:    vadd.vv v8, v8, v12
3011; RV64I-NEXT:    lui a0, 61681
3012; RV64I-NEXT:    addiw a0, a0, -241
3013; RV64I-NEXT:    vand.vx v8, v8, a0
3014; RV64I-NEXT:    lui a0, 4112
3015; RV64I-NEXT:    addiw a0, a0, 257
3016; RV64I-NEXT:    vmul.vx v8, v8, a0
3017; RV64I-NEXT:    vsrl.vi v8, v8, 24
3018; RV64I-NEXT:    ret
3019;
3020; RV32D-LABEL: cttz_zero_undef_nxv8i32:
3021; RV32D:       # %bb.0:
3022; RV32D-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
3023; RV32D-NEXT:    vrsub.vi v12, v8, 0
3024; RV32D-NEXT:    vand.vv v8, v8, v12
3025; RV32D-NEXT:    vfwcvt.f.xu.v v16, v8
3026; RV32D-NEXT:    li a0, 52
3027; RV32D-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
3028; RV32D-NEXT:    vsrl.vx v8, v16, a0
3029; RV32D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
3030; RV32D-NEXT:    vncvt.x.x.w v16, v8
3031; RV32D-NEXT:    li a0, 1023
3032; RV32D-NEXT:    vsub.vx v8, v16, a0
3033; RV32D-NEXT:    ret
3034;
3035; RV64D-LABEL: cttz_zero_undef_nxv8i32:
3036; RV64D:       # %bb.0:
3037; RV64D-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
3038; RV64D-NEXT:    vrsub.vi v12, v8, 0
3039; RV64D-NEXT:    vand.vv v8, v8, v12
3040; RV64D-NEXT:    vfwcvt.f.xu.v v16, v8
3041; RV64D-NEXT:    li a0, 52
3042; RV64D-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
3043; RV64D-NEXT:    vsrl.vx v8, v16, a0
3044; RV64D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
3045; RV64D-NEXT:    vncvt.x.x.w v16, v8
3046; RV64D-NEXT:    li a0, 1023
3047; RV64D-NEXT:    vsub.vx v8, v16, a0
3048; RV64D-NEXT:    ret
3049  %a = call <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 true)
3050  ret <vscale x 8 x i32> %a
3051}
3052
3053define <vscale x 16 x i32> @cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) {
3054; RV32-LABEL: cttz_zero_undef_nxv16i32:
3055; RV32:       # %bb.0:
3056; RV32-NEXT:    li a0, 1
3057; RV32-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
3058; RV32-NEXT:    vsub.vx v16, v8, a0
3059; RV32-NEXT:    vnot.v v8, v8
3060; RV32-NEXT:    vand.vv v8, v8, v16
3061; RV32-NEXT:    vsrl.vi v16, v8, 1
3062; RV32-NEXT:    lui a0, 349525
3063; RV32-NEXT:    addi a0, a0, 1365
3064; RV32-NEXT:    vand.vx v16, v16, a0
3065; RV32-NEXT:    vsub.vv v8, v8, v16
3066; RV32-NEXT:    lui a0, 209715
3067; RV32-NEXT:    addi a0, a0, 819
3068; RV32-NEXT:    vand.vx v16, v8, a0
3069; RV32-NEXT:    vsrl.vi v8, v8, 2
3070; RV32-NEXT:    vand.vx v8, v8, a0
3071; RV32-NEXT:    vadd.vv v8, v16, v8
3072; RV32-NEXT:    vsrl.vi v16, v8, 4
3073; RV32-NEXT:    vadd.vv v8, v8, v16
3074; RV32-NEXT:    lui a0, 61681
3075; RV32-NEXT:    addi a0, a0, -241
3076; RV32-NEXT:    vand.vx v8, v8, a0
3077; RV32-NEXT:    lui a0, 4112
3078; RV32-NEXT:    addi a0, a0, 257
3079; RV32-NEXT:    vmul.vx v8, v8, a0
3080; RV32-NEXT:    vsrl.vi v8, v8, 24
3081; RV32-NEXT:    ret
3082;
3083; RV64-LABEL: cttz_zero_undef_nxv16i32:
3084; RV64:       # %bb.0:
3085; RV64-NEXT:    li a0, 1
3086; RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
3087; RV64-NEXT:    vsub.vx v16, v8, a0
3088; RV64-NEXT:    vnot.v v8, v8
3089; RV64-NEXT:    vand.vv v8, v8, v16
3090; RV64-NEXT:    vsrl.vi v16, v8, 1
3091; RV64-NEXT:    lui a0, 349525
3092; RV64-NEXT:    addiw a0, a0, 1365
3093; RV64-NEXT:    vand.vx v16, v16, a0
3094; RV64-NEXT:    vsub.vv v8, v8, v16
3095; RV64-NEXT:    lui a0, 209715
3096; RV64-NEXT:    addiw a0, a0, 819
3097; RV64-NEXT:    vand.vx v16, v8, a0
3098; RV64-NEXT:    vsrl.vi v8, v8, 2
3099; RV64-NEXT:    vand.vx v8, v8, a0
3100; RV64-NEXT:    vadd.vv v8, v16, v8
3101; RV64-NEXT:    vsrl.vi v16, v8, 4
3102; RV64-NEXT:    vadd.vv v8, v8, v16
3103; RV64-NEXT:    lui a0, 61681
3104; RV64-NEXT:    addiw a0, a0, -241
3105; RV64-NEXT:    vand.vx v8, v8, a0
3106; RV64-NEXT:    lui a0, 4112
3107; RV64-NEXT:    addiw a0, a0, 257
3108; RV64-NEXT:    vmul.vx v8, v8, a0
3109; RV64-NEXT:    vsrl.vi v8, v8, 24
3110; RV64-NEXT:    ret
3111  %a = call <vscale x 16 x i32> @llvm.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 true)
3112  ret <vscale x 16 x i32> %a
3113}
3114
3115define <vscale x 1 x i64> @cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
3116; RV32-LABEL: cttz_zero_undef_nxv1i64:
3117; RV32:       # %bb.0:
3118; RV32-NEXT:    addi sp, sp, -16
3119; RV32-NEXT:    .cfi_def_cfa_offset 16
3120; RV32-NEXT:    lui a0, 349525
3121; RV32-NEXT:    addi a0, a0, 1365
3122; RV32-NEXT:    sw a0, 12(sp)
3123; RV32-NEXT:    sw a0, 8(sp)
3124; RV32-NEXT:    lui a0, 209715
3125; RV32-NEXT:    addi a0, a0, 819
3126; RV32-NEXT:    sw a0, 12(sp)
3127; RV32-NEXT:    sw a0, 8(sp)
3128; RV32-NEXT:    lui a0, 61681
3129; RV32-NEXT:    addi a0, a0, -241
3130; RV32-NEXT:    sw a0, 12(sp)
3131; RV32-NEXT:    sw a0, 8(sp)
3132; RV32-NEXT:    lui a0, 4112
3133; RV32-NEXT:    addi a0, a0, 257
3134; RV32-NEXT:    sw a0, 12(sp)
3135; RV32-NEXT:    sw a0, 8(sp)
3136; RV32-NEXT:    li a0, 1
3137; RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
3138; RV32-NEXT:    vsub.vx v9, v8, a0
3139; RV32-NEXT:    vnot.v v8, v8
3140; RV32-NEXT:    addi a0, sp, 8
3141; RV32-NEXT:    vlse64.v v10, (a0), zero
3142; RV32-NEXT:    vand.vv v8, v8, v9
3143; RV32-NEXT:    addi a0, sp, 8
3144; RV32-NEXT:    vlse64.v v9, (a0), zero
3145; RV32-NEXT:    vsrl.vi v11, v8, 1
3146; RV32-NEXT:    vand.vv v10, v11, v10
3147; RV32-NEXT:    vsub.vv v8, v8, v10
3148; RV32-NEXT:    vand.vv v10, v8, v9
3149; RV32-NEXT:    vsrl.vi v8, v8, 2
3150; RV32-NEXT:    vand.vv v8, v8, v9
3151; RV32-NEXT:    vadd.vv v8, v10, v8
3152; RV32-NEXT:    addi a0, sp, 8
3153; RV32-NEXT:    vlse64.v v9, (a0), zero
3154; RV32-NEXT:    addi a0, sp, 8
3155; RV32-NEXT:    vlse64.v v10, (a0), zero
3156; RV32-NEXT:    vsrl.vi v11, v8, 4
3157; RV32-NEXT:    vadd.vv v8, v8, v11
3158; RV32-NEXT:    vand.vv v8, v8, v9
3159; RV32-NEXT:    vmul.vv v8, v8, v10
3160; RV32-NEXT:    li a0, 56
3161; RV32-NEXT:    vsrl.vx v8, v8, a0
3162; RV32-NEXT:    addi sp, sp, 16
3163; RV32-NEXT:    ret
3164;
3165; RV64-LABEL: cttz_zero_undef_nxv1i64:
3166; RV64:       # %bb.0:
3167; RV64-NEXT:    li a0, 1
3168; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
3169; RV64-NEXT:    vsub.vx v9, v8, a0
3170; RV64-NEXT:    vnot.v v8, v8
3171; RV64-NEXT:    vand.vv v8, v8, v9
3172; RV64-NEXT:    lui a0, %hi(.LCPI40_0)
3173; RV64-NEXT:    ld a0, %lo(.LCPI40_0)(a0)
3174; RV64-NEXT:    lui a1, %hi(.LCPI40_1)
3175; RV64-NEXT:    ld a1, %lo(.LCPI40_1)(a1)
3176; RV64-NEXT:    vsrl.vi v9, v8, 1
3177; RV64-NEXT:    vand.vx v9, v9, a0
3178; RV64-NEXT:    vsub.vv v8, v8, v9
3179; RV64-NEXT:    vand.vx v9, v8, a1
3180; RV64-NEXT:    vsrl.vi v8, v8, 2
3181; RV64-NEXT:    vand.vx v8, v8, a1
3182; RV64-NEXT:    vadd.vv v8, v9, v8
3183; RV64-NEXT:    lui a0, %hi(.LCPI40_2)
3184; RV64-NEXT:    ld a0, %lo(.LCPI40_2)(a0)
3185; RV64-NEXT:    lui a1, %hi(.LCPI40_3)
3186; RV64-NEXT:    ld a1, %lo(.LCPI40_3)(a1)
3187; RV64-NEXT:    vsrl.vi v9, v8, 4
3188; RV64-NEXT:    vadd.vv v8, v8, v9
3189; RV64-NEXT:    vand.vx v8, v8, a0
3190; RV64-NEXT:    vmul.vx v8, v8, a1
3191; RV64-NEXT:    li a0, 56
3192; RV64-NEXT:    vsrl.vx v8, v8, a0
3193; RV64-NEXT:    ret
3194  %a = call <vscale x 1 x i64> @llvm.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 true)
3195  ret <vscale x 1 x i64> %a
3196}
3197
3198define <vscale x 2 x i64> @cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
3199; RV32-LABEL: cttz_zero_undef_nxv2i64:
3200; RV32:       # %bb.0:
3201; RV32-NEXT:    addi sp, sp, -16
3202; RV32-NEXT:    .cfi_def_cfa_offset 16
3203; RV32-NEXT:    lui a0, 349525
3204; RV32-NEXT:    addi a0, a0, 1365
3205; RV32-NEXT:    sw a0, 12(sp)
3206; RV32-NEXT:    sw a0, 8(sp)
3207; RV32-NEXT:    lui a0, 209715
3208; RV32-NEXT:    addi a0, a0, 819
3209; RV32-NEXT:    sw a0, 12(sp)
3210; RV32-NEXT:    sw a0, 8(sp)
3211; RV32-NEXT:    lui a0, 61681
3212; RV32-NEXT:    addi a0, a0, -241
3213; RV32-NEXT:    sw a0, 12(sp)
3214; RV32-NEXT:    sw a0, 8(sp)
3215; RV32-NEXT:    lui a0, 4112
3216; RV32-NEXT:    addi a0, a0, 257
3217; RV32-NEXT:    sw a0, 12(sp)
3218; RV32-NEXT:    sw a0, 8(sp)
3219; RV32-NEXT:    li a0, 1
3220; RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
3221; RV32-NEXT:    vsub.vx v10, v8, a0
3222; RV32-NEXT:    vnot.v v8, v8
3223; RV32-NEXT:    addi a0, sp, 8
3224; RV32-NEXT:    vlse64.v v12, (a0), zero
3225; RV32-NEXT:    vand.vv v8, v8, v10
3226; RV32-NEXT:    addi a0, sp, 8
3227; RV32-NEXT:    vlse64.v v10, (a0), zero
3228; RV32-NEXT:    vsrl.vi v14, v8, 1
3229; RV32-NEXT:    vand.vv v12, v14, v12
3230; RV32-NEXT:    vsub.vv v8, v8, v12
3231; RV32-NEXT:    vand.vv v12, v8, v10
3232; RV32-NEXT:    vsrl.vi v8, v8, 2
3233; RV32-NEXT:    vand.vv v8, v8, v10
3234; RV32-NEXT:    vadd.vv v8, v12, v8
3235; RV32-NEXT:    addi a0, sp, 8
3236; RV32-NEXT:    vlse64.v v10, (a0), zero
3237; RV32-NEXT:    addi a0, sp, 8
3238; RV32-NEXT:    vlse64.v v12, (a0), zero
3239; RV32-NEXT:    vsrl.vi v14, v8, 4
3240; RV32-NEXT:    vadd.vv v8, v8, v14
3241; RV32-NEXT:    vand.vv v8, v8, v10
3242; RV32-NEXT:    vmul.vv v8, v8, v12
3243; RV32-NEXT:    li a0, 56
3244; RV32-NEXT:    vsrl.vx v8, v8, a0
3245; RV32-NEXT:    addi sp, sp, 16
3246; RV32-NEXT:    ret
3247;
3248; RV64-LABEL: cttz_zero_undef_nxv2i64:
3249; RV64:       # %bb.0:
3250; RV64-NEXT:    li a0, 1
3251; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
3252; RV64-NEXT:    vsub.vx v10, v8, a0
3253; RV64-NEXT:    vnot.v v8, v8
3254; RV64-NEXT:    vand.vv v8, v8, v10
3255; RV64-NEXT:    lui a0, %hi(.LCPI41_0)
3256; RV64-NEXT:    ld a0, %lo(.LCPI41_0)(a0)
3257; RV64-NEXT:    lui a1, %hi(.LCPI41_1)
3258; RV64-NEXT:    ld a1, %lo(.LCPI41_1)(a1)
3259; RV64-NEXT:    vsrl.vi v10, v8, 1
3260; RV64-NEXT:    vand.vx v10, v10, a0
3261; RV64-NEXT:    vsub.vv v8, v8, v10
3262; RV64-NEXT:    vand.vx v10, v8, a1
3263; RV64-NEXT:    vsrl.vi v8, v8, 2
3264; RV64-NEXT:    vand.vx v8, v8, a1
3265; RV64-NEXT:    vadd.vv v8, v10, v8
3266; RV64-NEXT:    lui a0, %hi(.LCPI41_2)
3267; RV64-NEXT:    ld a0, %lo(.LCPI41_2)(a0)
3268; RV64-NEXT:    lui a1, %hi(.LCPI41_3)
3269; RV64-NEXT:    ld a1, %lo(.LCPI41_3)(a1)
3270; RV64-NEXT:    vsrl.vi v10, v8, 4
3271; RV64-NEXT:    vadd.vv v8, v8, v10
3272; RV64-NEXT:    vand.vx v8, v8, a0
3273; RV64-NEXT:    vmul.vx v8, v8, a1
3274; RV64-NEXT:    li a0, 56
3275; RV64-NEXT:    vsrl.vx v8, v8, a0
3276; RV64-NEXT:    ret
3277  %a = call <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 true)
3278  ret <vscale x 2 x i64> %a
3279}
3280
3281define <vscale x 4 x i64> @cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
3282; RV32-LABEL: cttz_zero_undef_nxv4i64:
3283; RV32:       # %bb.0:
3284; RV32-NEXT:    addi sp, sp, -16
3285; RV32-NEXT:    .cfi_def_cfa_offset 16
3286; RV32-NEXT:    lui a0, 349525
3287; RV32-NEXT:    addi a0, a0, 1365
3288; RV32-NEXT:    sw a0, 12(sp)
3289; RV32-NEXT:    sw a0, 8(sp)
3290; RV32-NEXT:    lui a0, 209715
3291; RV32-NEXT:    addi a0, a0, 819
3292; RV32-NEXT:    sw a0, 12(sp)
3293; RV32-NEXT:    sw a0, 8(sp)
3294; RV32-NEXT:    lui a0, 61681
3295; RV32-NEXT:    addi a0, a0, -241
3296; RV32-NEXT:    sw a0, 12(sp)
3297; RV32-NEXT:    sw a0, 8(sp)
3298; RV32-NEXT:    lui a0, 4112
3299; RV32-NEXT:    addi a0, a0, 257
3300; RV32-NEXT:    sw a0, 12(sp)
3301; RV32-NEXT:    sw a0, 8(sp)
3302; RV32-NEXT:    li a0, 1
3303; RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
3304; RV32-NEXT:    vsub.vx v12, v8, a0
3305; RV32-NEXT:    vnot.v v8, v8
3306; RV32-NEXT:    addi a0, sp, 8
3307; RV32-NEXT:    vlse64.v v16, (a0), zero
3308; RV32-NEXT:    vand.vv v8, v8, v12
3309; RV32-NEXT:    addi a0, sp, 8
3310; RV32-NEXT:    vlse64.v v12, (a0), zero
3311; RV32-NEXT:    vsrl.vi v20, v8, 1
3312; RV32-NEXT:    vand.vv v16, v20, v16
3313; RV32-NEXT:    vsub.vv v8, v8, v16
3314; RV32-NEXT:    vand.vv v16, v8, v12
3315; RV32-NEXT:    vsrl.vi v8, v8, 2
3316; RV32-NEXT:    vand.vv v8, v8, v12
3317; RV32-NEXT:    vadd.vv v8, v16, v8
3318; RV32-NEXT:    addi a0, sp, 8
3319; RV32-NEXT:    vlse64.v v12, (a0), zero
3320; RV32-NEXT:    addi a0, sp, 8
3321; RV32-NEXT:    vlse64.v v16, (a0), zero
3322; RV32-NEXT:    vsrl.vi v20, v8, 4
3323; RV32-NEXT:    vadd.vv v8, v8, v20
3324; RV32-NEXT:    vand.vv v8, v8, v12
3325; RV32-NEXT:    vmul.vv v8, v8, v16
3326; RV32-NEXT:    li a0, 56
3327; RV32-NEXT:    vsrl.vx v8, v8, a0
3328; RV32-NEXT:    addi sp, sp, 16
3329; RV32-NEXT:    ret
3330;
3331; RV64-LABEL: cttz_zero_undef_nxv4i64:
3332; RV64:       # %bb.0:
3333; RV64-NEXT:    li a0, 1
3334; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
3335; RV64-NEXT:    vsub.vx v12, v8, a0
3336; RV64-NEXT:    vnot.v v8, v8
3337; RV64-NEXT:    vand.vv v8, v8, v12
3338; RV64-NEXT:    lui a0, %hi(.LCPI42_0)
3339; RV64-NEXT:    ld a0, %lo(.LCPI42_0)(a0)
3340; RV64-NEXT:    lui a1, %hi(.LCPI42_1)
3341; RV64-NEXT:    ld a1, %lo(.LCPI42_1)(a1)
3342; RV64-NEXT:    vsrl.vi v12, v8, 1
3343; RV64-NEXT:    vand.vx v12, v12, a0
3344; RV64-NEXT:    vsub.vv v8, v8, v12
3345; RV64-NEXT:    vand.vx v12, v8, a1
3346; RV64-NEXT:    vsrl.vi v8, v8, 2
3347; RV64-NEXT:    vand.vx v8, v8, a1
3348; RV64-NEXT:    vadd.vv v8, v12, v8
3349; RV64-NEXT:    lui a0, %hi(.LCPI42_2)
3350; RV64-NEXT:    ld a0, %lo(.LCPI42_2)(a0)
3351; RV64-NEXT:    lui a1, %hi(.LCPI42_3)
3352; RV64-NEXT:    ld a1, %lo(.LCPI42_3)(a1)
3353; RV64-NEXT:    vsrl.vi v12, v8, 4
3354; RV64-NEXT:    vadd.vv v8, v8, v12
3355; RV64-NEXT:    vand.vx v8, v8, a0
3356; RV64-NEXT:    vmul.vx v8, v8, a1
3357; RV64-NEXT:    li a0, 56
3358; RV64-NEXT:    vsrl.vx v8, v8, a0
3359; RV64-NEXT:    ret
3360  %a = call <vscale x 4 x i64> @llvm.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 true)
3361  ret <vscale x 4 x i64> %a
3362}
3363
3364define <vscale x 8 x i64> @cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
3365; RV32-LABEL: cttz_zero_undef_nxv8i64:
3366; RV32:       # %bb.0:
3367; RV32-NEXT:    addi sp, sp, -16
3368; RV32-NEXT:    .cfi_def_cfa_offset 16
3369; RV32-NEXT:    lui a0, 349525
3370; RV32-NEXT:    addi a0, a0, 1365
3371; RV32-NEXT:    sw a0, 12(sp)
3372; RV32-NEXT:    sw a0, 8(sp)
3373; RV32-NEXT:    lui a0, 209715
3374; RV32-NEXT:    addi a0, a0, 819
3375; RV32-NEXT:    sw a0, 12(sp)
3376; RV32-NEXT:    sw a0, 8(sp)
3377; RV32-NEXT:    lui a0, 61681
3378; RV32-NEXT:    addi a0, a0, -241
3379; RV32-NEXT:    sw a0, 12(sp)
3380; RV32-NEXT:    sw a0, 8(sp)
3381; RV32-NEXT:    lui a0, 4112
3382; RV32-NEXT:    addi a0, a0, 257
3383; RV32-NEXT:    sw a0, 12(sp)
3384; RV32-NEXT:    sw a0, 8(sp)
3385; RV32-NEXT:    li a0, 1
3386; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
3387; RV32-NEXT:    vsub.vx v16, v8, a0
3388; RV32-NEXT:    vnot.v v8, v8
3389; RV32-NEXT:    addi a0, sp, 8
3390; RV32-NEXT:    vlse64.v v24, (a0), zero
3391; RV32-NEXT:    vand.vv v8, v8, v16
3392; RV32-NEXT:    addi a0, sp, 8
3393; RV32-NEXT:    vlse64.v v16, (a0), zero
3394; RV32-NEXT:    vsrl.vi v0, v8, 1
3395; RV32-NEXT:    vand.vv v24, v0, v24
3396; RV32-NEXT:    vsub.vv v8, v8, v24
3397; RV32-NEXT:    vand.vv v24, v8, v16
3398; RV32-NEXT:    vsrl.vi v8, v8, 2
3399; RV32-NEXT:    vand.vv v8, v8, v16
3400; RV32-NEXT:    vadd.vv v8, v24, v8
3401; RV32-NEXT:    addi a0, sp, 8
3402; RV32-NEXT:    vlse64.v v16, (a0), zero
3403; RV32-NEXT:    addi a0, sp, 8
3404; RV32-NEXT:    vlse64.v v24, (a0), zero
3405; RV32-NEXT:    vsrl.vi v0, v8, 4
3406; RV32-NEXT:    vadd.vv v8, v8, v0
3407; RV32-NEXT:    vand.vv v8, v8, v16
3408; RV32-NEXT:    vmul.vv v8, v8, v24
3409; RV32-NEXT:    li a0, 56
3410; RV32-NEXT:    vsrl.vx v8, v8, a0
3411; RV32-NEXT:    addi sp, sp, 16
3412; RV32-NEXT:    ret
3413;
3414; RV64-LABEL: cttz_zero_undef_nxv8i64:
3415; RV64:       # %bb.0:
3416; RV64-NEXT:    li a0, 1
3417; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
3418; RV64-NEXT:    vsub.vx v16, v8, a0
3419; RV64-NEXT:    vnot.v v8, v8
3420; RV64-NEXT:    vand.vv v8, v8, v16
3421; RV64-NEXT:    lui a0, %hi(.LCPI43_0)
3422; RV64-NEXT:    ld a0, %lo(.LCPI43_0)(a0)
3423; RV64-NEXT:    lui a1, %hi(.LCPI43_1)
3424; RV64-NEXT:    ld a1, %lo(.LCPI43_1)(a1)
3425; RV64-NEXT:    vsrl.vi v16, v8, 1
3426; RV64-NEXT:    vand.vx v16, v16, a0
3427; RV64-NEXT:    vsub.vv v8, v8, v16
3428; RV64-NEXT:    vand.vx v16, v8, a1
3429; RV64-NEXT:    vsrl.vi v8, v8, 2
3430; RV64-NEXT:    vand.vx v8, v8, a1
3431; RV64-NEXT:    vadd.vv v8, v16, v8
3432; RV64-NEXT:    lui a0, %hi(.LCPI43_2)
3433; RV64-NEXT:    ld a0, %lo(.LCPI43_2)(a0)
3434; RV64-NEXT:    lui a1, %hi(.LCPI43_3)
3435; RV64-NEXT:    ld a1, %lo(.LCPI43_3)(a1)
3436; RV64-NEXT:    vsrl.vi v16, v8, 4
3437; RV64-NEXT:    vadd.vv v8, v8, v16
3438; RV64-NEXT:    vand.vx v8, v8, a0
3439; RV64-NEXT:    vmul.vx v8, v8, a1
3440; RV64-NEXT:    li a0, 56
3441; RV64-NEXT:    vsrl.vx v8, v8, a0
3442; RV64-NEXT:    ret
3443  %a = call <vscale x 8 x i64> @llvm.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 true)
3444  ret <vscale x 8 x i64> %a
3445}
3446