1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32I
3; RUN: llc -mtriple=riscv64 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64I
4; RUN: llc -mtriple=riscv32 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32D
5; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64D
6
7define <vscale x 1 x i8> @cttz_nxv1i8(<vscale x 1 x i8> %va) {
8; RV32I-LABEL: cttz_nxv1i8:
9; RV32I:       # %bb.0:
10; RV32I-NEXT:    li a0, 1
11; RV32I-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
12; RV32I-NEXT:    vsub.vx v9, v8, a0
13; RV32I-NEXT:    vxor.vi v8, v8, -1
14; RV32I-NEXT:    vand.vv v8, v8, v9
15; RV32I-NEXT:    vsrl.vi v9, v8, 1
16; RV32I-NEXT:    li a0, 85
17; RV32I-NEXT:    vand.vx v9, v9, a0
18; RV32I-NEXT:    vsub.vv v8, v8, v9
19; RV32I-NEXT:    li a0, 51
20; RV32I-NEXT:    vand.vx v9, v8, a0
21; RV32I-NEXT:    vsrl.vi v8, v8, 2
22; RV32I-NEXT:    vand.vx v8, v8, a0
23; RV32I-NEXT:    vadd.vv v8, v9, v8
24; RV32I-NEXT:    vsrl.vi v9, v8, 4
25; RV32I-NEXT:    vadd.vv v8, v8, v9
26; RV32I-NEXT:    vand.vi v8, v8, 15
27; RV32I-NEXT:    ret
28;
29; RV64I-LABEL: cttz_nxv1i8:
30; RV64I:       # %bb.0:
31; RV64I-NEXT:    li a0, 1
32; RV64I-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
33; RV64I-NEXT:    vsub.vx v9, v8, a0
34; RV64I-NEXT:    vxor.vi v8, v8, -1
35; RV64I-NEXT:    vand.vv v8, v8, v9
36; RV64I-NEXT:    vsrl.vi v9, v8, 1
37; RV64I-NEXT:    li a0, 85
38; RV64I-NEXT:    vand.vx v9, v9, a0
39; RV64I-NEXT:    vsub.vv v8, v8, v9
40; RV64I-NEXT:    li a0, 51
41; RV64I-NEXT:    vand.vx v9, v8, a0
42; RV64I-NEXT:    vsrl.vi v8, v8, 2
43; RV64I-NEXT:    vand.vx v8, v8, a0
44; RV64I-NEXT:    vadd.vv v8, v9, v8
45; RV64I-NEXT:    vsrl.vi v9, v8, 4
46; RV64I-NEXT:    vadd.vv v8, v8, v9
47; RV64I-NEXT:    vand.vi v8, v8, 15
48; RV64I-NEXT:    ret
49;
50; RV32D-LABEL: cttz_nxv1i8:
51; RV32D:       # %bb.0:
52; RV32D-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
53; RV32D-NEXT:    vmv.v.i v9, 0
54; RV32D-NEXT:    vmseq.vv v0, v9, v8
55; RV32D-NEXT:    vrsub.vi v9, v8, 0
56; RV32D-NEXT:    vand.vv v8, v8, v9
57; RV32D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
58; RV32D-NEXT:    vzext.vf4 v9, v8
59; RV32D-NEXT:    vfcvt.f.xu.v v8, v9
60; RV32D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
61; RV32D-NEXT:    vnsrl.wi v8, v8, 23
62; RV32D-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
63; RV32D-NEXT:    vnsrl.wx v8, v8, zero
64; RV32D-NEXT:    li a0, 127
65; RV32D-NEXT:    vsub.vx v8, v8, a0
66; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
67; RV32D-NEXT:    ret
68;
69; RV64D-LABEL: cttz_nxv1i8:
70; RV64D:       # %bb.0:
71; RV64D-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
72; RV64D-NEXT:    vmv.v.i v9, 0
73; RV64D-NEXT:    vmseq.vv v0, v9, v8
74; RV64D-NEXT:    vrsub.vi v9, v8, 0
75; RV64D-NEXT:    vand.vv v8, v8, v9
76; RV64D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
77; RV64D-NEXT:    vzext.vf4 v9, v8
78; RV64D-NEXT:    vfcvt.f.xu.v v8, v9
79; RV64D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
80; RV64D-NEXT:    vnsrl.wi v8, v8, 23
81; RV64D-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
82; RV64D-NEXT:    vnsrl.wx v8, v8, zero
83; RV64D-NEXT:    li a0, 127
84; RV64D-NEXT:    vsub.vx v8, v8, a0
85; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
86; RV64D-NEXT:    ret
87  %a = call <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 false)
88  ret <vscale x 1 x i8> %a
89}
90declare <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8>, i1)
91
92define <vscale x 2 x i8> @cttz_nxv2i8(<vscale x 2 x i8> %va) {
93; RV32I-LABEL: cttz_nxv2i8:
94; RV32I:       # %bb.0:
95; RV32I-NEXT:    li a0, 1
96; RV32I-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
97; RV32I-NEXT:    vsub.vx v9, v8, a0
98; RV32I-NEXT:    vxor.vi v8, v8, -1
99; RV32I-NEXT:    vand.vv v8, v8, v9
100; RV32I-NEXT:    vsrl.vi v9, v8, 1
101; RV32I-NEXT:    li a0, 85
102; RV32I-NEXT:    vand.vx v9, v9, a0
103; RV32I-NEXT:    vsub.vv v8, v8, v9
104; RV32I-NEXT:    li a0, 51
105; RV32I-NEXT:    vand.vx v9, v8, a0
106; RV32I-NEXT:    vsrl.vi v8, v8, 2
107; RV32I-NEXT:    vand.vx v8, v8, a0
108; RV32I-NEXT:    vadd.vv v8, v9, v8
109; RV32I-NEXT:    vsrl.vi v9, v8, 4
110; RV32I-NEXT:    vadd.vv v8, v8, v9
111; RV32I-NEXT:    vand.vi v8, v8, 15
112; RV32I-NEXT:    ret
113;
114; RV64I-LABEL: cttz_nxv2i8:
115; RV64I:       # %bb.0:
116; RV64I-NEXT:    li a0, 1
117; RV64I-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
118; RV64I-NEXT:    vsub.vx v9, v8, a0
119; RV64I-NEXT:    vxor.vi v8, v8, -1
120; RV64I-NEXT:    vand.vv v8, v8, v9
121; RV64I-NEXT:    vsrl.vi v9, v8, 1
122; RV64I-NEXT:    li a0, 85
123; RV64I-NEXT:    vand.vx v9, v9, a0
124; RV64I-NEXT:    vsub.vv v8, v8, v9
125; RV64I-NEXT:    li a0, 51
126; RV64I-NEXT:    vand.vx v9, v8, a0
127; RV64I-NEXT:    vsrl.vi v8, v8, 2
128; RV64I-NEXT:    vand.vx v8, v8, a0
129; RV64I-NEXT:    vadd.vv v8, v9, v8
130; RV64I-NEXT:    vsrl.vi v9, v8, 4
131; RV64I-NEXT:    vadd.vv v8, v8, v9
132; RV64I-NEXT:    vand.vi v8, v8, 15
133; RV64I-NEXT:    ret
134;
135; RV32D-LABEL: cttz_nxv2i8:
136; RV32D:       # %bb.0:
137; RV32D-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
138; RV32D-NEXT:    vmv.v.i v9, 0
139; RV32D-NEXT:    vmseq.vv v0, v9, v8
140; RV32D-NEXT:    vrsub.vi v9, v8, 0
141; RV32D-NEXT:    vand.vv v8, v8, v9
142; RV32D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
143; RV32D-NEXT:    vzext.vf4 v9, v8
144; RV32D-NEXT:    vfcvt.f.xu.v v8, v9
145; RV32D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
146; RV32D-NEXT:    vnsrl.wi v8, v8, 23
147; RV32D-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
148; RV32D-NEXT:    vnsrl.wx v8, v8, zero
149; RV32D-NEXT:    li a0, 127
150; RV32D-NEXT:    vsub.vx v8, v8, a0
151; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
152; RV32D-NEXT:    ret
153;
154; RV64D-LABEL: cttz_nxv2i8:
155; RV64D:       # %bb.0:
156; RV64D-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
157; RV64D-NEXT:    vmv.v.i v9, 0
158; RV64D-NEXT:    vmseq.vv v0, v9, v8
159; RV64D-NEXT:    vrsub.vi v9, v8, 0
160; RV64D-NEXT:    vand.vv v8, v8, v9
161; RV64D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
162; RV64D-NEXT:    vzext.vf4 v9, v8
163; RV64D-NEXT:    vfcvt.f.xu.v v8, v9
164; RV64D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
165; RV64D-NEXT:    vnsrl.wi v8, v8, 23
166; RV64D-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
167; RV64D-NEXT:    vnsrl.wx v8, v8, zero
168; RV64D-NEXT:    li a0, 127
169; RV64D-NEXT:    vsub.vx v8, v8, a0
170; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
171; RV64D-NEXT:    ret
172  %a = call <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 false)
173  ret <vscale x 2 x i8> %a
174}
175declare <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8>, i1)
176
177define <vscale x 4 x i8> @cttz_nxv4i8(<vscale x 4 x i8> %va) {
178; RV32I-LABEL: cttz_nxv4i8:
179; RV32I:       # %bb.0:
180; RV32I-NEXT:    li a0, 1
181; RV32I-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
182; RV32I-NEXT:    vsub.vx v9, v8, a0
183; RV32I-NEXT:    vxor.vi v8, v8, -1
184; RV32I-NEXT:    vand.vv v8, v8, v9
185; RV32I-NEXT:    vsrl.vi v9, v8, 1
186; RV32I-NEXT:    li a0, 85
187; RV32I-NEXT:    vand.vx v9, v9, a0
188; RV32I-NEXT:    vsub.vv v8, v8, v9
189; RV32I-NEXT:    li a0, 51
190; RV32I-NEXT:    vand.vx v9, v8, a0
191; RV32I-NEXT:    vsrl.vi v8, v8, 2
192; RV32I-NEXT:    vand.vx v8, v8, a0
193; RV32I-NEXT:    vadd.vv v8, v9, v8
194; RV32I-NEXT:    vsrl.vi v9, v8, 4
195; RV32I-NEXT:    vadd.vv v8, v8, v9
196; RV32I-NEXT:    vand.vi v8, v8, 15
197; RV32I-NEXT:    ret
198;
199; RV64I-LABEL: cttz_nxv4i8:
200; RV64I:       # %bb.0:
201; RV64I-NEXT:    li a0, 1
202; RV64I-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
203; RV64I-NEXT:    vsub.vx v9, v8, a0
204; RV64I-NEXT:    vxor.vi v8, v8, -1
205; RV64I-NEXT:    vand.vv v8, v8, v9
206; RV64I-NEXT:    vsrl.vi v9, v8, 1
207; RV64I-NEXT:    li a0, 85
208; RV64I-NEXT:    vand.vx v9, v9, a0
209; RV64I-NEXT:    vsub.vv v8, v8, v9
210; RV64I-NEXT:    li a0, 51
211; RV64I-NEXT:    vand.vx v9, v8, a0
212; RV64I-NEXT:    vsrl.vi v8, v8, 2
213; RV64I-NEXT:    vand.vx v8, v8, a0
214; RV64I-NEXT:    vadd.vv v8, v9, v8
215; RV64I-NEXT:    vsrl.vi v9, v8, 4
216; RV64I-NEXT:    vadd.vv v8, v8, v9
217; RV64I-NEXT:    vand.vi v8, v8, 15
218; RV64I-NEXT:    ret
219;
220; RV32D-LABEL: cttz_nxv4i8:
221; RV32D:       # %bb.0:
222; RV32D-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
223; RV32D-NEXT:    vmv.v.i v9, 0
224; RV32D-NEXT:    vmseq.vv v0, v9, v8
225; RV32D-NEXT:    vrsub.vi v9, v8, 0
226; RV32D-NEXT:    vand.vv v8, v8, v9
227; RV32D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
228; RV32D-NEXT:    vzext.vf4 v10, v8
229; RV32D-NEXT:    vfcvt.f.xu.v v8, v10
230; RV32D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
231; RV32D-NEXT:    vnsrl.wi v10, v8, 23
232; RV32D-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
233; RV32D-NEXT:    vnsrl.wx v8, v10, zero
234; RV32D-NEXT:    li a0, 127
235; RV32D-NEXT:    vsub.vx v8, v8, a0
236; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
237; RV32D-NEXT:    ret
238;
239; RV64D-LABEL: cttz_nxv4i8:
240; RV64D:       # %bb.0:
241; RV64D-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
242; RV64D-NEXT:    vmv.v.i v9, 0
243; RV64D-NEXT:    vmseq.vv v0, v9, v8
244; RV64D-NEXT:    vrsub.vi v9, v8, 0
245; RV64D-NEXT:    vand.vv v8, v8, v9
246; RV64D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
247; RV64D-NEXT:    vzext.vf4 v10, v8
248; RV64D-NEXT:    vfcvt.f.xu.v v8, v10
249; RV64D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
250; RV64D-NEXT:    vnsrl.wi v10, v8, 23
251; RV64D-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
252; RV64D-NEXT:    vnsrl.wx v8, v10, zero
253; RV64D-NEXT:    li a0, 127
254; RV64D-NEXT:    vsub.vx v8, v8, a0
255; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
256; RV64D-NEXT:    ret
257  %a = call <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 false)
258  ret <vscale x 4 x i8> %a
259}
260declare <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8>, i1)
261
262define <vscale x 8 x i8> @cttz_nxv8i8(<vscale x 8 x i8> %va) {
263; RV32I-LABEL: cttz_nxv8i8:
264; RV32I:       # %bb.0:
265; RV32I-NEXT:    li a0, 1
266; RV32I-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
267; RV32I-NEXT:    vsub.vx v9, v8, a0
268; RV32I-NEXT:    vxor.vi v8, v8, -1
269; RV32I-NEXT:    vand.vv v8, v8, v9
270; RV32I-NEXT:    vsrl.vi v9, v8, 1
271; RV32I-NEXT:    li a0, 85
272; RV32I-NEXT:    vand.vx v9, v9, a0
273; RV32I-NEXT:    vsub.vv v8, v8, v9
274; RV32I-NEXT:    li a0, 51
275; RV32I-NEXT:    vand.vx v9, v8, a0
276; RV32I-NEXT:    vsrl.vi v8, v8, 2
277; RV32I-NEXT:    vand.vx v8, v8, a0
278; RV32I-NEXT:    vadd.vv v8, v9, v8
279; RV32I-NEXT:    vsrl.vi v9, v8, 4
280; RV32I-NEXT:    vadd.vv v8, v8, v9
281; RV32I-NEXT:    vand.vi v8, v8, 15
282; RV32I-NEXT:    ret
283;
284; RV64I-LABEL: cttz_nxv8i8:
285; RV64I:       # %bb.0:
286; RV64I-NEXT:    li a0, 1
287; RV64I-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
288; RV64I-NEXT:    vsub.vx v9, v8, a0
289; RV64I-NEXT:    vxor.vi v8, v8, -1
290; RV64I-NEXT:    vand.vv v8, v8, v9
291; RV64I-NEXT:    vsrl.vi v9, v8, 1
292; RV64I-NEXT:    li a0, 85
293; RV64I-NEXT:    vand.vx v9, v9, a0
294; RV64I-NEXT:    vsub.vv v8, v8, v9
295; RV64I-NEXT:    li a0, 51
296; RV64I-NEXT:    vand.vx v9, v8, a0
297; RV64I-NEXT:    vsrl.vi v8, v8, 2
298; RV64I-NEXT:    vand.vx v8, v8, a0
299; RV64I-NEXT:    vadd.vv v8, v9, v8
300; RV64I-NEXT:    vsrl.vi v9, v8, 4
301; RV64I-NEXT:    vadd.vv v8, v8, v9
302; RV64I-NEXT:    vand.vi v8, v8, 15
303; RV64I-NEXT:    ret
304;
305; RV32D-LABEL: cttz_nxv8i8:
306; RV32D:       # %bb.0:
307; RV32D-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
308; RV32D-NEXT:    vmv.v.i v9, 0
309; RV32D-NEXT:    vmseq.vv v0, v9, v8
310; RV32D-NEXT:    vrsub.vi v9, v8, 0
311; RV32D-NEXT:    vand.vv v8, v8, v9
312; RV32D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
313; RV32D-NEXT:    vzext.vf4 v12, v8
314; RV32D-NEXT:    vfcvt.f.xu.v v8, v12
315; RV32D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
316; RV32D-NEXT:    vnsrl.wi v12, v8, 23
317; RV32D-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
318; RV32D-NEXT:    vnsrl.wx v8, v12, zero
319; RV32D-NEXT:    li a0, 127
320; RV32D-NEXT:    vsub.vx v8, v8, a0
321; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
322; RV32D-NEXT:    ret
323;
324; RV64D-LABEL: cttz_nxv8i8:
325; RV64D:       # %bb.0:
326; RV64D-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
327; RV64D-NEXT:    vmv.v.i v9, 0
328; RV64D-NEXT:    vmseq.vv v0, v9, v8
329; RV64D-NEXT:    vrsub.vi v9, v8, 0
330; RV64D-NEXT:    vand.vv v8, v8, v9
331; RV64D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
332; RV64D-NEXT:    vzext.vf4 v12, v8
333; RV64D-NEXT:    vfcvt.f.xu.v v8, v12
334; RV64D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
335; RV64D-NEXT:    vnsrl.wi v12, v8, 23
336; RV64D-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
337; RV64D-NEXT:    vnsrl.wx v8, v12, zero
338; RV64D-NEXT:    li a0, 127
339; RV64D-NEXT:    vsub.vx v8, v8, a0
340; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
341; RV64D-NEXT:    ret
342  %a = call <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 false)
343  ret <vscale x 8 x i8> %a
344}
345declare <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8>, i1)
346
347define <vscale x 16 x i8> @cttz_nxv16i8(<vscale x 16 x i8> %va) {
348; RV32I-LABEL: cttz_nxv16i8:
349; RV32I:       # %bb.0:
350; RV32I-NEXT:    li a0, 1
351; RV32I-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
352; RV32I-NEXT:    vsub.vx v10, v8, a0
353; RV32I-NEXT:    vxor.vi v8, v8, -1
354; RV32I-NEXT:    vand.vv v8, v8, v10
355; RV32I-NEXT:    vsrl.vi v10, v8, 1
356; RV32I-NEXT:    li a0, 85
357; RV32I-NEXT:    vand.vx v10, v10, a0
358; RV32I-NEXT:    vsub.vv v8, v8, v10
359; RV32I-NEXT:    li a0, 51
360; RV32I-NEXT:    vand.vx v10, v8, a0
361; RV32I-NEXT:    vsrl.vi v8, v8, 2
362; RV32I-NEXT:    vand.vx v8, v8, a0
363; RV32I-NEXT:    vadd.vv v8, v10, v8
364; RV32I-NEXT:    vsrl.vi v10, v8, 4
365; RV32I-NEXT:    vadd.vv v8, v8, v10
366; RV32I-NEXT:    vand.vi v8, v8, 15
367; RV32I-NEXT:    ret
368;
369; RV64I-LABEL: cttz_nxv16i8:
370; RV64I:       # %bb.0:
371; RV64I-NEXT:    li a0, 1
372; RV64I-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
373; RV64I-NEXT:    vsub.vx v10, v8, a0
374; RV64I-NEXT:    vxor.vi v8, v8, -1
375; RV64I-NEXT:    vand.vv v8, v8, v10
376; RV64I-NEXT:    vsrl.vi v10, v8, 1
377; RV64I-NEXT:    li a0, 85
378; RV64I-NEXT:    vand.vx v10, v10, a0
379; RV64I-NEXT:    vsub.vv v8, v8, v10
380; RV64I-NEXT:    li a0, 51
381; RV64I-NEXT:    vand.vx v10, v8, a0
382; RV64I-NEXT:    vsrl.vi v8, v8, 2
383; RV64I-NEXT:    vand.vx v8, v8, a0
384; RV64I-NEXT:    vadd.vv v8, v10, v8
385; RV64I-NEXT:    vsrl.vi v10, v8, 4
386; RV64I-NEXT:    vadd.vv v8, v8, v10
387; RV64I-NEXT:    vand.vi v8, v8, 15
388; RV64I-NEXT:    ret
389;
390; RV32D-LABEL: cttz_nxv16i8:
391; RV32D:       # %bb.0:
392; RV32D-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
393; RV32D-NEXT:    vmv.v.i v10, 0
394; RV32D-NEXT:    vmseq.vv v0, v10, v8
395; RV32D-NEXT:    vrsub.vi v10, v8, 0
396; RV32D-NEXT:    vand.vv v8, v8, v10
397; RV32D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
398; RV32D-NEXT:    vzext.vf4 v16, v8
399; RV32D-NEXT:    vfcvt.f.xu.v v8, v16
400; RV32D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
401; RV32D-NEXT:    vnsrl.wi v16, v8, 23
402; RV32D-NEXT:    vsetvli zero, zero, e8, m2, ta, mu
403; RV32D-NEXT:    vnsrl.wx v8, v16, zero
404; RV32D-NEXT:    li a0, 127
405; RV32D-NEXT:    vsub.vx v8, v8, a0
406; RV32D-NEXT:    vmerge.vim v8, v8, 8, v0
407; RV32D-NEXT:    ret
408;
409; RV64D-LABEL: cttz_nxv16i8:
410; RV64D:       # %bb.0:
411; RV64D-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
412; RV64D-NEXT:    vmv.v.i v10, 0
413; RV64D-NEXT:    vmseq.vv v0, v10, v8
414; RV64D-NEXT:    vrsub.vi v10, v8, 0
415; RV64D-NEXT:    vand.vv v8, v8, v10
416; RV64D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
417; RV64D-NEXT:    vzext.vf4 v16, v8
418; RV64D-NEXT:    vfcvt.f.xu.v v8, v16
419; RV64D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
420; RV64D-NEXT:    vnsrl.wi v16, v8, 23
421; RV64D-NEXT:    vsetvli zero, zero, e8, m2, ta, mu
422; RV64D-NEXT:    vnsrl.wx v8, v16, zero
423; RV64D-NEXT:    li a0, 127
424; RV64D-NEXT:    vsub.vx v8, v8, a0
425; RV64D-NEXT:    vmerge.vim v8, v8, 8, v0
426; RV64D-NEXT:    ret
427  %a = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 false)
428  ret <vscale x 16 x i8> %a
429}
430declare <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8>, i1)
431
432define <vscale x 32 x i8> @cttz_nxv32i8(<vscale x 32 x i8> %va) {
433; CHECK-LABEL: cttz_nxv32i8:
434; CHECK:       # %bb.0:
435; CHECK-NEXT:    li a0, 1
436; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
437; CHECK-NEXT:    vsub.vx v12, v8, a0
438; CHECK-NEXT:    vxor.vi v8, v8, -1
439; CHECK-NEXT:    vand.vv v8, v8, v12
440; CHECK-NEXT:    vsrl.vi v12, v8, 1
441; CHECK-NEXT:    li a0, 85
442; CHECK-NEXT:    vand.vx v12, v12, a0
443; CHECK-NEXT:    vsub.vv v8, v8, v12
444; CHECK-NEXT:    li a0, 51
445; CHECK-NEXT:    vand.vx v12, v8, a0
446; CHECK-NEXT:    vsrl.vi v8, v8, 2
447; CHECK-NEXT:    vand.vx v8, v8, a0
448; CHECK-NEXT:    vadd.vv v8, v12, v8
449; CHECK-NEXT:    vsrl.vi v12, v8, 4
450; CHECK-NEXT:    vadd.vv v8, v8, v12
451; CHECK-NEXT:    vand.vi v8, v8, 15
452; CHECK-NEXT:    ret
453  %a = call <vscale x 32 x i8> @llvm.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 false)
454  ret <vscale x 32 x i8> %a
455}
456declare <vscale x 32 x i8> @llvm.cttz.nxv32i8(<vscale x 32 x i8>, i1)
457
458define <vscale x 64 x i8> @cttz_nxv64i8(<vscale x 64 x i8> %va) {
459; CHECK-LABEL: cttz_nxv64i8:
460; CHECK:       # %bb.0:
461; CHECK-NEXT:    li a0, 1
462; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
463; CHECK-NEXT:    vsub.vx v16, v8, a0
464; CHECK-NEXT:    vxor.vi v8, v8, -1
465; CHECK-NEXT:    vand.vv v8, v8, v16
466; CHECK-NEXT:    vsrl.vi v16, v8, 1
467; CHECK-NEXT:    li a0, 85
468; CHECK-NEXT:    vand.vx v16, v16, a0
469; CHECK-NEXT:    vsub.vv v8, v8, v16
470; CHECK-NEXT:    li a0, 51
471; CHECK-NEXT:    vand.vx v16, v8, a0
472; CHECK-NEXT:    vsrl.vi v8, v8, 2
473; CHECK-NEXT:    vand.vx v8, v8, a0
474; CHECK-NEXT:    vadd.vv v8, v16, v8
475; CHECK-NEXT:    vsrl.vi v16, v8, 4
476; CHECK-NEXT:    vadd.vv v8, v8, v16
477; CHECK-NEXT:    vand.vi v8, v8, 15
478; CHECK-NEXT:    ret
479  %a = call <vscale x 64 x i8> @llvm.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 false)
480  ret <vscale x 64 x i8> %a
481}
482declare <vscale x 64 x i8> @llvm.cttz.nxv64i8(<vscale x 64 x i8>, i1)
483
484define <vscale x 1 x i16> @cttz_nxv1i16(<vscale x 1 x i16> %va) {
485; RV32I-LABEL: cttz_nxv1i16:
486; RV32I:       # %bb.0:
487; RV32I-NEXT:    li a0, 1
488; RV32I-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
489; RV32I-NEXT:    vsub.vx v9, v8, a0
490; RV32I-NEXT:    vxor.vi v8, v8, -1
491; RV32I-NEXT:    vand.vv v8, v8, v9
492; RV32I-NEXT:    vsrl.vi v9, v8, 1
493; RV32I-NEXT:    lui a0, 5
494; RV32I-NEXT:    addi a0, a0, 1365
495; RV32I-NEXT:    vand.vx v9, v9, a0
496; RV32I-NEXT:    vsub.vv v8, v8, v9
497; RV32I-NEXT:    lui a0, 3
498; RV32I-NEXT:    addi a0, a0, 819
499; RV32I-NEXT:    vand.vx v9, v8, a0
500; RV32I-NEXT:    vsrl.vi v8, v8, 2
501; RV32I-NEXT:    vand.vx v8, v8, a0
502; RV32I-NEXT:    vadd.vv v8, v9, v8
503; RV32I-NEXT:    vsrl.vi v9, v8, 4
504; RV32I-NEXT:    vadd.vv v8, v8, v9
505; RV32I-NEXT:    lui a0, 1
506; RV32I-NEXT:    addi a0, a0, -241
507; RV32I-NEXT:    vand.vx v8, v8, a0
508; RV32I-NEXT:    li a0, 257
509; RV32I-NEXT:    vmul.vx v8, v8, a0
510; RV32I-NEXT:    vsrl.vi v8, v8, 8
511; RV32I-NEXT:    ret
512;
513; RV64I-LABEL: cttz_nxv1i16:
514; RV64I:       # %bb.0:
515; RV64I-NEXT:    li a0, 1
516; RV64I-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
517; RV64I-NEXT:    vsub.vx v9, v8, a0
518; RV64I-NEXT:    vxor.vi v8, v8, -1
519; RV64I-NEXT:    vand.vv v8, v8, v9
520; RV64I-NEXT:    vsrl.vi v9, v8, 1
521; RV64I-NEXT:    lui a0, 5
522; RV64I-NEXT:    addiw a0, a0, 1365
523; RV64I-NEXT:    vand.vx v9, v9, a0
524; RV64I-NEXT:    vsub.vv v8, v8, v9
525; RV64I-NEXT:    lui a0, 3
526; RV64I-NEXT:    addiw a0, a0, 819
527; RV64I-NEXT:    vand.vx v9, v8, a0
528; RV64I-NEXT:    vsrl.vi v8, v8, 2
529; RV64I-NEXT:    vand.vx v8, v8, a0
530; RV64I-NEXT:    vadd.vv v8, v9, v8
531; RV64I-NEXT:    vsrl.vi v9, v8, 4
532; RV64I-NEXT:    vadd.vv v8, v8, v9
533; RV64I-NEXT:    lui a0, 1
534; RV64I-NEXT:    addiw a0, a0, -241
535; RV64I-NEXT:    vand.vx v8, v8, a0
536; RV64I-NEXT:    li a0, 257
537; RV64I-NEXT:    vmul.vx v8, v8, a0
538; RV64I-NEXT:    vsrl.vi v8, v8, 8
539; RV64I-NEXT:    ret
540;
541; RV32D-LABEL: cttz_nxv1i16:
542; RV32D:       # %bb.0:
543; RV32D-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
544; RV32D-NEXT:    vmv.v.i v9, 0
545; RV32D-NEXT:    vmseq.vv v0, v9, v8
546; RV32D-NEXT:    vrsub.vi v9, v8, 0
547; RV32D-NEXT:    vand.vv v8, v8, v9
548; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
549; RV32D-NEXT:    vnsrl.wi v8, v9, 23
550; RV32D-NEXT:    li a0, 127
551; RV32D-NEXT:    vsub.vx v8, v8, a0
552; RV32D-NEXT:    li a0, 16
553; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
554; RV32D-NEXT:    ret
555;
556; RV64D-LABEL: cttz_nxv1i16:
557; RV64D:       # %bb.0:
558; RV64D-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
559; RV64D-NEXT:    vmv.v.i v9, 0
560; RV64D-NEXT:    vmseq.vv v0, v9, v8
561; RV64D-NEXT:    vrsub.vi v9, v8, 0
562; RV64D-NEXT:    vand.vv v8, v8, v9
563; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
564; RV64D-NEXT:    vnsrl.wi v8, v9, 23
565; RV64D-NEXT:    li a0, 127
566; RV64D-NEXT:    vsub.vx v8, v8, a0
567; RV64D-NEXT:    li a0, 16
568; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
569; RV64D-NEXT:    ret
570  %a = call <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 false)
571  ret <vscale x 1 x i16> %a
572}
573declare <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16>, i1)
574
575define <vscale x 2 x i16> @cttz_nxv2i16(<vscale x 2 x i16> %va) {
576; RV32I-LABEL: cttz_nxv2i16:
577; RV32I:       # %bb.0:
578; RV32I-NEXT:    li a0, 1
579; RV32I-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
580; RV32I-NEXT:    vsub.vx v9, v8, a0
581; RV32I-NEXT:    vxor.vi v8, v8, -1
582; RV32I-NEXT:    vand.vv v8, v8, v9
583; RV32I-NEXT:    vsrl.vi v9, v8, 1
584; RV32I-NEXT:    lui a0, 5
585; RV32I-NEXT:    addi a0, a0, 1365
586; RV32I-NEXT:    vand.vx v9, v9, a0
587; RV32I-NEXT:    vsub.vv v8, v8, v9
588; RV32I-NEXT:    lui a0, 3
589; RV32I-NEXT:    addi a0, a0, 819
590; RV32I-NEXT:    vand.vx v9, v8, a0
591; RV32I-NEXT:    vsrl.vi v8, v8, 2
592; RV32I-NEXT:    vand.vx v8, v8, a0
593; RV32I-NEXT:    vadd.vv v8, v9, v8
594; RV32I-NEXT:    vsrl.vi v9, v8, 4
595; RV32I-NEXT:    vadd.vv v8, v8, v9
596; RV32I-NEXT:    lui a0, 1
597; RV32I-NEXT:    addi a0, a0, -241
598; RV32I-NEXT:    vand.vx v8, v8, a0
599; RV32I-NEXT:    li a0, 257
600; RV32I-NEXT:    vmul.vx v8, v8, a0
601; RV32I-NEXT:    vsrl.vi v8, v8, 8
602; RV32I-NEXT:    ret
603;
604; RV64I-LABEL: cttz_nxv2i16:
605; RV64I:       # %bb.0:
606; RV64I-NEXT:    li a0, 1
607; RV64I-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
608; RV64I-NEXT:    vsub.vx v9, v8, a0
609; RV64I-NEXT:    vxor.vi v8, v8, -1
610; RV64I-NEXT:    vand.vv v8, v8, v9
611; RV64I-NEXT:    vsrl.vi v9, v8, 1
612; RV64I-NEXT:    lui a0, 5
613; RV64I-NEXT:    addiw a0, a0, 1365
614; RV64I-NEXT:    vand.vx v9, v9, a0
615; RV64I-NEXT:    vsub.vv v8, v8, v9
616; RV64I-NEXT:    lui a0, 3
617; RV64I-NEXT:    addiw a0, a0, 819
618; RV64I-NEXT:    vand.vx v9, v8, a0
619; RV64I-NEXT:    vsrl.vi v8, v8, 2
620; RV64I-NEXT:    vand.vx v8, v8, a0
621; RV64I-NEXT:    vadd.vv v8, v9, v8
622; RV64I-NEXT:    vsrl.vi v9, v8, 4
623; RV64I-NEXT:    vadd.vv v8, v8, v9
624; RV64I-NEXT:    lui a0, 1
625; RV64I-NEXT:    addiw a0, a0, -241
626; RV64I-NEXT:    vand.vx v8, v8, a0
627; RV64I-NEXT:    li a0, 257
628; RV64I-NEXT:    vmul.vx v8, v8, a0
629; RV64I-NEXT:    vsrl.vi v8, v8, 8
630; RV64I-NEXT:    ret
631;
632; RV32D-LABEL: cttz_nxv2i16:
633; RV32D:       # %bb.0:
634; RV32D-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
635; RV32D-NEXT:    vmv.v.i v9, 0
636; RV32D-NEXT:    vmseq.vv v0, v9, v8
637; RV32D-NEXT:    vrsub.vi v9, v8, 0
638; RV32D-NEXT:    vand.vv v8, v8, v9
639; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
640; RV32D-NEXT:    vnsrl.wi v8, v9, 23
641; RV32D-NEXT:    li a0, 127
642; RV32D-NEXT:    vsub.vx v8, v8, a0
643; RV32D-NEXT:    li a0, 16
644; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
645; RV32D-NEXT:    ret
646;
647; RV64D-LABEL: cttz_nxv2i16:
648; RV64D:       # %bb.0:
649; RV64D-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
650; RV64D-NEXT:    vmv.v.i v9, 0
651; RV64D-NEXT:    vmseq.vv v0, v9, v8
652; RV64D-NEXT:    vrsub.vi v9, v8, 0
653; RV64D-NEXT:    vand.vv v8, v8, v9
654; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
655; RV64D-NEXT:    vnsrl.wi v8, v9, 23
656; RV64D-NEXT:    li a0, 127
657; RV64D-NEXT:    vsub.vx v8, v8, a0
658; RV64D-NEXT:    li a0, 16
659; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
660; RV64D-NEXT:    ret
661  %a = call <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 false)
662  ret <vscale x 2 x i16> %a
663}
664declare <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16>, i1)
665
666define <vscale x 4 x i16> @cttz_nxv4i16(<vscale x 4 x i16> %va) {
667; RV32I-LABEL: cttz_nxv4i16:
668; RV32I:       # %bb.0:
669; RV32I-NEXT:    li a0, 1
670; RV32I-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
671; RV32I-NEXT:    vsub.vx v9, v8, a0
672; RV32I-NEXT:    vxor.vi v8, v8, -1
673; RV32I-NEXT:    vand.vv v8, v8, v9
674; RV32I-NEXT:    vsrl.vi v9, v8, 1
675; RV32I-NEXT:    lui a0, 5
676; RV32I-NEXT:    addi a0, a0, 1365
677; RV32I-NEXT:    vand.vx v9, v9, a0
678; RV32I-NEXT:    vsub.vv v8, v8, v9
679; RV32I-NEXT:    lui a0, 3
680; RV32I-NEXT:    addi a0, a0, 819
681; RV32I-NEXT:    vand.vx v9, v8, a0
682; RV32I-NEXT:    vsrl.vi v8, v8, 2
683; RV32I-NEXT:    vand.vx v8, v8, a0
684; RV32I-NEXT:    vadd.vv v8, v9, v8
685; RV32I-NEXT:    vsrl.vi v9, v8, 4
686; RV32I-NEXT:    vadd.vv v8, v8, v9
687; RV32I-NEXT:    lui a0, 1
688; RV32I-NEXT:    addi a0, a0, -241
689; RV32I-NEXT:    vand.vx v8, v8, a0
690; RV32I-NEXT:    li a0, 257
691; RV32I-NEXT:    vmul.vx v8, v8, a0
692; RV32I-NEXT:    vsrl.vi v8, v8, 8
693; RV32I-NEXT:    ret
694;
695; RV64I-LABEL: cttz_nxv4i16:
696; RV64I:       # %bb.0:
697; RV64I-NEXT:    li a0, 1
698; RV64I-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
699; RV64I-NEXT:    vsub.vx v9, v8, a0
700; RV64I-NEXT:    vxor.vi v8, v8, -1
701; RV64I-NEXT:    vand.vv v8, v8, v9
702; RV64I-NEXT:    vsrl.vi v9, v8, 1
703; RV64I-NEXT:    lui a0, 5
704; RV64I-NEXT:    addiw a0, a0, 1365
705; RV64I-NEXT:    vand.vx v9, v9, a0
706; RV64I-NEXT:    vsub.vv v8, v8, v9
707; RV64I-NEXT:    lui a0, 3
708; RV64I-NEXT:    addiw a0, a0, 819
709; RV64I-NEXT:    vand.vx v9, v8, a0
710; RV64I-NEXT:    vsrl.vi v8, v8, 2
711; RV64I-NEXT:    vand.vx v8, v8, a0
712; RV64I-NEXT:    vadd.vv v8, v9, v8
713; RV64I-NEXT:    vsrl.vi v9, v8, 4
714; RV64I-NEXT:    vadd.vv v8, v8, v9
715; RV64I-NEXT:    lui a0, 1
716; RV64I-NEXT:    addiw a0, a0, -241
717; RV64I-NEXT:    vand.vx v8, v8, a0
718; RV64I-NEXT:    li a0, 257
719; RV64I-NEXT:    vmul.vx v8, v8, a0
720; RV64I-NEXT:    vsrl.vi v8, v8, 8
721; RV64I-NEXT:    ret
722;
723; RV32D-LABEL: cttz_nxv4i16:
724; RV32D:       # %bb.0:
725; RV32D-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
726; RV32D-NEXT:    vmv.v.i v9, 0
727; RV32D-NEXT:    vmseq.vv v0, v9, v8
728; RV32D-NEXT:    vrsub.vi v9, v8, 0
729; RV32D-NEXT:    vand.vv v8, v8, v9
730; RV32D-NEXT:    vfwcvt.f.xu.v v10, v8
731; RV32D-NEXT:    vnsrl.wi v8, v10, 23
732; RV32D-NEXT:    li a0, 127
733; RV32D-NEXT:    vsub.vx v8, v8, a0
734; RV32D-NEXT:    li a0, 16
735; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
736; RV32D-NEXT:    ret
737;
738; RV64D-LABEL: cttz_nxv4i16:
739; RV64D:       # %bb.0:
740; RV64D-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
741; RV64D-NEXT:    vmv.v.i v9, 0
742; RV64D-NEXT:    vmseq.vv v0, v9, v8
743; RV64D-NEXT:    vrsub.vi v9, v8, 0
744; RV64D-NEXT:    vand.vv v8, v8, v9
745; RV64D-NEXT:    vfwcvt.f.xu.v v10, v8
746; RV64D-NEXT:    vnsrl.wi v8, v10, 23
747; RV64D-NEXT:    li a0, 127
748; RV64D-NEXT:    vsub.vx v8, v8, a0
749; RV64D-NEXT:    li a0, 16
750; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
751; RV64D-NEXT:    ret
752  %a = call <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 false)
753  ret <vscale x 4 x i16> %a
754}
755declare <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16>, i1)
756
757define <vscale x 8 x i16> @cttz_nxv8i16(<vscale x 8 x i16> %va) {
758; RV32I-LABEL: cttz_nxv8i16:
759; RV32I:       # %bb.0:
760; RV32I-NEXT:    li a0, 1
761; RV32I-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
762; RV32I-NEXT:    vsub.vx v10, v8, a0
763; RV32I-NEXT:    vxor.vi v8, v8, -1
764; RV32I-NEXT:    vand.vv v8, v8, v10
765; RV32I-NEXT:    vsrl.vi v10, v8, 1
766; RV32I-NEXT:    lui a0, 5
767; RV32I-NEXT:    addi a0, a0, 1365
768; RV32I-NEXT:    vand.vx v10, v10, a0
769; RV32I-NEXT:    vsub.vv v8, v8, v10
770; RV32I-NEXT:    lui a0, 3
771; RV32I-NEXT:    addi a0, a0, 819
772; RV32I-NEXT:    vand.vx v10, v8, a0
773; RV32I-NEXT:    vsrl.vi v8, v8, 2
774; RV32I-NEXT:    vand.vx v8, v8, a0
775; RV32I-NEXT:    vadd.vv v8, v10, v8
776; RV32I-NEXT:    vsrl.vi v10, v8, 4
777; RV32I-NEXT:    vadd.vv v8, v8, v10
778; RV32I-NEXT:    lui a0, 1
779; RV32I-NEXT:    addi a0, a0, -241
780; RV32I-NEXT:    vand.vx v8, v8, a0
781; RV32I-NEXT:    li a0, 257
782; RV32I-NEXT:    vmul.vx v8, v8, a0
783; RV32I-NEXT:    vsrl.vi v8, v8, 8
784; RV32I-NEXT:    ret
785;
786; RV64I-LABEL: cttz_nxv8i16:
787; RV64I:       # %bb.0:
788; RV64I-NEXT:    li a0, 1
789; RV64I-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
790; RV64I-NEXT:    vsub.vx v10, v8, a0
791; RV64I-NEXT:    vxor.vi v8, v8, -1
792; RV64I-NEXT:    vand.vv v8, v8, v10
793; RV64I-NEXT:    vsrl.vi v10, v8, 1
794; RV64I-NEXT:    lui a0, 5
795; RV64I-NEXT:    addiw a0, a0, 1365
796; RV64I-NEXT:    vand.vx v10, v10, a0
797; RV64I-NEXT:    vsub.vv v8, v8, v10
798; RV64I-NEXT:    lui a0, 3
799; RV64I-NEXT:    addiw a0, a0, 819
800; RV64I-NEXT:    vand.vx v10, v8, a0
801; RV64I-NEXT:    vsrl.vi v8, v8, 2
802; RV64I-NEXT:    vand.vx v8, v8, a0
803; RV64I-NEXT:    vadd.vv v8, v10, v8
804; RV64I-NEXT:    vsrl.vi v10, v8, 4
805; RV64I-NEXT:    vadd.vv v8, v8, v10
806; RV64I-NEXT:    lui a0, 1
807; RV64I-NEXT:    addiw a0, a0, -241
808; RV64I-NEXT:    vand.vx v8, v8, a0
809; RV64I-NEXT:    li a0, 257
810; RV64I-NEXT:    vmul.vx v8, v8, a0
811; RV64I-NEXT:    vsrl.vi v8, v8, 8
812; RV64I-NEXT:    ret
813;
814; RV32D-LABEL: cttz_nxv8i16:
815; RV32D:       # %bb.0:
816; RV32D-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
817; RV32D-NEXT:    vmv.v.i v10, 0
818; RV32D-NEXT:    vmseq.vv v0, v10, v8
819; RV32D-NEXT:    vrsub.vi v10, v8, 0
820; RV32D-NEXT:    vand.vv v8, v8, v10
821; RV32D-NEXT:    vfwcvt.f.xu.v v12, v8
822; RV32D-NEXT:    vnsrl.wi v8, v12, 23
823; RV32D-NEXT:    li a0, 127
824; RV32D-NEXT:    vsub.vx v8, v8, a0
825; RV32D-NEXT:    li a0, 16
826; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
827; RV32D-NEXT:    ret
828;
829; RV64D-LABEL: cttz_nxv8i16:
830; RV64D:       # %bb.0:
831; RV64D-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
832; RV64D-NEXT:    vmv.v.i v10, 0
833; RV64D-NEXT:    vmseq.vv v0, v10, v8
834; RV64D-NEXT:    vrsub.vi v10, v8, 0
835; RV64D-NEXT:    vand.vv v8, v8, v10
836; RV64D-NEXT:    vfwcvt.f.xu.v v12, v8
837; RV64D-NEXT:    vnsrl.wi v8, v12, 23
838; RV64D-NEXT:    li a0, 127
839; RV64D-NEXT:    vsub.vx v8, v8, a0
840; RV64D-NEXT:    li a0, 16
841; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
842; RV64D-NEXT:    ret
843  %a = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 false)
844  ret <vscale x 8 x i16> %a
845}
846declare <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16>, i1)
847
848define <vscale x 16 x i16> @cttz_nxv16i16(<vscale x 16 x i16> %va) {
849; RV32I-LABEL: cttz_nxv16i16:
850; RV32I:       # %bb.0:
851; RV32I-NEXT:    li a0, 1
852; RV32I-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
853; RV32I-NEXT:    vsub.vx v12, v8, a0
854; RV32I-NEXT:    vxor.vi v8, v8, -1
855; RV32I-NEXT:    vand.vv v8, v8, v12
856; RV32I-NEXT:    vsrl.vi v12, v8, 1
857; RV32I-NEXT:    lui a0, 5
858; RV32I-NEXT:    addi a0, a0, 1365
859; RV32I-NEXT:    vand.vx v12, v12, a0
860; RV32I-NEXT:    vsub.vv v8, v8, v12
861; RV32I-NEXT:    lui a0, 3
862; RV32I-NEXT:    addi a0, a0, 819
863; RV32I-NEXT:    vand.vx v12, v8, a0
864; RV32I-NEXT:    vsrl.vi v8, v8, 2
865; RV32I-NEXT:    vand.vx v8, v8, a0
866; RV32I-NEXT:    vadd.vv v8, v12, v8
867; RV32I-NEXT:    vsrl.vi v12, v8, 4
868; RV32I-NEXT:    vadd.vv v8, v8, v12
869; RV32I-NEXT:    lui a0, 1
870; RV32I-NEXT:    addi a0, a0, -241
871; RV32I-NEXT:    vand.vx v8, v8, a0
872; RV32I-NEXT:    li a0, 257
873; RV32I-NEXT:    vmul.vx v8, v8, a0
874; RV32I-NEXT:    vsrl.vi v8, v8, 8
875; RV32I-NEXT:    ret
876;
877; RV64I-LABEL: cttz_nxv16i16:
878; RV64I:       # %bb.0:
879; RV64I-NEXT:    li a0, 1
880; RV64I-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
881; RV64I-NEXT:    vsub.vx v12, v8, a0
882; RV64I-NEXT:    vxor.vi v8, v8, -1
883; RV64I-NEXT:    vand.vv v8, v8, v12
884; RV64I-NEXT:    vsrl.vi v12, v8, 1
885; RV64I-NEXT:    lui a0, 5
886; RV64I-NEXT:    addiw a0, a0, 1365
887; RV64I-NEXT:    vand.vx v12, v12, a0
888; RV64I-NEXT:    vsub.vv v8, v8, v12
889; RV64I-NEXT:    lui a0, 3
890; RV64I-NEXT:    addiw a0, a0, 819
891; RV64I-NEXT:    vand.vx v12, v8, a0
892; RV64I-NEXT:    vsrl.vi v8, v8, 2
893; RV64I-NEXT:    vand.vx v8, v8, a0
894; RV64I-NEXT:    vadd.vv v8, v12, v8
895; RV64I-NEXT:    vsrl.vi v12, v8, 4
896; RV64I-NEXT:    vadd.vv v8, v8, v12
897; RV64I-NEXT:    lui a0, 1
898; RV64I-NEXT:    addiw a0, a0, -241
899; RV64I-NEXT:    vand.vx v8, v8, a0
900; RV64I-NEXT:    li a0, 257
901; RV64I-NEXT:    vmul.vx v8, v8, a0
902; RV64I-NEXT:    vsrl.vi v8, v8, 8
903; RV64I-NEXT:    ret
904;
905; RV32D-LABEL: cttz_nxv16i16:
906; RV32D:       # %bb.0:
907; RV32D-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
908; RV32D-NEXT:    vmv.v.i v12, 0
909; RV32D-NEXT:    vmseq.vv v0, v12, v8
910; RV32D-NEXT:    vrsub.vi v12, v8, 0
911; RV32D-NEXT:    vand.vv v8, v8, v12
912; RV32D-NEXT:    vfwcvt.f.xu.v v16, v8
913; RV32D-NEXT:    vnsrl.wi v8, v16, 23
914; RV32D-NEXT:    li a0, 127
915; RV32D-NEXT:    vsub.vx v8, v8, a0
916; RV32D-NEXT:    li a0, 16
917; RV32D-NEXT:    vmerge.vxm v8, v8, a0, v0
918; RV32D-NEXT:    ret
919;
920; RV64D-LABEL: cttz_nxv16i16:
921; RV64D:       # %bb.0:
922; RV64D-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
923; RV64D-NEXT:    vmv.v.i v12, 0
924; RV64D-NEXT:    vmseq.vv v0, v12, v8
925; RV64D-NEXT:    vrsub.vi v12, v8, 0
926; RV64D-NEXT:    vand.vv v8, v8, v12
927; RV64D-NEXT:    vfwcvt.f.xu.v v16, v8
928; RV64D-NEXT:    vnsrl.wi v8, v16, 23
929; RV64D-NEXT:    li a0, 127
930; RV64D-NEXT:    vsub.vx v8, v8, a0
931; RV64D-NEXT:    li a0, 16
932; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
933; RV64D-NEXT:    ret
934  %a = call <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 false)
935  ret <vscale x 16 x i16> %a
936}
937declare <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16>, i1)
938
939define <vscale x 32 x i16> @cttz_nxv32i16(<vscale x 32 x i16> %va) {
940; RV32-LABEL: cttz_nxv32i16:
941; RV32:       # %bb.0:
942; RV32-NEXT:    li a0, 1
943; RV32-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
944; RV32-NEXT:    vsub.vx v16, v8, a0
945; RV32-NEXT:    vxor.vi v8, v8, -1
946; RV32-NEXT:    vand.vv v8, v8, v16
947; RV32-NEXT:    vsrl.vi v16, v8, 1
948; RV32-NEXT:    lui a0, 5
949; RV32-NEXT:    addi a0, a0, 1365
950; RV32-NEXT:    vand.vx v16, v16, a0
951; RV32-NEXT:    vsub.vv v8, v8, v16
952; RV32-NEXT:    lui a0, 3
953; RV32-NEXT:    addi a0, a0, 819
954; RV32-NEXT:    vand.vx v16, v8, a0
955; RV32-NEXT:    vsrl.vi v8, v8, 2
956; RV32-NEXT:    vand.vx v8, v8, a0
957; RV32-NEXT:    vadd.vv v8, v16, v8
958; RV32-NEXT:    vsrl.vi v16, v8, 4
959; RV32-NEXT:    vadd.vv v8, v8, v16
960; RV32-NEXT:    lui a0, 1
961; RV32-NEXT:    addi a0, a0, -241
962; RV32-NEXT:    vand.vx v8, v8, a0
963; RV32-NEXT:    li a0, 257
964; RV32-NEXT:    vmul.vx v8, v8, a0
965; RV32-NEXT:    vsrl.vi v8, v8, 8
966; RV32-NEXT:    ret
967;
968; RV64-LABEL: cttz_nxv32i16:
969; RV64:       # %bb.0:
970; RV64-NEXT:    li a0, 1
971; RV64-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
972; RV64-NEXT:    vsub.vx v16, v8, a0
973; RV64-NEXT:    vxor.vi v8, v8, -1
974; RV64-NEXT:    vand.vv v8, v8, v16
975; RV64-NEXT:    vsrl.vi v16, v8, 1
976; RV64-NEXT:    lui a0, 5
977; RV64-NEXT:    addiw a0, a0, 1365
978; RV64-NEXT:    vand.vx v16, v16, a0
979; RV64-NEXT:    vsub.vv v8, v8, v16
980; RV64-NEXT:    lui a0, 3
981; RV64-NEXT:    addiw a0, a0, 819
982; RV64-NEXT:    vand.vx v16, v8, a0
983; RV64-NEXT:    vsrl.vi v8, v8, 2
984; RV64-NEXT:    vand.vx v8, v8, a0
985; RV64-NEXT:    vadd.vv v8, v16, v8
986; RV64-NEXT:    vsrl.vi v16, v8, 4
987; RV64-NEXT:    vadd.vv v8, v8, v16
988; RV64-NEXT:    lui a0, 1
989; RV64-NEXT:    addiw a0, a0, -241
990; RV64-NEXT:    vand.vx v8, v8, a0
991; RV64-NEXT:    li a0, 257
992; RV64-NEXT:    vmul.vx v8, v8, a0
993; RV64-NEXT:    vsrl.vi v8, v8, 8
994; RV64-NEXT:    ret
995  %a = call <vscale x 32 x i16> @llvm.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 false)
996  ret <vscale x 32 x i16> %a
997}
998declare <vscale x 32 x i16> @llvm.cttz.nxv32i16(<vscale x 32 x i16>, i1)
999
1000define <vscale x 1 x i32> @cttz_nxv1i32(<vscale x 1 x i32> %va) {
1001; RV32I-LABEL: cttz_nxv1i32:
1002; RV32I:       # %bb.0:
1003; RV32I-NEXT:    li a0, 1
1004; RV32I-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
1005; RV32I-NEXT:    vsub.vx v9, v8, a0
1006; RV32I-NEXT:    vxor.vi v8, v8, -1
1007; RV32I-NEXT:    vand.vv v8, v8, v9
1008; RV32I-NEXT:    vsrl.vi v9, v8, 1
1009; RV32I-NEXT:    lui a0, 349525
1010; RV32I-NEXT:    addi a0, a0, 1365
1011; RV32I-NEXT:    vand.vx v9, v9, a0
1012; RV32I-NEXT:    vsub.vv v8, v8, v9
1013; RV32I-NEXT:    lui a0, 209715
1014; RV32I-NEXT:    addi a0, a0, 819
1015; RV32I-NEXT:    vand.vx v9, v8, a0
1016; RV32I-NEXT:    vsrl.vi v8, v8, 2
1017; RV32I-NEXT:    vand.vx v8, v8, a0
1018; RV32I-NEXT:    vadd.vv v8, v9, v8
1019; RV32I-NEXT:    vsrl.vi v9, v8, 4
1020; RV32I-NEXT:    vadd.vv v8, v8, v9
1021; RV32I-NEXT:    lui a0, 61681
1022; RV32I-NEXT:    addi a0, a0, -241
1023; RV32I-NEXT:    vand.vx v8, v8, a0
1024; RV32I-NEXT:    lui a0, 4112
1025; RV32I-NEXT:    addi a0, a0, 257
1026; RV32I-NEXT:    vmul.vx v8, v8, a0
1027; RV32I-NEXT:    vsrl.vi v8, v8, 24
1028; RV32I-NEXT:    ret
1029;
1030; RV64I-LABEL: cttz_nxv1i32:
1031; RV64I:       # %bb.0:
1032; RV64I-NEXT:    li a0, 1
1033; RV64I-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
1034; RV64I-NEXT:    vsub.vx v9, v8, a0
1035; RV64I-NEXT:    vxor.vi v8, v8, -1
1036; RV64I-NEXT:    vand.vv v8, v8, v9
1037; RV64I-NEXT:    vsrl.vi v9, v8, 1
1038; RV64I-NEXT:    lui a0, 349525
1039; RV64I-NEXT:    addiw a0, a0, 1365
1040; RV64I-NEXT:    vand.vx v9, v9, a0
1041; RV64I-NEXT:    vsub.vv v8, v8, v9
1042; RV64I-NEXT:    lui a0, 209715
1043; RV64I-NEXT:    addiw a0, a0, 819
1044; RV64I-NEXT:    vand.vx v9, v8, a0
1045; RV64I-NEXT:    vsrl.vi v8, v8, 2
1046; RV64I-NEXT:    vand.vx v8, v8, a0
1047; RV64I-NEXT:    vadd.vv v8, v9, v8
1048; RV64I-NEXT:    vsrl.vi v9, v8, 4
1049; RV64I-NEXT:    vadd.vv v8, v8, v9
1050; RV64I-NEXT:    lui a0, 61681
1051; RV64I-NEXT:    addiw a0, a0, -241
1052; RV64I-NEXT:    vand.vx v8, v8, a0
1053; RV64I-NEXT:    lui a0, 4112
1054; RV64I-NEXT:    addiw a0, a0, 257
1055; RV64I-NEXT:    vmul.vx v8, v8, a0
1056; RV64I-NEXT:    vsrl.vi v8, v8, 24
1057; RV64I-NEXT:    ret
1058;
1059; RV32D-LABEL: cttz_nxv1i32:
1060; RV32D:       # %bb.0:
1061; RV32D-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
1062; RV32D-NEXT:    vrsub.vi v9, v8, 0
1063; RV32D-NEXT:    vand.vv v9, v8, v9
1064; RV32D-NEXT:    vfwcvt.f.xu.v v10, v9
1065; RV32D-NEXT:    li a0, 52
1066; RV32D-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
1067; RV32D-NEXT:    vsrl.vx v9, v10, a0
1068; RV32D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
1069; RV32D-NEXT:    vnsrl.wx v9, v9, zero
1070; RV32D-NEXT:    li a0, 1023
1071; RV32D-NEXT:    vsub.vx v9, v9, a0
1072; RV32D-NEXT:    vmseq.vi v0, v8, 0
1073; RV32D-NEXT:    li a0, 32
1074; RV32D-NEXT:    vmerge.vxm v8, v9, a0, v0
1075; RV32D-NEXT:    ret
1076;
1077; RV64D-LABEL: cttz_nxv1i32:
1078; RV64D:       # %bb.0:
1079; RV64D-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
1080; RV64D-NEXT:    vmv.v.i v9, 0
1081; RV64D-NEXT:    vmseq.vv v0, v9, v8
1082; RV64D-NEXT:    vrsub.vi v9, v8, 0
1083; RV64D-NEXT:    vand.vv v8, v8, v9
1084; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
1085; RV64D-NEXT:    li a0, 52
1086; RV64D-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
1087; RV64D-NEXT:    vsrl.vx v8, v9, a0
1088; RV64D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
1089; RV64D-NEXT:    vnsrl.wx v8, v8, zero
1090; RV64D-NEXT:    li a0, 1023
1091; RV64D-NEXT:    vsub.vx v8, v8, a0
1092; RV64D-NEXT:    li a0, 32
1093; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
1094; RV64D-NEXT:    ret
1095  %a = call <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 false)
1096  ret <vscale x 1 x i32> %a
1097}
1098declare <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32>, i1)
1099
1100define <vscale x 2 x i32> @cttz_nxv2i32(<vscale x 2 x i32> %va) {
1101; RV32I-LABEL: cttz_nxv2i32:
1102; RV32I:       # %bb.0:
1103; RV32I-NEXT:    li a0, 1
1104; RV32I-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
1105; RV32I-NEXT:    vsub.vx v9, v8, a0
1106; RV32I-NEXT:    vxor.vi v8, v8, -1
1107; RV32I-NEXT:    vand.vv v8, v8, v9
1108; RV32I-NEXT:    vsrl.vi v9, v8, 1
1109; RV32I-NEXT:    lui a0, 349525
1110; RV32I-NEXT:    addi a0, a0, 1365
1111; RV32I-NEXT:    vand.vx v9, v9, a0
1112; RV32I-NEXT:    vsub.vv v8, v8, v9
1113; RV32I-NEXT:    lui a0, 209715
1114; RV32I-NEXT:    addi a0, a0, 819
1115; RV32I-NEXT:    vand.vx v9, v8, a0
1116; RV32I-NEXT:    vsrl.vi v8, v8, 2
1117; RV32I-NEXT:    vand.vx v8, v8, a0
1118; RV32I-NEXT:    vadd.vv v8, v9, v8
1119; RV32I-NEXT:    vsrl.vi v9, v8, 4
1120; RV32I-NEXT:    vadd.vv v8, v8, v9
1121; RV32I-NEXT:    lui a0, 61681
1122; RV32I-NEXT:    addi a0, a0, -241
1123; RV32I-NEXT:    vand.vx v8, v8, a0
1124; RV32I-NEXT:    lui a0, 4112
1125; RV32I-NEXT:    addi a0, a0, 257
1126; RV32I-NEXT:    vmul.vx v8, v8, a0
1127; RV32I-NEXT:    vsrl.vi v8, v8, 24
1128; RV32I-NEXT:    ret
1129;
1130; RV64I-LABEL: cttz_nxv2i32:
1131; RV64I:       # %bb.0:
1132; RV64I-NEXT:    li a0, 1
1133; RV64I-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
1134; RV64I-NEXT:    vsub.vx v9, v8, a0
1135; RV64I-NEXT:    vxor.vi v8, v8, -1
1136; RV64I-NEXT:    vand.vv v8, v8, v9
1137; RV64I-NEXT:    vsrl.vi v9, v8, 1
1138; RV64I-NEXT:    lui a0, 349525
1139; RV64I-NEXT:    addiw a0, a0, 1365
1140; RV64I-NEXT:    vand.vx v9, v9, a0
1141; RV64I-NEXT:    vsub.vv v8, v8, v9
1142; RV64I-NEXT:    lui a0, 209715
1143; RV64I-NEXT:    addiw a0, a0, 819
1144; RV64I-NEXT:    vand.vx v9, v8, a0
1145; RV64I-NEXT:    vsrl.vi v8, v8, 2
1146; RV64I-NEXT:    vand.vx v8, v8, a0
1147; RV64I-NEXT:    vadd.vv v8, v9, v8
1148; RV64I-NEXT:    vsrl.vi v9, v8, 4
1149; RV64I-NEXT:    vadd.vv v8, v8, v9
1150; RV64I-NEXT:    lui a0, 61681
1151; RV64I-NEXT:    addiw a0, a0, -241
1152; RV64I-NEXT:    vand.vx v8, v8, a0
1153; RV64I-NEXT:    lui a0, 4112
1154; RV64I-NEXT:    addiw a0, a0, 257
1155; RV64I-NEXT:    vmul.vx v8, v8, a0
1156; RV64I-NEXT:    vsrl.vi v8, v8, 24
1157; RV64I-NEXT:    ret
1158;
1159; RV32D-LABEL: cttz_nxv2i32:
1160; RV32D:       # %bb.0:
1161; RV32D-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
1162; RV32D-NEXT:    vrsub.vi v9, v8, 0
1163; RV32D-NEXT:    vand.vv v9, v8, v9
1164; RV32D-NEXT:    vfwcvt.f.xu.v v10, v9
1165; RV32D-NEXT:    li a0, 52
1166; RV32D-NEXT:    vsetvli zero, zero, e64, m2, ta, mu
1167; RV32D-NEXT:    vsrl.vx v10, v10, a0
1168; RV32D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
1169; RV32D-NEXT:    vnsrl.wx v9, v10, zero
1170; RV32D-NEXT:    li a0, 1023
1171; RV32D-NEXT:    vsub.vx v9, v9, a0
1172; RV32D-NEXT:    vmseq.vi v0, v8, 0
1173; RV32D-NEXT:    li a0, 32
1174; RV32D-NEXT:    vmerge.vxm v8, v9, a0, v0
1175; RV32D-NEXT:    ret
1176;
1177; RV64D-LABEL: cttz_nxv2i32:
1178; RV64D:       # %bb.0:
1179; RV64D-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
1180; RV64D-NEXT:    vmv.v.i v9, 0
1181; RV64D-NEXT:    vmseq.vv v0, v9, v8
1182; RV64D-NEXT:    vrsub.vi v9, v8, 0
1183; RV64D-NEXT:    vand.vv v8, v8, v9
1184; RV64D-NEXT:    vfwcvt.f.xu.v v10, v8
1185; RV64D-NEXT:    li a0, 52
1186; RV64D-NEXT:    vsetvli zero, zero, e64, m2, ta, mu
1187; RV64D-NEXT:    vsrl.vx v8, v10, a0
1188; RV64D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
1189; RV64D-NEXT:    vnsrl.wx v10, v8, zero
1190; RV64D-NEXT:    li a0, 1023
1191; RV64D-NEXT:    vsub.vx v8, v10, a0
1192; RV64D-NEXT:    li a0, 32
1193; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
1194; RV64D-NEXT:    ret
1195  %a = call <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 false)
1196  ret <vscale x 2 x i32> %a
1197}
1198declare <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32>, i1)
1199
1200define <vscale x 4 x i32> @cttz_nxv4i32(<vscale x 4 x i32> %va) {
1201; RV32I-LABEL: cttz_nxv4i32:
1202; RV32I:       # %bb.0:
1203; RV32I-NEXT:    li a0, 1
1204; RV32I-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
1205; RV32I-NEXT:    vsub.vx v10, v8, a0
1206; RV32I-NEXT:    vxor.vi v8, v8, -1
1207; RV32I-NEXT:    vand.vv v8, v8, v10
1208; RV32I-NEXT:    vsrl.vi v10, v8, 1
1209; RV32I-NEXT:    lui a0, 349525
1210; RV32I-NEXT:    addi a0, a0, 1365
1211; RV32I-NEXT:    vand.vx v10, v10, a0
1212; RV32I-NEXT:    vsub.vv v8, v8, v10
1213; RV32I-NEXT:    lui a0, 209715
1214; RV32I-NEXT:    addi a0, a0, 819
1215; RV32I-NEXT:    vand.vx v10, v8, a0
1216; RV32I-NEXT:    vsrl.vi v8, v8, 2
1217; RV32I-NEXT:    vand.vx v8, v8, a0
1218; RV32I-NEXT:    vadd.vv v8, v10, v8
1219; RV32I-NEXT:    vsrl.vi v10, v8, 4
1220; RV32I-NEXT:    vadd.vv v8, v8, v10
1221; RV32I-NEXT:    lui a0, 61681
1222; RV32I-NEXT:    addi a0, a0, -241
1223; RV32I-NEXT:    vand.vx v8, v8, a0
1224; RV32I-NEXT:    lui a0, 4112
1225; RV32I-NEXT:    addi a0, a0, 257
1226; RV32I-NEXT:    vmul.vx v8, v8, a0
1227; RV32I-NEXT:    vsrl.vi v8, v8, 24
1228; RV32I-NEXT:    ret
1229;
1230; RV64I-LABEL: cttz_nxv4i32:
1231; RV64I:       # %bb.0:
1232; RV64I-NEXT:    li a0, 1
1233; RV64I-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
1234; RV64I-NEXT:    vsub.vx v10, v8, a0
1235; RV64I-NEXT:    vxor.vi v8, v8, -1
1236; RV64I-NEXT:    vand.vv v8, v8, v10
1237; RV64I-NEXT:    vsrl.vi v10, v8, 1
1238; RV64I-NEXT:    lui a0, 349525
1239; RV64I-NEXT:    addiw a0, a0, 1365
1240; RV64I-NEXT:    vand.vx v10, v10, a0
1241; RV64I-NEXT:    vsub.vv v8, v8, v10
1242; RV64I-NEXT:    lui a0, 209715
1243; RV64I-NEXT:    addiw a0, a0, 819
1244; RV64I-NEXT:    vand.vx v10, v8, a0
1245; RV64I-NEXT:    vsrl.vi v8, v8, 2
1246; RV64I-NEXT:    vand.vx v8, v8, a0
1247; RV64I-NEXT:    vadd.vv v8, v10, v8
1248; RV64I-NEXT:    vsrl.vi v10, v8, 4
1249; RV64I-NEXT:    vadd.vv v8, v8, v10
1250; RV64I-NEXT:    lui a0, 61681
1251; RV64I-NEXT:    addiw a0, a0, -241
1252; RV64I-NEXT:    vand.vx v8, v8, a0
1253; RV64I-NEXT:    lui a0, 4112
1254; RV64I-NEXT:    addiw a0, a0, 257
1255; RV64I-NEXT:    vmul.vx v8, v8, a0
1256; RV64I-NEXT:    vsrl.vi v8, v8, 24
1257; RV64I-NEXT:    ret
1258;
1259; RV32D-LABEL: cttz_nxv4i32:
1260; RV32D:       # %bb.0:
1261; RV32D-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
1262; RV32D-NEXT:    vrsub.vi v10, v8, 0
1263; RV32D-NEXT:    vand.vv v10, v8, v10
1264; RV32D-NEXT:    vfwcvt.f.xu.v v12, v10
1265; RV32D-NEXT:    li a0, 52
1266; RV32D-NEXT:    vsetvli zero, zero, e64, m4, ta, mu
1267; RV32D-NEXT:    vsrl.vx v12, v12, a0
1268; RV32D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
1269; RV32D-NEXT:    vnsrl.wx v10, v12, zero
1270; RV32D-NEXT:    li a0, 1023
1271; RV32D-NEXT:    vsub.vx v10, v10, a0
1272; RV32D-NEXT:    vmseq.vi v0, v8, 0
1273; RV32D-NEXT:    li a0, 32
1274; RV32D-NEXT:    vmerge.vxm v8, v10, a0, v0
1275; RV32D-NEXT:    ret
1276;
1277; RV64D-LABEL: cttz_nxv4i32:
1278; RV64D:       # %bb.0:
1279; RV64D-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
1280; RV64D-NEXT:    vmv.v.i v10, 0
1281; RV64D-NEXT:    vmseq.vv v0, v10, v8
1282; RV64D-NEXT:    vrsub.vi v10, v8, 0
1283; RV64D-NEXT:    vand.vv v8, v8, v10
1284; RV64D-NEXT:    vfwcvt.f.xu.v v12, v8
1285; RV64D-NEXT:    li a0, 52
1286; RV64D-NEXT:    vsetvli zero, zero, e64, m4, ta, mu
1287; RV64D-NEXT:    vsrl.vx v8, v12, a0
1288; RV64D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
1289; RV64D-NEXT:    vnsrl.wx v12, v8, zero
1290; RV64D-NEXT:    li a0, 1023
1291; RV64D-NEXT:    vsub.vx v8, v12, a0
1292; RV64D-NEXT:    li a0, 32
1293; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
1294; RV64D-NEXT:    ret
1295  %a = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 false)
1296  ret <vscale x 4 x i32> %a
1297}
1298declare <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32>, i1)
1299
1300define <vscale x 8 x i32> @cttz_nxv8i32(<vscale x 8 x i32> %va) {
1301; RV32I-LABEL: cttz_nxv8i32:
1302; RV32I:       # %bb.0:
1303; RV32I-NEXT:    li a0, 1
1304; RV32I-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1305; RV32I-NEXT:    vsub.vx v12, v8, a0
1306; RV32I-NEXT:    vxor.vi v8, v8, -1
1307; RV32I-NEXT:    vand.vv v8, v8, v12
1308; RV32I-NEXT:    vsrl.vi v12, v8, 1
1309; RV32I-NEXT:    lui a0, 349525
1310; RV32I-NEXT:    addi a0, a0, 1365
1311; RV32I-NEXT:    vand.vx v12, v12, a0
1312; RV32I-NEXT:    vsub.vv v8, v8, v12
1313; RV32I-NEXT:    lui a0, 209715
1314; RV32I-NEXT:    addi a0, a0, 819
1315; RV32I-NEXT:    vand.vx v12, v8, a0
1316; RV32I-NEXT:    vsrl.vi v8, v8, 2
1317; RV32I-NEXT:    vand.vx v8, v8, a0
1318; RV32I-NEXT:    vadd.vv v8, v12, v8
1319; RV32I-NEXT:    vsrl.vi v12, v8, 4
1320; RV32I-NEXT:    vadd.vv v8, v8, v12
1321; RV32I-NEXT:    lui a0, 61681
1322; RV32I-NEXT:    addi a0, a0, -241
1323; RV32I-NEXT:    vand.vx v8, v8, a0
1324; RV32I-NEXT:    lui a0, 4112
1325; RV32I-NEXT:    addi a0, a0, 257
1326; RV32I-NEXT:    vmul.vx v8, v8, a0
1327; RV32I-NEXT:    vsrl.vi v8, v8, 24
1328; RV32I-NEXT:    ret
1329;
1330; RV64I-LABEL: cttz_nxv8i32:
1331; RV64I:       # %bb.0:
1332; RV64I-NEXT:    li a0, 1
1333; RV64I-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1334; RV64I-NEXT:    vsub.vx v12, v8, a0
1335; RV64I-NEXT:    vxor.vi v8, v8, -1
1336; RV64I-NEXT:    vand.vv v8, v8, v12
1337; RV64I-NEXT:    vsrl.vi v12, v8, 1
1338; RV64I-NEXT:    lui a0, 349525
1339; RV64I-NEXT:    addiw a0, a0, 1365
1340; RV64I-NEXT:    vand.vx v12, v12, a0
1341; RV64I-NEXT:    vsub.vv v8, v8, v12
1342; RV64I-NEXT:    lui a0, 209715
1343; RV64I-NEXT:    addiw a0, a0, 819
1344; RV64I-NEXT:    vand.vx v12, v8, a0
1345; RV64I-NEXT:    vsrl.vi v8, v8, 2
1346; RV64I-NEXT:    vand.vx v8, v8, a0
1347; RV64I-NEXT:    vadd.vv v8, v12, v8
1348; RV64I-NEXT:    vsrl.vi v12, v8, 4
1349; RV64I-NEXT:    vadd.vv v8, v8, v12
1350; RV64I-NEXT:    lui a0, 61681
1351; RV64I-NEXT:    addiw a0, a0, -241
1352; RV64I-NEXT:    vand.vx v8, v8, a0
1353; RV64I-NEXT:    lui a0, 4112
1354; RV64I-NEXT:    addiw a0, a0, 257
1355; RV64I-NEXT:    vmul.vx v8, v8, a0
1356; RV64I-NEXT:    vsrl.vi v8, v8, 24
1357; RV64I-NEXT:    ret
1358;
1359; RV32D-LABEL: cttz_nxv8i32:
1360; RV32D:       # %bb.0:
1361; RV32D-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1362; RV32D-NEXT:    vrsub.vi v12, v8, 0
1363; RV32D-NEXT:    vand.vv v12, v8, v12
1364; RV32D-NEXT:    vfwcvt.f.xu.v v16, v12
1365; RV32D-NEXT:    li a0, 52
1366; RV32D-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
1367; RV32D-NEXT:    vsrl.vx v16, v16, a0
1368; RV32D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
1369; RV32D-NEXT:    vnsrl.wx v12, v16, zero
1370; RV32D-NEXT:    li a0, 1023
1371; RV32D-NEXT:    vsub.vx v12, v12, a0
1372; RV32D-NEXT:    vmseq.vi v0, v8, 0
1373; RV32D-NEXT:    li a0, 32
1374; RV32D-NEXT:    vmerge.vxm v8, v12, a0, v0
1375; RV32D-NEXT:    ret
1376;
1377; RV64D-LABEL: cttz_nxv8i32:
1378; RV64D:       # %bb.0:
1379; RV64D-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1380; RV64D-NEXT:    vmv.v.i v12, 0
1381; RV64D-NEXT:    vmseq.vv v0, v12, v8
1382; RV64D-NEXT:    vrsub.vi v12, v8, 0
1383; RV64D-NEXT:    vand.vv v8, v8, v12
1384; RV64D-NEXT:    vfwcvt.f.xu.v v16, v8
1385; RV64D-NEXT:    li a0, 52
1386; RV64D-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
1387; RV64D-NEXT:    vsrl.vx v8, v16, a0
1388; RV64D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
1389; RV64D-NEXT:    vnsrl.wx v16, v8, zero
1390; RV64D-NEXT:    li a0, 1023
1391; RV64D-NEXT:    vsub.vx v8, v16, a0
1392; RV64D-NEXT:    li a0, 32
1393; RV64D-NEXT:    vmerge.vxm v8, v8, a0, v0
1394; RV64D-NEXT:    ret
1395  %a = call <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 false)
1396  ret <vscale x 8 x i32> %a
1397}
1398declare <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32>, i1)
1399
1400define <vscale x 16 x i32> @cttz_nxv16i32(<vscale x 16 x i32> %va) {
1401; RV32-LABEL: cttz_nxv16i32:
1402; RV32:       # %bb.0:
1403; RV32-NEXT:    li a0, 1
1404; RV32-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
1405; RV32-NEXT:    vsub.vx v16, v8, a0
1406; RV32-NEXT:    vxor.vi v8, v8, -1
1407; RV32-NEXT:    vand.vv v8, v8, v16
1408; RV32-NEXT:    vsrl.vi v16, v8, 1
1409; RV32-NEXT:    lui a0, 349525
1410; RV32-NEXT:    addi a0, a0, 1365
1411; RV32-NEXT:    vand.vx v16, v16, a0
1412; RV32-NEXT:    vsub.vv v8, v8, v16
1413; RV32-NEXT:    lui a0, 209715
1414; RV32-NEXT:    addi a0, a0, 819
1415; RV32-NEXT:    vand.vx v16, v8, a0
1416; RV32-NEXT:    vsrl.vi v8, v8, 2
1417; RV32-NEXT:    vand.vx v8, v8, a0
1418; RV32-NEXT:    vadd.vv v8, v16, v8
1419; RV32-NEXT:    vsrl.vi v16, v8, 4
1420; RV32-NEXT:    vadd.vv v8, v8, v16
1421; RV32-NEXT:    lui a0, 61681
1422; RV32-NEXT:    addi a0, a0, -241
1423; RV32-NEXT:    vand.vx v8, v8, a0
1424; RV32-NEXT:    lui a0, 4112
1425; RV32-NEXT:    addi a0, a0, 257
1426; RV32-NEXT:    vmul.vx v8, v8, a0
1427; RV32-NEXT:    vsrl.vi v8, v8, 24
1428; RV32-NEXT:    ret
1429;
1430; RV64-LABEL: cttz_nxv16i32:
1431; RV64:       # %bb.0:
1432; RV64-NEXT:    li a0, 1
1433; RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
1434; RV64-NEXT:    vsub.vx v16, v8, a0
1435; RV64-NEXT:    vxor.vi v8, v8, -1
1436; RV64-NEXT:    vand.vv v8, v8, v16
1437; RV64-NEXT:    vsrl.vi v16, v8, 1
1438; RV64-NEXT:    lui a0, 349525
1439; RV64-NEXT:    addiw a0, a0, 1365
1440; RV64-NEXT:    vand.vx v16, v16, a0
1441; RV64-NEXT:    vsub.vv v8, v8, v16
1442; RV64-NEXT:    lui a0, 209715
1443; RV64-NEXT:    addiw a0, a0, 819
1444; RV64-NEXT:    vand.vx v16, v8, a0
1445; RV64-NEXT:    vsrl.vi v8, v8, 2
1446; RV64-NEXT:    vand.vx v8, v8, a0
1447; RV64-NEXT:    vadd.vv v8, v16, v8
1448; RV64-NEXT:    vsrl.vi v16, v8, 4
1449; RV64-NEXT:    vadd.vv v8, v8, v16
1450; RV64-NEXT:    lui a0, 61681
1451; RV64-NEXT:    addiw a0, a0, -241
1452; RV64-NEXT:    vand.vx v8, v8, a0
1453; RV64-NEXT:    lui a0, 4112
1454; RV64-NEXT:    addiw a0, a0, 257
1455; RV64-NEXT:    vmul.vx v8, v8, a0
1456; RV64-NEXT:    vsrl.vi v8, v8, 24
1457; RV64-NEXT:    ret
1458  %a = call <vscale x 16 x i32> @llvm.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 false)
1459  ret <vscale x 16 x i32> %a
1460}
1461declare <vscale x 16 x i32> @llvm.cttz.nxv16i32(<vscale x 16 x i32>, i1)
1462
1463define <vscale x 1 x i64> @cttz_nxv1i64(<vscale x 1 x i64> %va) {
1464; RV32-LABEL: cttz_nxv1i64:
1465; RV32:       # %bb.0:
1466; RV32-NEXT:    addi sp, sp, -16
1467; RV32-NEXT:    .cfi_def_cfa_offset 16
1468; RV32-NEXT:    lui a0, 349525
1469; RV32-NEXT:    addi a0, a0, 1365
1470; RV32-NEXT:    sw a0, 12(sp)
1471; RV32-NEXT:    sw a0, 8(sp)
1472; RV32-NEXT:    lui a0, 209715
1473; RV32-NEXT:    addi a0, a0, 819
1474; RV32-NEXT:    sw a0, 12(sp)
1475; RV32-NEXT:    sw a0, 8(sp)
1476; RV32-NEXT:    lui a0, 61681
1477; RV32-NEXT:    addi a0, a0, -241
1478; RV32-NEXT:    sw a0, 12(sp)
1479; RV32-NEXT:    sw a0, 8(sp)
1480; RV32-NEXT:    lui a0, 4112
1481; RV32-NEXT:    addi a0, a0, 257
1482; RV32-NEXT:    sw a0, 12(sp)
1483; RV32-NEXT:    sw a0, 8(sp)
1484; RV32-NEXT:    li a0, 1
1485; RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
1486; RV32-NEXT:    vsub.vx v9, v8, a0
1487; RV32-NEXT:    vxor.vi v8, v8, -1
1488; RV32-NEXT:    addi a0, sp, 8
1489; RV32-NEXT:    vlse64.v v10, (a0), zero
1490; RV32-NEXT:    vand.vv v8, v8, v9
1491; RV32-NEXT:    addi a0, sp, 8
1492; RV32-NEXT:    vlse64.v v9, (a0), zero
1493; RV32-NEXT:    vsrl.vi v11, v8, 1
1494; RV32-NEXT:    vand.vv v10, v11, v10
1495; RV32-NEXT:    vsub.vv v8, v8, v10
1496; RV32-NEXT:    vand.vv v10, v8, v9
1497; RV32-NEXT:    vsrl.vi v8, v8, 2
1498; RV32-NEXT:    vand.vv v8, v8, v9
1499; RV32-NEXT:    vadd.vv v8, v10, v8
1500; RV32-NEXT:    addi a0, sp, 8
1501; RV32-NEXT:    vlse64.v v9, (a0), zero
1502; RV32-NEXT:    addi a0, sp, 8
1503; RV32-NEXT:    vlse64.v v10, (a0), zero
1504; RV32-NEXT:    vsrl.vi v11, v8, 4
1505; RV32-NEXT:    vadd.vv v8, v8, v11
1506; RV32-NEXT:    vand.vv v8, v8, v9
1507; RV32-NEXT:    vmul.vv v8, v8, v10
1508; RV32-NEXT:    li a0, 56
1509; RV32-NEXT:    vsrl.vx v8, v8, a0
1510; RV32-NEXT:    addi sp, sp, 16
1511; RV32-NEXT:    ret
1512;
1513; RV64-LABEL: cttz_nxv1i64:
1514; RV64:       # %bb.0:
1515; RV64-NEXT:    li a0, 1
1516; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
1517; RV64-NEXT:    vsub.vx v9, v8, a0
1518; RV64-NEXT:    vxor.vi v8, v8, -1
1519; RV64-NEXT:    vand.vv v8, v8, v9
1520; RV64-NEXT:    lui a0, %hi(.LCPI18_0)
1521; RV64-NEXT:    ld a0, %lo(.LCPI18_0)(a0)
1522; RV64-NEXT:    lui a1, %hi(.LCPI18_1)
1523; RV64-NEXT:    ld a1, %lo(.LCPI18_1)(a1)
1524; RV64-NEXT:    vsrl.vi v9, v8, 1
1525; RV64-NEXT:    vand.vx v9, v9, a0
1526; RV64-NEXT:    vsub.vv v8, v8, v9
1527; RV64-NEXT:    vand.vx v9, v8, a1
1528; RV64-NEXT:    vsrl.vi v8, v8, 2
1529; RV64-NEXT:    vand.vx v8, v8, a1
1530; RV64-NEXT:    vadd.vv v8, v9, v8
1531; RV64-NEXT:    lui a0, %hi(.LCPI18_2)
1532; RV64-NEXT:    ld a0, %lo(.LCPI18_2)(a0)
1533; RV64-NEXT:    lui a1, %hi(.LCPI18_3)
1534; RV64-NEXT:    ld a1, %lo(.LCPI18_3)(a1)
1535; RV64-NEXT:    vsrl.vi v9, v8, 4
1536; RV64-NEXT:    vadd.vv v8, v8, v9
1537; RV64-NEXT:    vand.vx v8, v8, a0
1538; RV64-NEXT:    vmul.vx v8, v8, a1
1539; RV64-NEXT:    li a0, 56
1540; RV64-NEXT:    vsrl.vx v8, v8, a0
1541; RV64-NEXT:    ret
1542  %a = call <vscale x 1 x i64> @llvm.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 false)
1543  ret <vscale x 1 x i64> %a
1544}
1545declare <vscale x 1 x i64> @llvm.cttz.nxv1i64(<vscale x 1 x i64>, i1)
1546
1547define <vscale x 2 x i64> @cttz_nxv2i64(<vscale x 2 x i64> %va) {
1548; RV32-LABEL: cttz_nxv2i64:
1549; RV32:       # %bb.0:
1550; RV32-NEXT:    addi sp, sp, -16
1551; RV32-NEXT:    .cfi_def_cfa_offset 16
1552; RV32-NEXT:    lui a0, 349525
1553; RV32-NEXT:    addi a0, a0, 1365
1554; RV32-NEXT:    sw a0, 12(sp)
1555; RV32-NEXT:    sw a0, 8(sp)
1556; RV32-NEXT:    lui a0, 209715
1557; RV32-NEXT:    addi a0, a0, 819
1558; RV32-NEXT:    sw a0, 12(sp)
1559; RV32-NEXT:    sw a0, 8(sp)
1560; RV32-NEXT:    lui a0, 61681
1561; RV32-NEXT:    addi a0, a0, -241
1562; RV32-NEXT:    sw a0, 12(sp)
1563; RV32-NEXT:    sw a0, 8(sp)
1564; RV32-NEXT:    lui a0, 4112
1565; RV32-NEXT:    addi a0, a0, 257
1566; RV32-NEXT:    sw a0, 12(sp)
1567; RV32-NEXT:    sw a0, 8(sp)
1568; RV32-NEXT:    li a0, 1
1569; RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
1570; RV32-NEXT:    vsub.vx v10, v8, a0
1571; RV32-NEXT:    vxor.vi v8, v8, -1
1572; RV32-NEXT:    addi a0, sp, 8
1573; RV32-NEXT:    vlse64.v v12, (a0), zero
1574; RV32-NEXT:    vand.vv v8, v8, v10
1575; RV32-NEXT:    addi a0, sp, 8
1576; RV32-NEXT:    vlse64.v v10, (a0), zero
1577; RV32-NEXT:    vsrl.vi v14, v8, 1
1578; RV32-NEXT:    vand.vv v12, v14, v12
1579; RV32-NEXT:    vsub.vv v8, v8, v12
1580; RV32-NEXT:    vand.vv v12, v8, v10
1581; RV32-NEXT:    vsrl.vi v8, v8, 2
1582; RV32-NEXT:    vand.vv v8, v8, v10
1583; RV32-NEXT:    vadd.vv v8, v12, v8
1584; RV32-NEXT:    addi a0, sp, 8
1585; RV32-NEXT:    vlse64.v v10, (a0), zero
1586; RV32-NEXT:    addi a0, sp, 8
1587; RV32-NEXT:    vlse64.v v12, (a0), zero
1588; RV32-NEXT:    vsrl.vi v14, v8, 4
1589; RV32-NEXT:    vadd.vv v8, v8, v14
1590; RV32-NEXT:    vand.vv v8, v8, v10
1591; RV32-NEXT:    vmul.vv v8, v8, v12
1592; RV32-NEXT:    li a0, 56
1593; RV32-NEXT:    vsrl.vx v8, v8, a0
1594; RV32-NEXT:    addi sp, sp, 16
1595; RV32-NEXT:    ret
1596;
1597; RV64-LABEL: cttz_nxv2i64:
1598; RV64:       # %bb.0:
1599; RV64-NEXT:    li a0, 1
1600; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
1601; RV64-NEXT:    vsub.vx v10, v8, a0
1602; RV64-NEXT:    vxor.vi v8, v8, -1
1603; RV64-NEXT:    vand.vv v8, v8, v10
1604; RV64-NEXT:    lui a0, %hi(.LCPI19_0)
1605; RV64-NEXT:    ld a0, %lo(.LCPI19_0)(a0)
1606; RV64-NEXT:    lui a1, %hi(.LCPI19_1)
1607; RV64-NEXT:    ld a1, %lo(.LCPI19_1)(a1)
1608; RV64-NEXT:    vsrl.vi v10, v8, 1
1609; RV64-NEXT:    vand.vx v10, v10, a0
1610; RV64-NEXT:    vsub.vv v8, v8, v10
1611; RV64-NEXT:    vand.vx v10, v8, a1
1612; RV64-NEXT:    vsrl.vi v8, v8, 2
1613; RV64-NEXT:    vand.vx v8, v8, a1
1614; RV64-NEXT:    vadd.vv v8, v10, v8
1615; RV64-NEXT:    lui a0, %hi(.LCPI19_2)
1616; RV64-NEXT:    ld a0, %lo(.LCPI19_2)(a0)
1617; RV64-NEXT:    lui a1, %hi(.LCPI19_3)
1618; RV64-NEXT:    ld a1, %lo(.LCPI19_3)(a1)
1619; RV64-NEXT:    vsrl.vi v10, v8, 4
1620; RV64-NEXT:    vadd.vv v8, v8, v10
1621; RV64-NEXT:    vand.vx v8, v8, a0
1622; RV64-NEXT:    vmul.vx v8, v8, a1
1623; RV64-NEXT:    li a0, 56
1624; RV64-NEXT:    vsrl.vx v8, v8, a0
1625; RV64-NEXT:    ret
1626  %a = call <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 false)
1627  ret <vscale x 2 x i64> %a
1628}
1629declare <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64>, i1)
1630
1631define <vscale x 4 x i64> @cttz_nxv4i64(<vscale x 4 x i64> %va) {
1632; RV32-LABEL: cttz_nxv4i64:
1633; RV32:       # %bb.0:
1634; RV32-NEXT:    addi sp, sp, -16
1635; RV32-NEXT:    .cfi_def_cfa_offset 16
1636; RV32-NEXT:    lui a0, 349525
1637; RV32-NEXT:    addi a0, a0, 1365
1638; RV32-NEXT:    sw a0, 12(sp)
1639; RV32-NEXT:    sw a0, 8(sp)
1640; RV32-NEXT:    lui a0, 209715
1641; RV32-NEXT:    addi a0, a0, 819
1642; RV32-NEXT:    sw a0, 12(sp)
1643; RV32-NEXT:    sw a0, 8(sp)
1644; RV32-NEXT:    lui a0, 61681
1645; RV32-NEXT:    addi a0, a0, -241
1646; RV32-NEXT:    sw a0, 12(sp)
1647; RV32-NEXT:    sw a0, 8(sp)
1648; RV32-NEXT:    lui a0, 4112
1649; RV32-NEXT:    addi a0, a0, 257
1650; RV32-NEXT:    sw a0, 12(sp)
1651; RV32-NEXT:    sw a0, 8(sp)
1652; RV32-NEXT:    li a0, 1
1653; RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1654; RV32-NEXT:    vsub.vx v12, v8, a0
1655; RV32-NEXT:    vxor.vi v8, v8, -1
1656; RV32-NEXT:    addi a0, sp, 8
1657; RV32-NEXT:    vlse64.v v16, (a0), zero
1658; RV32-NEXT:    vand.vv v8, v8, v12
1659; RV32-NEXT:    addi a0, sp, 8
1660; RV32-NEXT:    vlse64.v v12, (a0), zero
1661; RV32-NEXT:    vsrl.vi v20, v8, 1
1662; RV32-NEXT:    vand.vv v16, v20, v16
1663; RV32-NEXT:    vsub.vv v8, v8, v16
1664; RV32-NEXT:    vand.vv v16, v8, v12
1665; RV32-NEXT:    vsrl.vi v8, v8, 2
1666; RV32-NEXT:    vand.vv v8, v8, v12
1667; RV32-NEXT:    vadd.vv v8, v16, v8
1668; RV32-NEXT:    addi a0, sp, 8
1669; RV32-NEXT:    vlse64.v v12, (a0), zero
1670; RV32-NEXT:    addi a0, sp, 8
1671; RV32-NEXT:    vlse64.v v16, (a0), zero
1672; RV32-NEXT:    vsrl.vi v20, v8, 4
1673; RV32-NEXT:    vadd.vv v8, v8, v20
1674; RV32-NEXT:    vand.vv v8, v8, v12
1675; RV32-NEXT:    vmul.vv v8, v8, v16
1676; RV32-NEXT:    li a0, 56
1677; RV32-NEXT:    vsrl.vx v8, v8, a0
1678; RV32-NEXT:    addi sp, sp, 16
1679; RV32-NEXT:    ret
1680;
1681; RV64-LABEL: cttz_nxv4i64:
1682; RV64:       # %bb.0:
1683; RV64-NEXT:    li a0, 1
1684; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
1685; RV64-NEXT:    vsub.vx v12, v8, a0
1686; RV64-NEXT:    vxor.vi v8, v8, -1
1687; RV64-NEXT:    vand.vv v8, v8, v12
1688; RV64-NEXT:    lui a0, %hi(.LCPI20_0)
1689; RV64-NEXT:    ld a0, %lo(.LCPI20_0)(a0)
1690; RV64-NEXT:    lui a1, %hi(.LCPI20_1)
1691; RV64-NEXT:    ld a1, %lo(.LCPI20_1)(a1)
1692; RV64-NEXT:    vsrl.vi v12, v8, 1
1693; RV64-NEXT:    vand.vx v12, v12, a0
1694; RV64-NEXT:    vsub.vv v8, v8, v12
1695; RV64-NEXT:    vand.vx v12, v8, a1
1696; RV64-NEXT:    vsrl.vi v8, v8, 2
1697; RV64-NEXT:    vand.vx v8, v8, a1
1698; RV64-NEXT:    vadd.vv v8, v12, v8
1699; RV64-NEXT:    lui a0, %hi(.LCPI20_2)
1700; RV64-NEXT:    ld a0, %lo(.LCPI20_2)(a0)
1701; RV64-NEXT:    lui a1, %hi(.LCPI20_3)
1702; RV64-NEXT:    ld a1, %lo(.LCPI20_3)(a1)
1703; RV64-NEXT:    vsrl.vi v12, v8, 4
1704; RV64-NEXT:    vadd.vv v8, v8, v12
1705; RV64-NEXT:    vand.vx v8, v8, a0
1706; RV64-NEXT:    vmul.vx v8, v8, a1
1707; RV64-NEXT:    li a0, 56
1708; RV64-NEXT:    vsrl.vx v8, v8, a0
1709; RV64-NEXT:    ret
1710  %a = call <vscale x 4 x i64> @llvm.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 false)
1711  ret <vscale x 4 x i64> %a
1712}
1713declare <vscale x 4 x i64> @llvm.cttz.nxv4i64(<vscale x 4 x i64>, i1)
1714
1715define <vscale x 8 x i64> @cttz_nxv8i64(<vscale x 8 x i64> %va) {
1716; RV32-LABEL: cttz_nxv8i64:
1717; RV32:       # %bb.0:
1718; RV32-NEXT:    addi sp, sp, -16
1719; RV32-NEXT:    .cfi_def_cfa_offset 16
1720; RV32-NEXT:    lui a0, 349525
1721; RV32-NEXT:    addi a0, a0, 1365
1722; RV32-NEXT:    sw a0, 12(sp)
1723; RV32-NEXT:    sw a0, 8(sp)
1724; RV32-NEXT:    lui a0, 209715
1725; RV32-NEXT:    addi a0, a0, 819
1726; RV32-NEXT:    sw a0, 12(sp)
1727; RV32-NEXT:    sw a0, 8(sp)
1728; RV32-NEXT:    lui a0, 61681
1729; RV32-NEXT:    addi a0, a0, -241
1730; RV32-NEXT:    sw a0, 12(sp)
1731; RV32-NEXT:    sw a0, 8(sp)
1732; RV32-NEXT:    lui a0, 4112
1733; RV32-NEXT:    addi a0, a0, 257
1734; RV32-NEXT:    sw a0, 12(sp)
1735; RV32-NEXT:    sw a0, 8(sp)
1736; RV32-NEXT:    li a0, 1
1737; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1738; RV32-NEXT:    vsub.vx v16, v8, a0
1739; RV32-NEXT:    vxor.vi v8, v8, -1
1740; RV32-NEXT:    addi a0, sp, 8
1741; RV32-NEXT:    vlse64.v v24, (a0), zero
1742; RV32-NEXT:    vand.vv v8, v8, v16
1743; RV32-NEXT:    addi a0, sp, 8
1744; RV32-NEXT:    vlse64.v v16, (a0), zero
1745; RV32-NEXT:    vsrl.vi v0, v8, 1
1746; RV32-NEXT:    vand.vv v24, v0, v24
1747; RV32-NEXT:    vsub.vv v8, v8, v24
1748; RV32-NEXT:    vand.vv v24, v8, v16
1749; RV32-NEXT:    vsrl.vi v8, v8, 2
1750; RV32-NEXT:    vand.vv v8, v8, v16
1751; RV32-NEXT:    vadd.vv v8, v24, v8
1752; RV32-NEXT:    addi a0, sp, 8
1753; RV32-NEXT:    vlse64.v v16, (a0), zero
1754; RV32-NEXT:    addi a0, sp, 8
1755; RV32-NEXT:    vlse64.v v24, (a0), zero
1756; RV32-NEXT:    vsrl.vi v0, v8, 4
1757; RV32-NEXT:    vadd.vv v8, v8, v0
1758; RV32-NEXT:    vand.vv v8, v8, v16
1759; RV32-NEXT:    vmul.vv v8, v8, v24
1760; RV32-NEXT:    li a0, 56
1761; RV32-NEXT:    vsrl.vx v8, v8, a0
1762; RV32-NEXT:    addi sp, sp, 16
1763; RV32-NEXT:    ret
1764;
1765; RV64-LABEL: cttz_nxv8i64:
1766; RV64:       # %bb.0:
1767; RV64-NEXT:    li a0, 1
1768; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
1769; RV64-NEXT:    vsub.vx v16, v8, a0
1770; RV64-NEXT:    vxor.vi v8, v8, -1
1771; RV64-NEXT:    vand.vv v8, v8, v16
1772; RV64-NEXT:    lui a0, %hi(.LCPI21_0)
1773; RV64-NEXT:    ld a0, %lo(.LCPI21_0)(a0)
1774; RV64-NEXT:    lui a1, %hi(.LCPI21_1)
1775; RV64-NEXT:    ld a1, %lo(.LCPI21_1)(a1)
1776; RV64-NEXT:    vsrl.vi v16, v8, 1
1777; RV64-NEXT:    vand.vx v16, v16, a0
1778; RV64-NEXT:    vsub.vv v8, v8, v16
1779; RV64-NEXT:    vand.vx v16, v8, a1
1780; RV64-NEXT:    vsrl.vi v8, v8, 2
1781; RV64-NEXT:    vand.vx v8, v8, a1
1782; RV64-NEXT:    vadd.vv v8, v16, v8
1783; RV64-NEXT:    lui a0, %hi(.LCPI21_2)
1784; RV64-NEXT:    ld a0, %lo(.LCPI21_2)(a0)
1785; RV64-NEXT:    lui a1, %hi(.LCPI21_3)
1786; RV64-NEXT:    ld a1, %lo(.LCPI21_3)(a1)
1787; RV64-NEXT:    vsrl.vi v16, v8, 4
1788; RV64-NEXT:    vadd.vv v8, v8, v16
1789; RV64-NEXT:    vand.vx v8, v8, a0
1790; RV64-NEXT:    vmul.vx v8, v8, a1
1791; RV64-NEXT:    li a0, 56
1792; RV64-NEXT:    vsrl.vx v8, v8, a0
1793; RV64-NEXT:    ret
1794  %a = call <vscale x 8 x i64> @llvm.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 false)
1795  ret <vscale x 8 x i64> %a
1796}
1797declare <vscale x 8 x i64> @llvm.cttz.nxv8i64(<vscale x 8 x i64>, i1)
1798
1799define <vscale x 1 x i8> @cttz_zero_undef_nxv1i8(<vscale x 1 x i8> %va) {
1800; RV32I-LABEL: cttz_zero_undef_nxv1i8:
1801; RV32I:       # %bb.0:
1802; RV32I-NEXT:    li a0, 1
1803; RV32I-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
1804; RV32I-NEXT:    vsub.vx v9, v8, a0
1805; RV32I-NEXT:    vxor.vi v8, v8, -1
1806; RV32I-NEXT:    vand.vv v8, v8, v9
1807; RV32I-NEXT:    vsrl.vi v9, v8, 1
1808; RV32I-NEXT:    li a0, 85
1809; RV32I-NEXT:    vand.vx v9, v9, a0
1810; RV32I-NEXT:    vsub.vv v8, v8, v9
1811; RV32I-NEXT:    li a0, 51
1812; RV32I-NEXT:    vand.vx v9, v8, a0
1813; RV32I-NEXT:    vsrl.vi v8, v8, 2
1814; RV32I-NEXT:    vand.vx v8, v8, a0
1815; RV32I-NEXT:    vadd.vv v8, v9, v8
1816; RV32I-NEXT:    vsrl.vi v9, v8, 4
1817; RV32I-NEXT:    vadd.vv v8, v8, v9
1818; RV32I-NEXT:    vand.vi v8, v8, 15
1819; RV32I-NEXT:    ret
1820;
1821; RV64I-LABEL: cttz_zero_undef_nxv1i8:
1822; RV64I:       # %bb.0:
1823; RV64I-NEXT:    li a0, 1
1824; RV64I-NEXT:    vsetvli a1, zero, e8, mf8, ta, mu
1825; RV64I-NEXT:    vsub.vx v9, v8, a0
1826; RV64I-NEXT:    vxor.vi v8, v8, -1
1827; RV64I-NEXT:    vand.vv v8, v8, v9
1828; RV64I-NEXT:    vsrl.vi v9, v8, 1
1829; RV64I-NEXT:    li a0, 85
1830; RV64I-NEXT:    vand.vx v9, v9, a0
1831; RV64I-NEXT:    vsub.vv v8, v8, v9
1832; RV64I-NEXT:    li a0, 51
1833; RV64I-NEXT:    vand.vx v9, v8, a0
1834; RV64I-NEXT:    vsrl.vi v8, v8, 2
1835; RV64I-NEXT:    vand.vx v8, v8, a0
1836; RV64I-NEXT:    vadd.vv v8, v9, v8
1837; RV64I-NEXT:    vsrl.vi v9, v8, 4
1838; RV64I-NEXT:    vadd.vv v8, v8, v9
1839; RV64I-NEXT:    vand.vi v8, v8, 15
1840; RV64I-NEXT:    ret
1841;
1842; RV32D-LABEL: cttz_zero_undef_nxv1i8:
1843; RV32D:       # %bb.0:
1844; RV32D-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
1845; RV32D-NEXT:    vrsub.vi v9, v8, 0
1846; RV32D-NEXT:    vand.vv v8, v8, v9
1847; RV32D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
1848; RV32D-NEXT:    vzext.vf4 v9, v8
1849; RV32D-NEXT:    vfcvt.f.xu.v v8, v9
1850; RV32D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
1851; RV32D-NEXT:    vnsrl.wi v8, v8, 23
1852; RV32D-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
1853; RV32D-NEXT:    vnsrl.wx v8, v8, zero
1854; RV32D-NEXT:    li a0, 127
1855; RV32D-NEXT:    vsub.vx v8, v8, a0
1856; RV32D-NEXT:    ret
1857;
1858; RV64D-LABEL: cttz_zero_undef_nxv1i8:
1859; RV64D:       # %bb.0:
1860; RV64D-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
1861; RV64D-NEXT:    vrsub.vi v9, v8, 0
1862; RV64D-NEXT:    vand.vv v8, v8, v9
1863; RV64D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
1864; RV64D-NEXT:    vzext.vf4 v9, v8
1865; RV64D-NEXT:    vfcvt.f.xu.v v8, v9
1866; RV64D-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
1867; RV64D-NEXT:    vnsrl.wi v8, v8, 23
1868; RV64D-NEXT:    vsetvli zero, zero, e8, mf8, ta, mu
1869; RV64D-NEXT:    vnsrl.wx v8, v8, zero
1870; RV64D-NEXT:    li a0, 127
1871; RV64D-NEXT:    vsub.vx v8, v8, a0
1872; RV64D-NEXT:    ret
1873  %a = call <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 true)
1874  ret <vscale x 1 x i8> %a
1875}
1876
1877define <vscale x 2 x i8> @cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va) {
1878; RV32I-LABEL: cttz_zero_undef_nxv2i8:
1879; RV32I:       # %bb.0:
1880; RV32I-NEXT:    li a0, 1
1881; RV32I-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
1882; RV32I-NEXT:    vsub.vx v9, v8, a0
1883; RV32I-NEXT:    vxor.vi v8, v8, -1
1884; RV32I-NEXT:    vand.vv v8, v8, v9
1885; RV32I-NEXT:    vsrl.vi v9, v8, 1
1886; RV32I-NEXT:    li a0, 85
1887; RV32I-NEXT:    vand.vx v9, v9, a0
1888; RV32I-NEXT:    vsub.vv v8, v8, v9
1889; RV32I-NEXT:    li a0, 51
1890; RV32I-NEXT:    vand.vx v9, v8, a0
1891; RV32I-NEXT:    vsrl.vi v8, v8, 2
1892; RV32I-NEXT:    vand.vx v8, v8, a0
1893; RV32I-NEXT:    vadd.vv v8, v9, v8
1894; RV32I-NEXT:    vsrl.vi v9, v8, 4
1895; RV32I-NEXT:    vadd.vv v8, v8, v9
1896; RV32I-NEXT:    vand.vi v8, v8, 15
1897; RV32I-NEXT:    ret
1898;
1899; RV64I-LABEL: cttz_zero_undef_nxv2i8:
1900; RV64I:       # %bb.0:
1901; RV64I-NEXT:    li a0, 1
1902; RV64I-NEXT:    vsetvli a1, zero, e8, mf4, ta, mu
1903; RV64I-NEXT:    vsub.vx v9, v8, a0
1904; RV64I-NEXT:    vxor.vi v8, v8, -1
1905; RV64I-NEXT:    vand.vv v8, v8, v9
1906; RV64I-NEXT:    vsrl.vi v9, v8, 1
1907; RV64I-NEXT:    li a0, 85
1908; RV64I-NEXT:    vand.vx v9, v9, a0
1909; RV64I-NEXT:    vsub.vv v8, v8, v9
1910; RV64I-NEXT:    li a0, 51
1911; RV64I-NEXT:    vand.vx v9, v8, a0
1912; RV64I-NEXT:    vsrl.vi v8, v8, 2
1913; RV64I-NEXT:    vand.vx v8, v8, a0
1914; RV64I-NEXT:    vadd.vv v8, v9, v8
1915; RV64I-NEXT:    vsrl.vi v9, v8, 4
1916; RV64I-NEXT:    vadd.vv v8, v8, v9
1917; RV64I-NEXT:    vand.vi v8, v8, 15
1918; RV64I-NEXT:    ret
1919;
1920; RV32D-LABEL: cttz_zero_undef_nxv2i8:
1921; RV32D:       # %bb.0:
1922; RV32D-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
1923; RV32D-NEXT:    vrsub.vi v9, v8, 0
1924; RV32D-NEXT:    vand.vv v8, v8, v9
1925; RV32D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
1926; RV32D-NEXT:    vzext.vf4 v9, v8
1927; RV32D-NEXT:    vfcvt.f.xu.v v8, v9
1928; RV32D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
1929; RV32D-NEXT:    vnsrl.wi v8, v8, 23
1930; RV32D-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
1931; RV32D-NEXT:    vnsrl.wx v8, v8, zero
1932; RV32D-NEXT:    li a0, 127
1933; RV32D-NEXT:    vsub.vx v8, v8, a0
1934; RV32D-NEXT:    ret
1935;
1936; RV64D-LABEL: cttz_zero_undef_nxv2i8:
1937; RV64D:       # %bb.0:
1938; RV64D-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
1939; RV64D-NEXT:    vrsub.vi v9, v8, 0
1940; RV64D-NEXT:    vand.vv v8, v8, v9
1941; RV64D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
1942; RV64D-NEXT:    vzext.vf4 v9, v8
1943; RV64D-NEXT:    vfcvt.f.xu.v v8, v9
1944; RV64D-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
1945; RV64D-NEXT:    vnsrl.wi v8, v8, 23
1946; RV64D-NEXT:    vsetvli zero, zero, e8, mf4, ta, mu
1947; RV64D-NEXT:    vnsrl.wx v8, v8, zero
1948; RV64D-NEXT:    li a0, 127
1949; RV64D-NEXT:    vsub.vx v8, v8, a0
1950; RV64D-NEXT:    ret
1951  %a = call <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 true)
1952  ret <vscale x 2 x i8> %a
1953}
1954
1955define <vscale x 4 x i8> @cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va) {
1956; RV32I-LABEL: cttz_zero_undef_nxv4i8:
1957; RV32I:       # %bb.0:
1958; RV32I-NEXT:    li a0, 1
1959; RV32I-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
1960; RV32I-NEXT:    vsub.vx v9, v8, a0
1961; RV32I-NEXT:    vxor.vi v8, v8, -1
1962; RV32I-NEXT:    vand.vv v8, v8, v9
1963; RV32I-NEXT:    vsrl.vi v9, v8, 1
1964; RV32I-NEXT:    li a0, 85
1965; RV32I-NEXT:    vand.vx v9, v9, a0
1966; RV32I-NEXT:    vsub.vv v8, v8, v9
1967; RV32I-NEXT:    li a0, 51
1968; RV32I-NEXT:    vand.vx v9, v8, a0
1969; RV32I-NEXT:    vsrl.vi v8, v8, 2
1970; RV32I-NEXT:    vand.vx v8, v8, a0
1971; RV32I-NEXT:    vadd.vv v8, v9, v8
1972; RV32I-NEXT:    vsrl.vi v9, v8, 4
1973; RV32I-NEXT:    vadd.vv v8, v8, v9
1974; RV32I-NEXT:    vand.vi v8, v8, 15
1975; RV32I-NEXT:    ret
1976;
1977; RV64I-LABEL: cttz_zero_undef_nxv4i8:
1978; RV64I:       # %bb.0:
1979; RV64I-NEXT:    li a0, 1
1980; RV64I-NEXT:    vsetvli a1, zero, e8, mf2, ta, mu
1981; RV64I-NEXT:    vsub.vx v9, v8, a0
1982; RV64I-NEXT:    vxor.vi v8, v8, -1
1983; RV64I-NEXT:    vand.vv v8, v8, v9
1984; RV64I-NEXT:    vsrl.vi v9, v8, 1
1985; RV64I-NEXT:    li a0, 85
1986; RV64I-NEXT:    vand.vx v9, v9, a0
1987; RV64I-NEXT:    vsub.vv v8, v8, v9
1988; RV64I-NEXT:    li a0, 51
1989; RV64I-NEXT:    vand.vx v9, v8, a0
1990; RV64I-NEXT:    vsrl.vi v8, v8, 2
1991; RV64I-NEXT:    vand.vx v8, v8, a0
1992; RV64I-NEXT:    vadd.vv v8, v9, v8
1993; RV64I-NEXT:    vsrl.vi v9, v8, 4
1994; RV64I-NEXT:    vadd.vv v8, v8, v9
1995; RV64I-NEXT:    vand.vi v8, v8, 15
1996; RV64I-NEXT:    ret
1997;
1998; RV32D-LABEL: cttz_zero_undef_nxv4i8:
1999; RV32D:       # %bb.0:
2000; RV32D-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
2001; RV32D-NEXT:    vrsub.vi v9, v8, 0
2002; RV32D-NEXT:    vand.vv v8, v8, v9
2003; RV32D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
2004; RV32D-NEXT:    vzext.vf4 v10, v8
2005; RV32D-NEXT:    vfcvt.f.xu.v v8, v10
2006; RV32D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
2007; RV32D-NEXT:    vnsrl.wi v10, v8, 23
2008; RV32D-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
2009; RV32D-NEXT:    vnsrl.wx v8, v10, zero
2010; RV32D-NEXT:    li a0, 127
2011; RV32D-NEXT:    vsub.vx v8, v8, a0
2012; RV32D-NEXT:    ret
2013;
2014; RV64D-LABEL: cttz_zero_undef_nxv4i8:
2015; RV64D:       # %bb.0:
2016; RV64D-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
2017; RV64D-NEXT:    vrsub.vi v9, v8, 0
2018; RV64D-NEXT:    vand.vv v8, v8, v9
2019; RV64D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
2020; RV64D-NEXT:    vzext.vf4 v10, v8
2021; RV64D-NEXT:    vfcvt.f.xu.v v8, v10
2022; RV64D-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
2023; RV64D-NEXT:    vnsrl.wi v10, v8, 23
2024; RV64D-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
2025; RV64D-NEXT:    vnsrl.wx v8, v10, zero
2026; RV64D-NEXT:    li a0, 127
2027; RV64D-NEXT:    vsub.vx v8, v8, a0
2028; RV64D-NEXT:    ret
2029  %a = call <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 true)
2030  ret <vscale x 4 x i8> %a
2031}
2032
2033define <vscale x 8 x i8> @cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va) {
2034; RV32I-LABEL: cttz_zero_undef_nxv8i8:
2035; RV32I:       # %bb.0:
2036; RV32I-NEXT:    li a0, 1
2037; RV32I-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
2038; RV32I-NEXT:    vsub.vx v9, v8, a0
2039; RV32I-NEXT:    vxor.vi v8, v8, -1
2040; RV32I-NEXT:    vand.vv v8, v8, v9
2041; RV32I-NEXT:    vsrl.vi v9, v8, 1
2042; RV32I-NEXT:    li a0, 85
2043; RV32I-NEXT:    vand.vx v9, v9, a0
2044; RV32I-NEXT:    vsub.vv v8, v8, v9
2045; RV32I-NEXT:    li a0, 51
2046; RV32I-NEXT:    vand.vx v9, v8, a0
2047; RV32I-NEXT:    vsrl.vi v8, v8, 2
2048; RV32I-NEXT:    vand.vx v8, v8, a0
2049; RV32I-NEXT:    vadd.vv v8, v9, v8
2050; RV32I-NEXT:    vsrl.vi v9, v8, 4
2051; RV32I-NEXT:    vadd.vv v8, v8, v9
2052; RV32I-NEXT:    vand.vi v8, v8, 15
2053; RV32I-NEXT:    ret
2054;
2055; RV64I-LABEL: cttz_zero_undef_nxv8i8:
2056; RV64I:       # %bb.0:
2057; RV64I-NEXT:    li a0, 1
2058; RV64I-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
2059; RV64I-NEXT:    vsub.vx v9, v8, a0
2060; RV64I-NEXT:    vxor.vi v8, v8, -1
2061; RV64I-NEXT:    vand.vv v8, v8, v9
2062; RV64I-NEXT:    vsrl.vi v9, v8, 1
2063; RV64I-NEXT:    li a0, 85
2064; RV64I-NEXT:    vand.vx v9, v9, a0
2065; RV64I-NEXT:    vsub.vv v8, v8, v9
2066; RV64I-NEXT:    li a0, 51
2067; RV64I-NEXT:    vand.vx v9, v8, a0
2068; RV64I-NEXT:    vsrl.vi v8, v8, 2
2069; RV64I-NEXT:    vand.vx v8, v8, a0
2070; RV64I-NEXT:    vadd.vv v8, v9, v8
2071; RV64I-NEXT:    vsrl.vi v9, v8, 4
2072; RV64I-NEXT:    vadd.vv v8, v8, v9
2073; RV64I-NEXT:    vand.vi v8, v8, 15
2074; RV64I-NEXT:    ret
2075;
2076; RV32D-LABEL: cttz_zero_undef_nxv8i8:
2077; RV32D:       # %bb.0:
2078; RV32D-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
2079; RV32D-NEXT:    vrsub.vi v9, v8, 0
2080; RV32D-NEXT:    vand.vv v8, v8, v9
2081; RV32D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
2082; RV32D-NEXT:    vzext.vf4 v12, v8
2083; RV32D-NEXT:    vfcvt.f.xu.v v8, v12
2084; RV32D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
2085; RV32D-NEXT:    vnsrl.wi v12, v8, 23
2086; RV32D-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
2087; RV32D-NEXT:    vnsrl.wx v8, v12, zero
2088; RV32D-NEXT:    li a0, 127
2089; RV32D-NEXT:    vsub.vx v8, v8, a0
2090; RV32D-NEXT:    ret
2091;
2092; RV64D-LABEL: cttz_zero_undef_nxv8i8:
2093; RV64D:       # %bb.0:
2094; RV64D-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
2095; RV64D-NEXT:    vrsub.vi v9, v8, 0
2096; RV64D-NEXT:    vand.vv v8, v8, v9
2097; RV64D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
2098; RV64D-NEXT:    vzext.vf4 v12, v8
2099; RV64D-NEXT:    vfcvt.f.xu.v v8, v12
2100; RV64D-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
2101; RV64D-NEXT:    vnsrl.wi v12, v8, 23
2102; RV64D-NEXT:    vsetvli zero, zero, e8, m1, ta, mu
2103; RV64D-NEXT:    vnsrl.wx v8, v12, zero
2104; RV64D-NEXT:    li a0, 127
2105; RV64D-NEXT:    vsub.vx v8, v8, a0
2106; RV64D-NEXT:    ret
2107  %a = call <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 true)
2108  ret <vscale x 8 x i8> %a
2109}
2110
2111define <vscale x 16 x i8> @cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) {
2112; RV32I-LABEL: cttz_zero_undef_nxv16i8:
2113; RV32I:       # %bb.0:
2114; RV32I-NEXT:    li a0, 1
2115; RV32I-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
2116; RV32I-NEXT:    vsub.vx v10, v8, a0
2117; RV32I-NEXT:    vxor.vi v8, v8, -1
2118; RV32I-NEXT:    vand.vv v8, v8, v10
2119; RV32I-NEXT:    vsrl.vi v10, v8, 1
2120; RV32I-NEXT:    li a0, 85
2121; RV32I-NEXT:    vand.vx v10, v10, a0
2122; RV32I-NEXT:    vsub.vv v8, v8, v10
2123; RV32I-NEXT:    li a0, 51
2124; RV32I-NEXT:    vand.vx v10, v8, a0
2125; RV32I-NEXT:    vsrl.vi v8, v8, 2
2126; RV32I-NEXT:    vand.vx v8, v8, a0
2127; RV32I-NEXT:    vadd.vv v8, v10, v8
2128; RV32I-NEXT:    vsrl.vi v10, v8, 4
2129; RV32I-NEXT:    vadd.vv v8, v8, v10
2130; RV32I-NEXT:    vand.vi v8, v8, 15
2131; RV32I-NEXT:    ret
2132;
2133; RV64I-LABEL: cttz_zero_undef_nxv16i8:
2134; RV64I:       # %bb.0:
2135; RV64I-NEXT:    li a0, 1
2136; RV64I-NEXT:    vsetvli a1, zero, e8, m2, ta, mu
2137; RV64I-NEXT:    vsub.vx v10, v8, a0
2138; RV64I-NEXT:    vxor.vi v8, v8, -1
2139; RV64I-NEXT:    vand.vv v8, v8, v10
2140; RV64I-NEXT:    vsrl.vi v10, v8, 1
2141; RV64I-NEXT:    li a0, 85
2142; RV64I-NEXT:    vand.vx v10, v10, a0
2143; RV64I-NEXT:    vsub.vv v8, v8, v10
2144; RV64I-NEXT:    li a0, 51
2145; RV64I-NEXT:    vand.vx v10, v8, a0
2146; RV64I-NEXT:    vsrl.vi v8, v8, 2
2147; RV64I-NEXT:    vand.vx v8, v8, a0
2148; RV64I-NEXT:    vadd.vv v8, v10, v8
2149; RV64I-NEXT:    vsrl.vi v10, v8, 4
2150; RV64I-NEXT:    vadd.vv v8, v8, v10
2151; RV64I-NEXT:    vand.vi v8, v8, 15
2152; RV64I-NEXT:    ret
2153;
2154; RV32D-LABEL: cttz_zero_undef_nxv16i8:
2155; RV32D:       # %bb.0:
2156; RV32D-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
2157; RV32D-NEXT:    vrsub.vi v10, v8, 0
2158; RV32D-NEXT:    vand.vv v8, v8, v10
2159; RV32D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
2160; RV32D-NEXT:    vzext.vf4 v16, v8
2161; RV32D-NEXT:    vfcvt.f.xu.v v8, v16
2162; RV32D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
2163; RV32D-NEXT:    vnsrl.wi v16, v8, 23
2164; RV32D-NEXT:    vsetvli zero, zero, e8, m2, ta, mu
2165; RV32D-NEXT:    vnsrl.wx v8, v16, zero
2166; RV32D-NEXT:    li a0, 127
2167; RV32D-NEXT:    vsub.vx v8, v8, a0
2168; RV32D-NEXT:    ret
2169;
2170; RV64D-LABEL: cttz_zero_undef_nxv16i8:
2171; RV64D:       # %bb.0:
2172; RV64D-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
2173; RV64D-NEXT:    vrsub.vi v10, v8, 0
2174; RV64D-NEXT:    vand.vv v8, v8, v10
2175; RV64D-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
2176; RV64D-NEXT:    vzext.vf4 v16, v8
2177; RV64D-NEXT:    vfcvt.f.xu.v v8, v16
2178; RV64D-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
2179; RV64D-NEXT:    vnsrl.wi v16, v8, 23
2180; RV64D-NEXT:    vsetvli zero, zero, e8, m2, ta, mu
2181; RV64D-NEXT:    vnsrl.wx v8, v16, zero
2182; RV64D-NEXT:    li a0, 127
2183; RV64D-NEXT:    vsub.vx v8, v8, a0
2184; RV64D-NEXT:    ret
2185  %a = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 true)
2186  ret <vscale x 16 x i8> %a
2187}
2188
2189define <vscale x 32 x i8> @cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va) {
2190; CHECK-LABEL: cttz_zero_undef_nxv32i8:
2191; CHECK:       # %bb.0:
2192; CHECK-NEXT:    li a0, 1
2193; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, mu
2194; CHECK-NEXT:    vsub.vx v12, v8, a0
2195; CHECK-NEXT:    vxor.vi v8, v8, -1
2196; CHECK-NEXT:    vand.vv v8, v8, v12
2197; CHECK-NEXT:    vsrl.vi v12, v8, 1
2198; CHECK-NEXT:    li a0, 85
2199; CHECK-NEXT:    vand.vx v12, v12, a0
2200; CHECK-NEXT:    vsub.vv v8, v8, v12
2201; CHECK-NEXT:    li a0, 51
2202; CHECK-NEXT:    vand.vx v12, v8, a0
2203; CHECK-NEXT:    vsrl.vi v8, v8, 2
2204; CHECK-NEXT:    vand.vx v8, v8, a0
2205; CHECK-NEXT:    vadd.vv v8, v12, v8
2206; CHECK-NEXT:    vsrl.vi v12, v8, 4
2207; CHECK-NEXT:    vadd.vv v8, v8, v12
2208; CHECK-NEXT:    vand.vi v8, v8, 15
2209; CHECK-NEXT:    ret
2210  %a = call <vscale x 32 x i8> @llvm.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 true)
2211  ret <vscale x 32 x i8> %a
2212}
2213
2214define <vscale x 64 x i8> @cttz_zero_undef_nxv64i8(<vscale x 64 x i8> %va) {
2215; CHECK-LABEL: cttz_zero_undef_nxv64i8:
2216; CHECK:       # %bb.0:
2217; CHECK-NEXT:    li a0, 1
2218; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, mu
2219; CHECK-NEXT:    vsub.vx v16, v8, a0
2220; CHECK-NEXT:    vxor.vi v8, v8, -1
2221; CHECK-NEXT:    vand.vv v8, v8, v16
2222; CHECK-NEXT:    vsrl.vi v16, v8, 1
2223; CHECK-NEXT:    li a0, 85
2224; CHECK-NEXT:    vand.vx v16, v16, a0
2225; CHECK-NEXT:    vsub.vv v8, v8, v16
2226; CHECK-NEXT:    li a0, 51
2227; CHECK-NEXT:    vand.vx v16, v8, a0
2228; CHECK-NEXT:    vsrl.vi v8, v8, 2
2229; CHECK-NEXT:    vand.vx v8, v8, a0
2230; CHECK-NEXT:    vadd.vv v8, v16, v8
2231; CHECK-NEXT:    vsrl.vi v16, v8, 4
2232; CHECK-NEXT:    vadd.vv v8, v8, v16
2233; CHECK-NEXT:    vand.vi v8, v8, 15
2234; CHECK-NEXT:    ret
2235  %a = call <vscale x 64 x i8> @llvm.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 true)
2236  ret <vscale x 64 x i8> %a
2237}
2238
2239define <vscale x 1 x i16> @cttz_zero_undef_nxv1i16(<vscale x 1 x i16> %va) {
2240; RV32I-LABEL: cttz_zero_undef_nxv1i16:
2241; RV32I:       # %bb.0:
2242; RV32I-NEXT:    li a0, 1
2243; RV32I-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
2244; RV32I-NEXT:    vsub.vx v9, v8, a0
2245; RV32I-NEXT:    vxor.vi v8, v8, -1
2246; RV32I-NEXT:    vand.vv v8, v8, v9
2247; RV32I-NEXT:    vsrl.vi v9, v8, 1
2248; RV32I-NEXT:    lui a0, 5
2249; RV32I-NEXT:    addi a0, a0, 1365
2250; RV32I-NEXT:    vand.vx v9, v9, a0
2251; RV32I-NEXT:    vsub.vv v8, v8, v9
2252; RV32I-NEXT:    lui a0, 3
2253; RV32I-NEXT:    addi a0, a0, 819
2254; RV32I-NEXT:    vand.vx v9, v8, a0
2255; RV32I-NEXT:    vsrl.vi v8, v8, 2
2256; RV32I-NEXT:    vand.vx v8, v8, a0
2257; RV32I-NEXT:    vadd.vv v8, v9, v8
2258; RV32I-NEXT:    vsrl.vi v9, v8, 4
2259; RV32I-NEXT:    vadd.vv v8, v8, v9
2260; RV32I-NEXT:    lui a0, 1
2261; RV32I-NEXT:    addi a0, a0, -241
2262; RV32I-NEXT:    vand.vx v8, v8, a0
2263; RV32I-NEXT:    li a0, 257
2264; RV32I-NEXT:    vmul.vx v8, v8, a0
2265; RV32I-NEXT:    vsrl.vi v8, v8, 8
2266; RV32I-NEXT:    ret
2267;
2268; RV64I-LABEL: cttz_zero_undef_nxv1i16:
2269; RV64I:       # %bb.0:
2270; RV64I-NEXT:    li a0, 1
2271; RV64I-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
2272; RV64I-NEXT:    vsub.vx v9, v8, a0
2273; RV64I-NEXT:    vxor.vi v8, v8, -1
2274; RV64I-NEXT:    vand.vv v8, v8, v9
2275; RV64I-NEXT:    vsrl.vi v9, v8, 1
2276; RV64I-NEXT:    lui a0, 5
2277; RV64I-NEXT:    addiw a0, a0, 1365
2278; RV64I-NEXT:    vand.vx v9, v9, a0
2279; RV64I-NEXT:    vsub.vv v8, v8, v9
2280; RV64I-NEXT:    lui a0, 3
2281; RV64I-NEXT:    addiw a0, a0, 819
2282; RV64I-NEXT:    vand.vx v9, v8, a0
2283; RV64I-NEXT:    vsrl.vi v8, v8, 2
2284; RV64I-NEXT:    vand.vx v8, v8, a0
2285; RV64I-NEXT:    vadd.vv v8, v9, v8
2286; RV64I-NEXT:    vsrl.vi v9, v8, 4
2287; RV64I-NEXT:    vadd.vv v8, v8, v9
2288; RV64I-NEXT:    lui a0, 1
2289; RV64I-NEXT:    addiw a0, a0, -241
2290; RV64I-NEXT:    vand.vx v8, v8, a0
2291; RV64I-NEXT:    li a0, 257
2292; RV64I-NEXT:    vmul.vx v8, v8, a0
2293; RV64I-NEXT:    vsrl.vi v8, v8, 8
2294; RV64I-NEXT:    ret
2295;
2296; RV32D-LABEL: cttz_zero_undef_nxv1i16:
2297; RV32D:       # %bb.0:
2298; RV32D-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
2299; RV32D-NEXT:    vrsub.vi v9, v8, 0
2300; RV32D-NEXT:    vand.vv v8, v8, v9
2301; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
2302; RV32D-NEXT:    vnsrl.wi v8, v9, 23
2303; RV32D-NEXT:    li a0, 127
2304; RV32D-NEXT:    vsub.vx v8, v8, a0
2305; RV32D-NEXT:    ret
2306;
2307; RV64D-LABEL: cttz_zero_undef_nxv1i16:
2308; RV64D:       # %bb.0:
2309; RV64D-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
2310; RV64D-NEXT:    vrsub.vi v9, v8, 0
2311; RV64D-NEXT:    vand.vv v8, v8, v9
2312; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
2313; RV64D-NEXT:    vnsrl.wi v8, v9, 23
2314; RV64D-NEXT:    li a0, 127
2315; RV64D-NEXT:    vsub.vx v8, v8, a0
2316; RV64D-NEXT:    ret
2317  %a = call <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 true)
2318  ret <vscale x 1 x i16> %a
2319}
2320
2321define <vscale x 2 x i16> @cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) {
2322; RV32I-LABEL: cttz_zero_undef_nxv2i16:
2323; RV32I:       # %bb.0:
2324; RV32I-NEXT:    li a0, 1
2325; RV32I-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
2326; RV32I-NEXT:    vsub.vx v9, v8, a0
2327; RV32I-NEXT:    vxor.vi v8, v8, -1
2328; RV32I-NEXT:    vand.vv v8, v8, v9
2329; RV32I-NEXT:    vsrl.vi v9, v8, 1
2330; RV32I-NEXT:    lui a0, 5
2331; RV32I-NEXT:    addi a0, a0, 1365
2332; RV32I-NEXT:    vand.vx v9, v9, a0
2333; RV32I-NEXT:    vsub.vv v8, v8, v9
2334; RV32I-NEXT:    lui a0, 3
2335; RV32I-NEXT:    addi a0, a0, 819
2336; RV32I-NEXT:    vand.vx v9, v8, a0
2337; RV32I-NEXT:    vsrl.vi v8, v8, 2
2338; RV32I-NEXT:    vand.vx v8, v8, a0
2339; RV32I-NEXT:    vadd.vv v8, v9, v8
2340; RV32I-NEXT:    vsrl.vi v9, v8, 4
2341; RV32I-NEXT:    vadd.vv v8, v8, v9
2342; RV32I-NEXT:    lui a0, 1
2343; RV32I-NEXT:    addi a0, a0, -241
2344; RV32I-NEXT:    vand.vx v8, v8, a0
2345; RV32I-NEXT:    li a0, 257
2346; RV32I-NEXT:    vmul.vx v8, v8, a0
2347; RV32I-NEXT:    vsrl.vi v8, v8, 8
2348; RV32I-NEXT:    ret
2349;
2350; RV64I-LABEL: cttz_zero_undef_nxv2i16:
2351; RV64I:       # %bb.0:
2352; RV64I-NEXT:    li a0, 1
2353; RV64I-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
2354; RV64I-NEXT:    vsub.vx v9, v8, a0
2355; RV64I-NEXT:    vxor.vi v8, v8, -1
2356; RV64I-NEXT:    vand.vv v8, v8, v9
2357; RV64I-NEXT:    vsrl.vi v9, v8, 1
2358; RV64I-NEXT:    lui a0, 5
2359; RV64I-NEXT:    addiw a0, a0, 1365
2360; RV64I-NEXT:    vand.vx v9, v9, a0
2361; RV64I-NEXT:    vsub.vv v8, v8, v9
2362; RV64I-NEXT:    lui a0, 3
2363; RV64I-NEXT:    addiw a0, a0, 819
2364; RV64I-NEXT:    vand.vx v9, v8, a0
2365; RV64I-NEXT:    vsrl.vi v8, v8, 2
2366; RV64I-NEXT:    vand.vx v8, v8, a0
2367; RV64I-NEXT:    vadd.vv v8, v9, v8
2368; RV64I-NEXT:    vsrl.vi v9, v8, 4
2369; RV64I-NEXT:    vadd.vv v8, v8, v9
2370; RV64I-NEXT:    lui a0, 1
2371; RV64I-NEXT:    addiw a0, a0, -241
2372; RV64I-NEXT:    vand.vx v8, v8, a0
2373; RV64I-NEXT:    li a0, 257
2374; RV64I-NEXT:    vmul.vx v8, v8, a0
2375; RV64I-NEXT:    vsrl.vi v8, v8, 8
2376; RV64I-NEXT:    ret
2377;
2378; RV32D-LABEL: cttz_zero_undef_nxv2i16:
2379; RV32D:       # %bb.0:
2380; RV32D-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
2381; RV32D-NEXT:    vrsub.vi v9, v8, 0
2382; RV32D-NEXT:    vand.vv v8, v8, v9
2383; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
2384; RV32D-NEXT:    vnsrl.wi v8, v9, 23
2385; RV32D-NEXT:    li a0, 127
2386; RV32D-NEXT:    vsub.vx v8, v8, a0
2387; RV32D-NEXT:    ret
2388;
2389; RV64D-LABEL: cttz_zero_undef_nxv2i16:
2390; RV64D:       # %bb.0:
2391; RV64D-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
2392; RV64D-NEXT:    vrsub.vi v9, v8, 0
2393; RV64D-NEXT:    vand.vv v8, v8, v9
2394; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
2395; RV64D-NEXT:    vnsrl.wi v8, v9, 23
2396; RV64D-NEXT:    li a0, 127
2397; RV64D-NEXT:    vsub.vx v8, v8, a0
2398; RV64D-NEXT:    ret
2399  %a = call <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 true)
2400  ret <vscale x 2 x i16> %a
2401}
2402
2403define <vscale x 4 x i16> @cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) {
2404; RV32I-LABEL: cttz_zero_undef_nxv4i16:
2405; RV32I:       # %bb.0:
2406; RV32I-NEXT:    li a0, 1
2407; RV32I-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
2408; RV32I-NEXT:    vsub.vx v9, v8, a0
2409; RV32I-NEXT:    vxor.vi v8, v8, -1
2410; RV32I-NEXT:    vand.vv v8, v8, v9
2411; RV32I-NEXT:    vsrl.vi v9, v8, 1
2412; RV32I-NEXT:    lui a0, 5
2413; RV32I-NEXT:    addi a0, a0, 1365
2414; RV32I-NEXT:    vand.vx v9, v9, a0
2415; RV32I-NEXT:    vsub.vv v8, v8, v9
2416; RV32I-NEXT:    lui a0, 3
2417; RV32I-NEXT:    addi a0, a0, 819
2418; RV32I-NEXT:    vand.vx v9, v8, a0
2419; RV32I-NEXT:    vsrl.vi v8, v8, 2
2420; RV32I-NEXT:    vand.vx v8, v8, a0
2421; RV32I-NEXT:    vadd.vv v8, v9, v8
2422; RV32I-NEXT:    vsrl.vi v9, v8, 4
2423; RV32I-NEXT:    vadd.vv v8, v8, v9
2424; RV32I-NEXT:    lui a0, 1
2425; RV32I-NEXT:    addi a0, a0, -241
2426; RV32I-NEXT:    vand.vx v8, v8, a0
2427; RV32I-NEXT:    li a0, 257
2428; RV32I-NEXT:    vmul.vx v8, v8, a0
2429; RV32I-NEXT:    vsrl.vi v8, v8, 8
2430; RV32I-NEXT:    ret
2431;
2432; RV64I-LABEL: cttz_zero_undef_nxv4i16:
2433; RV64I:       # %bb.0:
2434; RV64I-NEXT:    li a0, 1
2435; RV64I-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
2436; RV64I-NEXT:    vsub.vx v9, v8, a0
2437; RV64I-NEXT:    vxor.vi v8, v8, -1
2438; RV64I-NEXT:    vand.vv v8, v8, v9
2439; RV64I-NEXT:    vsrl.vi v9, v8, 1
2440; RV64I-NEXT:    lui a0, 5
2441; RV64I-NEXT:    addiw a0, a0, 1365
2442; RV64I-NEXT:    vand.vx v9, v9, a0
2443; RV64I-NEXT:    vsub.vv v8, v8, v9
2444; RV64I-NEXT:    lui a0, 3
2445; RV64I-NEXT:    addiw a0, a0, 819
2446; RV64I-NEXT:    vand.vx v9, v8, a0
2447; RV64I-NEXT:    vsrl.vi v8, v8, 2
2448; RV64I-NEXT:    vand.vx v8, v8, a0
2449; RV64I-NEXT:    vadd.vv v8, v9, v8
2450; RV64I-NEXT:    vsrl.vi v9, v8, 4
2451; RV64I-NEXT:    vadd.vv v8, v8, v9
2452; RV64I-NEXT:    lui a0, 1
2453; RV64I-NEXT:    addiw a0, a0, -241
2454; RV64I-NEXT:    vand.vx v8, v8, a0
2455; RV64I-NEXT:    li a0, 257
2456; RV64I-NEXT:    vmul.vx v8, v8, a0
2457; RV64I-NEXT:    vsrl.vi v8, v8, 8
2458; RV64I-NEXT:    ret
2459;
2460; RV32D-LABEL: cttz_zero_undef_nxv4i16:
2461; RV32D:       # %bb.0:
2462; RV32D-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
2463; RV32D-NEXT:    vrsub.vi v9, v8, 0
2464; RV32D-NEXT:    vand.vv v8, v8, v9
2465; RV32D-NEXT:    vfwcvt.f.xu.v v10, v8
2466; RV32D-NEXT:    vnsrl.wi v8, v10, 23
2467; RV32D-NEXT:    li a0, 127
2468; RV32D-NEXT:    vsub.vx v8, v8, a0
2469; RV32D-NEXT:    ret
2470;
2471; RV64D-LABEL: cttz_zero_undef_nxv4i16:
2472; RV64D:       # %bb.0:
2473; RV64D-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
2474; RV64D-NEXT:    vrsub.vi v9, v8, 0
2475; RV64D-NEXT:    vand.vv v8, v8, v9
2476; RV64D-NEXT:    vfwcvt.f.xu.v v10, v8
2477; RV64D-NEXT:    vnsrl.wi v8, v10, 23
2478; RV64D-NEXT:    li a0, 127
2479; RV64D-NEXT:    vsub.vx v8, v8, a0
2480; RV64D-NEXT:    ret
2481  %a = call <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 true)
2482  ret <vscale x 4 x i16> %a
2483}
2484
2485define <vscale x 8 x i16> @cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
2486; RV32I-LABEL: cttz_zero_undef_nxv8i16:
2487; RV32I:       # %bb.0:
2488; RV32I-NEXT:    li a0, 1
2489; RV32I-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
2490; RV32I-NEXT:    vsub.vx v10, v8, a0
2491; RV32I-NEXT:    vxor.vi v8, v8, -1
2492; RV32I-NEXT:    vand.vv v8, v8, v10
2493; RV32I-NEXT:    vsrl.vi v10, v8, 1
2494; RV32I-NEXT:    lui a0, 5
2495; RV32I-NEXT:    addi a0, a0, 1365
2496; RV32I-NEXT:    vand.vx v10, v10, a0
2497; RV32I-NEXT:    vsub.vv v8, v8, v10
2498; RV32I-NEXT:    lui a0, 3
2499; RV32I-NEXT:    addi a0, a0, 819
2500; RV32I-NEXT:    vand.vx v10, v8, a0
2501; RV32I-NEXT:    vsrl.vi v8, v8, 2
2502; RV32I-NEXT:    vand.vx v8, v8, a0
2503; RV32I-NEXT:    vadd.vv v8, v10, v8
2504; RV32I-NEXT:    vsrl.vi v10, v8, 4
2505; RV32I-NEXT:    vadd.vv v8, v8, v10
2506; RV32I-NEXT:    lui a0, 1
2507; RV32I-NEXT:    addi a0, a0, -241
2508; RV32I-NEXT:    vand.vx v8, v8, a0
2509; RV32I-NEXT:    li a0, 257
2510; RV32I-NEXT:    vmul.vx v8, v8, a0
2511; RV32I-NEXT:    vsrl.vi v8, v8, 8
2512; RV32I-NEXT:    ret
2513;
2514; RV64I-LABEL: cttz_zero_undef_nxv8i16:
2515; RV64I:       # %bb.0:
2516; RV64I-NEXT:    li a0, 1
2517; RV64I-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
2518; RV64I-NEXT:    vsub.vx v10, v8, a0
2519; RV64I-NEXT:    vxor.vi v8, v8, -1
2520; RV64I-NEXT:    vand.vv v8, v8, v10
2521; RV64I-NEXT:    vsrl.vi v10, v8, 1
2522; RV64I-NEXT:    lui a0, 5
2523; RV64I-NEXT:    addiw a0, a0, 1365
2524; RV64I-NEXT:    vand.vx v10, v10, a0
2525; RV64I-NEXT:    vsub.vv v8, v8, v10
2526; RV64I-NEXT:    lui a0, 3
2527; RV64I-NEXT:    addiw a0, a0, 819
2528; RV64I-NEXT:    vand.vx v10, v8, a0
2529; RV64I-NEXT:    vsrl.vi v8, v8, 2
2530; RV64I-NEXT:    vand.vx v8, v8, a0
2531; RV64I-NEXT:    vadd.vv v8, v10, v8
2532; RV64I-NEXT:    vsrl.vi v10, v8, 4
2533; RV64I-NEXT:    vadd.vv v8, v8, v10
2534; RV64I-NEXT:    lui a0, 1
2535; RV64I-NEXT:    addiw a0, a0, -241
2536; RV64I-NEXT:    vand.vx v8, v8, a0
2537; RV64I-NEXT:    li a0, 257
2538; RV64I-NEXT:    vmul.vx v8, v8, a0
2539; RV64I-NEXT:    vsrl.vi v8, v8, 8
2540; RV64I-NEXT:    ret
2541;
2542; RV32D-LABEL: cttz_zero_undef_nxv8i16:
2543; RV32D:       # %bb.0:
2544; RV32D-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
2545; RV32D-NEXT:    vrsub.vi v10, v8, 0
2546; RV32D-NEXT:    vand.vv v8, v8, v10
2547; RV32D-NEXT:    vfwcvt.f.xu.v v12, v8
2548; RV32D-NEXT:    vnsrl.wi v8, v12, 23
2549; RV32D-NEXT:    li a0, 127
2550; RV32D-NEXT:    vsub.vx v8, v8, a0
2551; RV32D-NEXT:    ret
2552;
2553; RV64D-LABEL: cttz_zero_undef_nxv8i16:
2554; RV64D:       # %bb.0:
2555; RV64D-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
2556; RV64D-NEXT:    vrsub.vi v10, v8, 0
2557; RV64D-NEXT:    vand.vv v8, v8, v10
2558; RV64D-NEXT:    vfwcvt.f.xu.v v12, v8
2559; RV64D-NEXT:    vnsrl.wi v8, v12, 23
2560; RV64D-NEXT:    li a0, 127
2561; RV64D-NEXT:    vsub.vx v8, v8, a0
2562; RV64D-NEXT:    ret
2563  %a = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 true)
2564  ret <vscale x 8 x i16> %a
2565}
2566
2567define <vscale x 16 x i16> @cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
2568; RV32I-LABEL: cttz_zero_undef_nxv16i16:
2569; RV32I:       # %bb.0:
2570; RV32I-NEXT:    li a0, 1
2571; RV32I-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
2572; RV32I-NEXT:    vsub.vx v12, v8, a0
2573; RV32I-NEXT:    vxor.vi v8, v8, -1
2574; RV32I-NEXT:    vand.vv v8, v8, v12
2575; RV32I-NEXT:    vsrl.vi v12, v8, 1
2576; RV32I-NEXT:    lui a0, 5
2577; RV32I-NEXT:    addi a0, a0, 1365
2578; RV32I-NEXT:    vand.vx v12, v12, a0
2579; RV32I-NEXT:    vsub.vv v8, v8, v12
2580; RV32I-NEXT:    lui a0, 3
2581; RV32I-NEXT:    addi a0, a0, 819
2582; RV32I-NEXT:    vand.vx v12, v8, a0
2583; RV32I-NEXT:    vsrl.vi v8, v8, 2
2584; RV32I-NEXT:    vand.vx v8, v8, a0
2585; RV32I-NEXT:    vadd.vv v8, v12, v8
2586; RV32I-NEXT:    vsrl.vi v12, v8, 4
2587; RV32I-NEXT:    vadd.vv v8, v8, v12
2588; RV32I-NEXT:    lui a0, 1
2589; RV32I-NEXT:    addi a0, a0, -241
2590; RV32I-NEXT:    vand.vx v8, v8, a0
2591; RV32I-NEXT:    li a0, 257
2592; RV32I-NEXT:    vmul.vx v8, v8, a0
2593; RV32I-NEXT:    vsrl.vi v8, v8, 8
2594; RV32I-NEXT:    ret
2595;
2596; RV64I-LABEL: cttz_zero_undef_nxv16i16:
2597; RV64I:       # %bb.0:
2598; RV64I-NEXT:    li a0, 1
2599; RV64I-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
2600; RV64I-NEXT:    vsub.vx v12, v8, a0
2601; RV64I-NEXT:    vxor.vi v8, v8, -1
2602; RV64I-NEXT:    vand.vv v8, v8, v12
2603; RV64I-NEXT:    vsrl.vi v12, v8, 1
2604; RV64I-NEXT:    lui a0, 5
2605; RV64I-NEXT:    addiw a0, a0, 1365
2606; RV64I-NEXT:    vand.vx v12, v12, a0
2607; RV64I-NEXT:    vsub.vv v8, v8, v12
2608; RV64I-NEXT:    lui a0, 3
2609; RV64I-NEXT:    addiw a0, a0, 819
2610; RV64I-NEXT:    vand.vx v12, v8, a0
2611; RV64I-NEXT:    vsrl.vi v8, v8, 2
2612; RV64I-NEXT:    vand.vx v8, v8, a0
2613; RV64I-NEXT:    vadd.vv v8, v12, v8
2614; RV64I-NEXT:    vsrl.vi v12, v8, 4
2615; RV64I-NEXT:    vadd.vv v8, v8, v12
2616; RV64I-NEXT:    lui a0, 1
2617; RV64I-NEXT:    addiw a0, a0, -241
2618; RV64I-NEXT:    vand.vx v8, v8, a0
2619; RV64I-NEXT:    li a0, 257
2620; RV64I-NEXT:    vmul.vx v8, v8, a0
2621; RV64I-NEXT:    vsrl.vi v8, v8, 8
2622; RV64I-NEXT:    ret
2623;
2624; RV32D-LABEL: cttz_zero_undef_nxv16i16:
2625; RV32D:       # %bb.0:
2626; RV32D-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
2627; RV32D-NEXT:    vrsub.vi v12, v8, 0
2628; RV32D-NEXT:    vand.vv v8, v8, v12
2629; RV32D-NEXT:    vfwcvt.f.xu.v v16, v8
2630; RV32D-NEXT:    vnsrl.wi v8, v16, 23
2631; RV32D-NEXT:    li a0, 127
2632; RV32D-NEXT:    vsub.vx v8, v8, a0
2633; RV32D-NEXT:    ret
2634;
2635; RV64D-LABEL: cttz_zero_undef_nxv16i16:
2636; RV64D:       # %bb.0:
2637; RV64D-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
2638; RV64D-NEXT:    vrsub.vi v12, v8, 0
2639; RV64D-NEXT:    vand.vv v8, v8, v12
2640; RV64D-NEXT:    vfwcvt.f.xu.v v16, v8
2641; RV64D-NEXT:    vnsrl.wi v8, v16, 23
2642; RV64D-NEXT:    li a0, 127
2643; RV64D-NEXT:    vsub.vx v8, v8, a0
2644; RV64D-NEXT:    ret
2645  %a = call <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 true)
2646  ret <vscale x 16 x i16> %a
2647}
2648
2649define <vscale x 32 x i16> @cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va) {
2650; RV32-LABEL: cttz_zero_undef_nxv32i16:
2651; RV32:       # %bb.0:
2652; RV32-NEXT:    li a0, 1
2653; RV32-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
2654; RV32-NEXT:    vsub.vx v16, v8, a0
2655; RV32-NEXT:    vxor.vi v8, v8, -1
2656; RV32-NEXT:    vand.vv v8, v8, v16
2657; RV32-NEXT:    vsrl.vi v16, v8, 1
2658; RV32-NEXT:    lui a0, 5
2659; RV32-NEXT:    addi a0, a0, 1365
2660; RV32-NEXT:    vand.vx v16, v16, a0
2661; RV32-NEXT:    vsub.vv v8, v8, v16
2662; RV32-NEXT:    lui a0, 3
2663; RV32-NEXT:    addi a0, a0, 819
2664; RV32-NEXT:    vand.vx v16, v8, a0
2665; RV32-NEXT:    vsrl.vi v8, v8, 2
2666; RV32-NEXT:    vand.vx v8, v8, a0
2667; RV32-NEXT:    vadd.vv v8, v16, v8
2668; RV32-NEXT:    vsrl.vi v16, v8, 4
2669; RV32-NEXT:    vadd.vv v8, v8, v16
2670; RV32-NEXT:    lui a0, 1
2671; RV32-NEXT:    addi a0, a0, -241
2672; RV32-NEXT:    vand.vx v8, v8, a0
2673; RV32-NEXT:    li a0, 257
2674; RV32-NEXT:    vmul.vx v8, v8, a0
2675; RV32-NEXT:    vsrl.vi v8, v8, 8
2676; RV32-NEXT:    ret
2677;
2678; RV64-LABEL: cttz_zero_undef_nxv32i16:
2679; RV64:       # %bb.0:
2680; RV64-NEXT:    li a0, 1
2681; RV64-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
2682; RV64-NEXT:    vsub.vx v16, v8, a0
2683; RV64-NEXT:    vxor.vi v8, v8, -1
2684; RV64-NEXT:    vand.vv v8, v8, v16
2685; RV64-NEXT:    vsrl.vi v16, v8, 1
2686; RV64-NEXT:    lui a0, 5
2687; RV64-NEXT:    addiw a0, a0, 1365
2688; RV64-NEXT:    vand.vx v16, v16, a0
2689; RV64-NEXT:    vsub.vv v8, v8, v16
2690; RV64-NEXT:    lui a0, 3
2691; RV64-NEXT:    addiw a0, a0, 819
2692; RV64-NEXT:    vand.vx v16, v8, a0
2693; RV64-NEXT:    vsrl.vi v8, v8, 2
2694; RV64-NEXT:    vand.vx v8, v8, a0
2695; RV64-NEXT:    vadd.vv v8, v16, v8
2696; RV64-NEXT:    vsrl.vi v16, v8, 4
2697; RV64-NEXT:    vadd.vv v8, v8, v16
2698; RV64-NEXT:    lui a0, 1
2699; RV64-NEXT:    addiw a0, a0, -241
2700; RV64-NEXT:    vand.vx v8, v8, a0
2701; RV64-NEXT:    li a0, 257
2702; RV64-NEXT:    vmul.vx v8, v8, a0
2703; RV64-NEXT:    vsrl.vi v8, v8, 8
2704; RV64-NEXT:    ret
2705  %a = call <vscale x 32 x i16> @llvm.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 true)
2706  ret <vscale x 32 x i16> %a
2707}
2708
2709define <vscale x 1 x i32> @cttz_zero_undef_nxv1i32(<vscale x 1 x i32> %va) {
2710; RV32I-LABEL: cttz_zero_undef_nxv1i32:
2711; RV32I:       # %bb.0:
2712; RV32I-NEXT:    li a0, 1
2713; RV32I-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
2714; RV32I-NEXT:    vsub.vx v9, v8, a0
2715; RV32I-NEXT:    vxor.vi v8, v8, -1
2716; RV32I-NEXT:    vand.vv v8, v8, v9
2717; RV32I-NEXT:    vsrl.vi v9, v8, 1
2718; RV32I-NEXT:    lui a0, 349525
2719; RV32I-NEXT:    addi a0, a0, 1365
2720; RV32I-NEXT:    vand.vx v9, v9, a0
2721; RV32I-NEXT:    vsub.vv v8, v8, v9
2722; RV32I-NEXT:    lui a0, 209715
2723; RV32I-NEXT:    addi a0, a0, 819
2724; RV32I-NEXT:    vand.vx v9, v8, a0
2725; RV32I-NEXT:    vsrl.vi v8, v8, 2
2726; RV32I-NEXT:    vand.vx v8, v8, a0
2727; RV32I-NEXT:    vadd.vv v8, v9, v8
2728; RV32I-NEXT:    vsrl.vi v9, v8, 4
2729; RV32I-NEXT:    vadd.vv v8, v8, v9
2730; RV32I-NEXT:    lui a0, 61681
2731; RV32I-NEXT:    addi a0, a0, -241
2732; RV32I-NEXT:    vand.vx v8, v8, a0
2733; RV32I-NEXT:    lui a0, 4112
2734; RV32I-NEXT:    addi a0, a0, 257
2735; RV32I-NEXT:    vmul.vx v8, v8, a0
2736; RV32I-NEXT:    vsrl.vi v8, v8, 24
2737; RV32I-NEXT:    ret
2738;
2739; RV64I-LABEL: cttz_zero_undef_nxv1i32:
2740; RV64I:       # %bb.0:
2741; RV64I-NEXT:    li a0, 1
2742; RV64I-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
2743; RV64I-NEXT:    vsub.vx v9, v8, a0
2744; RV64I-NEXT:    vxor.vi v8, v8, -1
2745; RV64I-NEXT:    vand.vv v8, v8, v9
2746; RV64I-NEXT:    vsrl.vi v9, v8, 1
2747; RV64I-NEXT:    lui a0, 349525
2748; RV64I-NEXT:    addiw a0, a0, 1365
2749; RV64I-NEXT:    vand.vx v9, v9, a0
2750; RV64I-NEXT:    vsub.vv v8, v8, v9
2751; RV64I-NEXT:    lui a0, 209715
2752; RV64I-NEXT:    addiw a0, a0, 819
2753; RV64I-NEXT:    vand.vx v9, v8, a0
2754; RV64I-NEXT:    vsrl.vi v8, v8, 2
2755; RV64I-NEXT:    vand.vx v8, v8, a0
2756; RV64I-NEXT:    vadd.vv v8, v9, v8
2757; RV64I-NEXT:    vsrl.vi v9, v8, 4
2758; RV64I-NEXT:    vadd.vv v8, v8, v9
2759; RV64I-NEXT:    lui a0, 61681
2760; RV64I-NEXT:    addiw a0, a0, -241
2761; RV64I-NEXT:    vand.vx v8, v8, a0
2762; RV64I-NEXT:    lui a0, 4112
2763; RV64I-NEXT:    addiw a0, a0, 257
2764; RV64I-NEXT:    vmul.vx v8, v8, a0
2765; RV64I-NEXT:    vsrl.vi v8, v8, 24
2766; RV64I-NEXT:    ret
2767;
2768; RV32D-LABEL: cttz_zero_undef_nxv1i32:
2769; RV32D:       # %bb.0:
2770; RV32D-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
2771; RV32D-NEXT:    vrsub.vi v9, v8, 0
2772; RV32D-NEXT:    vand.vv v8, v8, v9
2773; RV32D-NEXT:    vfwcvt.f.xu.v v9, v8
2774; RV32D-NEXT:    li a0, 52
2775; RV32D-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
2776; RV32D-NEXT:    vsrl.vx v8, v9, a0
2777; RV32D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
2778; RV32D-NEXT:    vnsrl.wx v8, v8, zero
2779; RV32D-NEXT:    li a0, 1023
2780; RV32D-NEXT:    vsub.vx v8, v8, a0
2781; RV32D-NEXT:    ret
2782;
2783; RV64D-LABEL: cttz_zero_undef_nxv1i32:
2784; RV64D:       # %bb.0:
2785; RV64D-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
2786; RV64D-NEXT:    vrsub.vi v9, v8, 0
2787; RV64D-NEXT:    vand.vv v8, v8, v9
2788; RV64D-NEXT:    vfwcvt.f.xu.v v9, v8
2789; RV64D-NEXT:    li a0, 52
2790; RV64D-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
2791; RV64D-NEXT:    vsrl.vx v8, v9, a0
2792; RV64D-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
2793; RV64D-NEXT:    vnsrl.wx v8, v8, zero
2794; RV64D-NEXT:    li a0, 1023
2795; RV64D-NEXT:    vsub.vx v8, v8, a0
2796; RV64D-NEXT:    ret
2797  %a = call <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 true)
2798  ret <vscale x 1 x i32> %a
2799}
2800
2801define <vscale x 2 x i32> @cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) {
2802; RV32I-LABEL: cttz_zero_undef_nxv2i32:
2803; RV32I:       # %bb.0:
2804; RV32I-NEXT:    li a0, 1
2805; RV32I-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
2806; RV32I-NEXT:    vsub.vx v9, v8, a0
2807; RV32I-NEXT:    vxor.vi v8, v8, -1
2808; RV32I-NEXT:    vand.vv v8, v8, v9
2809; RV32I-NEXT:    vsrl.vi v9, v8, 1
2810; RV32I-NEXT:    lui a0, 349525
2811; RV32I-NEXT:    addi a0, a0, 1365
2812; RV32I-NEXT:    vand.vx v9, v9, a0
2813; RV32I-NEXT:    vsub.vv v8, v8, v9
2814; RV32I-NEXT:    lui a0, 209715
2815; RV32I-NEXT:    addi a0, a0, 819
2816; RV32I-NEXT:    vand.vx v9, v8, a0
2817; RV32I-NEXT:    vsrl.vi v8, v8, 2
2818; RV32I-NEXT:    vand.vx v8, v8, a0
2819; RV32I-NEXT:    vadd.vv v8, v9, v8
2820; RV32I-NEXT:    vsrl.vi v9, v8, 4
2821; RV32I-NEXT:    vadd.vv v8, v8, v9
2822; RV32I-NEXT:    lui a0, 61681
2823; RV32I-NEXT:    addi a0, a0, -241
2824; RV32I-NEXT:    vand.vx v8, v8, a0
2825; RV32I-NEXT:    lui a0, 4112
2826; RV32I-NEXT:    addi a0, a0, 257
2827; RV32I-NEXT:    vmul.vx v8, v8, a0
2828; RV32I-NEXT:    vsrl.vi v8, v8, 24
2829; RV32I-NEXT:    ret
2830;
2831; RV64I-LABEL: cttz_zero_undef_nxv2i32:
2832; RV64I:       # %bb.0:
2833; RV64I-NEXT:    li a0, 1
2834; RV64I-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
2835; RV64I-NEXT:    vsub.vx v9, v8, a0
2836; RV64I-NEXT:    vxor.vi v8, v8, -1
2837; RV64I-NEXT:    vand.vv v8, v8, v9
2838; RV64I-NEXT:    vsrl.vi v9, v8, 1
2839; RV64I-NEXT:    lui a0, 349525
2840; RV64I-NEXT:    addiw a0, a0, 1365
2841; RV64I-NEXT:    vand.vx v9, v9, a0
2842; RV64I-NEXT:    vsub.vv v8, v8, v9
2843; RV64I-NEXT:    lui a0, 209715
2844; RV64I-NEXT:    addiw a0, a0, 819
2845; RV64I-NEXT:    vand.vx v9, v8, a0
2846; RV64I-NEXT:    vsrl.vi v8, v8, 2
2847; RV64I-NEXT:    vand.vx v8, v8, a0
2848; RV64I-NEXT:    vadd.vv v8, v9, v8
2849; RV64I-NEXT:    vsrl.vi v9, v8, 4
2850; RV64I-NEXT:    vadd.vv v8, v8, v9
2851; RV64I-NEXT:    lui a0, 61681
2852; RV64I-NEXT:    addiw a0, a0, -241
2853; RV64I-NEXT:    vand.vx v8, v8, a0
2854; RV64I-NEXT:    lui a0, 4112
2855; RV64I-NEXT:    addiw a0, a0, 257
2856; RV64I-NEXT:    vmul.vx v8, v8, a0
2857; RV64I-NEXT:    vsrl.vi v8, v8, 24
2858; RV64I-NEXT:    ret
2859;
2860; RV32D-LABEL: cttz_zero_undef_nxv2i32:
2861; RV32D:       # %bb.0:
2862; RV32D-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
2863; RV32D-NEXT:    vrsub.vi v9, v8, 0
2864; RV32D-NEXT:    vand.vv v8, v8, v9
2865; RV32D-NEXT:    vfwcvt.f.xu.v v10, v8
2866; RV32D-NEXT:    li a0, 52
2867; RV32D-NEXT:    vsetvli zero, zero, e64, m2, ta, mu
2868; RV32D-NEXT:    vsrl.vx v8, v10, a0
2869; RV32D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
2870; RV32D-NEXT:    vnsrl.wx v10, v8, zero
2871; RV32D-NEXT:    li a0, 1023
2872; RV32D-NEXT:    vsub.vx v8, v10, a0
2873; RV32D-NEXT:    ret
2874;
2875; RV64D-LABEL: cttz_zero_undef_nxv2i32:
2876; RV64D:       # %bb.0:
2877; RV64D-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
2878; RV64D-NEXT:    vrsub.vi v9, v8, 0
2879; RV64D-NEXT:    vand.vv v8, v8, v9
2880; RV64D-NEXT:    vfwcvt.f.xu.v v10, v8
2881; RV64D-NEXT:    li a0, 52
2882; RV64D-NEXT:    vsetvli zero, zero, e64, m2, ta, mu
2883; RV64D-NEXT:    vsrl.vx v8, v10, a0
2884; RV64D-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
2885; RV64D-NEXT:    vnsrl.wx v10, v8, zero
2886; RV64D-NEXT:    li a0, 1023
2887; RV64D-NEXT:    vsub.vx v8, v10, a0
2888; RV64D-NEXT:    ret
2889  %a = call <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 true)
2890  ret <vscale x 2 x i32> %a
2891}
2892
2893define <vscale x 4 x i32> @cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
2894; RV32I-LABEL: cttz_zero_undef_nxv4i32:
2895; RV32I:       # %bb.0:
2896; RV32I-NEXT:    li a0, 1
2897; RV32I-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
2898; RV32I-NEXT:    vsub.vx v10, v8, a0
2899; RV32I-NEXT:    vxor.vi v8, v8, -1
2900; RV32I-NEXT:    vand.vv v8, v8, v10
2901; RV32I-NEXT:    vsrl.vi v10, v8, 1
2902; RV32I-NEXT:    lui a0, 349525
2903; RV32I-NEXT:    addi a0, a0, 1365
2904; RV32I-NEXT:    vand.vx v10, v10, a0
2905; RV32I-NEXT:    vsub.vv v8, v8, v10
2906; RV32I-NEXT:    lui a0, 209715
2907; RV32I-NEXT:    addi a0, a0, 819
2908; RV32I-NEXT:    vand.vx v10, v8, a0
2909; RV32I-NEXT:    vsrl.vi v8, v8, 2
2910; RV32I-NEXT:    vand.vx v8, v8, a0
2911; RV32I-NEXT:    vadd.vv v8, v10, v8
2912; RV32I-NEXT:    vsrl.vi v10, v8, 4
2913; RV32I-NEXT:    vadd.vv v8, v8, v10
2914; RV32I-NEXT:    lui a0, 61681
2915; RV32I-NEXT:    addi a0, a0, -241
2916; RV32I-NEXT:    vand.vx v8, v8, a0
2917; RV32I-NEXT:    lui a0, 4112
2918; RV32I-NEXT:    addi a0, a0, 257
2919; RV32I-NEXT:    vmul.vx v8, v8, a0
2920; RV32I-NEXT:    vsrl.vi v8, v8, 24
2921; RV32I-NEXT:    ret
2922;
2923; RV64I-LABEL: cttz_zero_undef_nxv4i32:
2924; RV64I:       # %bb.0:
2925; RV64I-NEXT:    li a0, 1
2926; RV64I-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
2927; RV64I-NEXT:    vsub.vx v10, v8, a0
2928; RV64I-NEXT:    vxor.vi v8, v8, -1
2929; RV64I-NEXT:    vand.vv v8, v8, v10
2930; RV64I-NEXT:    vsrl.vi v10, v8, 1
2931; RV64I-NEXT:    lui a0, 349525
2932; RV64I-NEXT:    addiw a0, a0, 1365
2933; RV64I-NEXT:    vand.vx v10, v10, a0
2934; RV64I-NEXT:    vsub.vv v8, v8, v10
2935; RV64I-NEXT:    lui a0, 209715
2936; RV64I-NEXT:    addiw a0, a0, 819
2937; RV64I-NEXT:    vand.vx v10, v8, a0
2938; RV64I-NEXT:    vsrl.vi v8, v8, 2
2939; RV64I-NEXT:    vand.vx v8, v8, a0
2940; RV64I-NEXT:    vadd.vv v8, v10, v8
2941; RV64I-NEXT:    vsrl.vi v10, v8, 4
2942; RV64I-NEXT:    vadd.vv v8, v8, v10
2943; RV64I-NEXT:    lui a0, 61681
2944; RV64I-NEXT:    addiw a0, a0, -241
2945; RV64I-NEXT:    vand.vx v8, v8, a0
2946; RV64I-NEXT:    lui a0, 4112
2947; RV64I-NEXT:    addiw a0, a0, 257
2948; RV64I-NEXT:    vmul.vx v8, v8, a0
2949; RV64I-NEXT:    vsrl.vi v8, v8, 24
2950; RV64I-NEXT:    ret
2951;
2952; RV32D-LABEL: cttz_zero_undef_nxv4i32:
2953; RV32D:       # %bb.0:
2954; RV32D-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
2955; RV32D-NEXT:    vrsub.vi v10, v8, 0
2956; RV32D-NEXT:    vand.vv v8, v8, v10
2957; RV32D-NEXT:    vfwcvt.f.xu.v v12, v8
2958; RV32D-NEXT:    li a0, 52
2959; RV32D-NEXT:    vsetvli zero, zero, e64, m4, ta, mu
2960; RV32D-NEXT:    vsrl.vx v8, v12, a0
2961; RV32D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
2962; RV32D-NEXT:    vnsrl.wx v12, v8, zero
2963; RV32D-NEXT:    li a0, 1023
2964; RV32D-NEXT:    vsub.vx v8, v12, a0
2965; RV32D-NEXT:    ret
2966;
2967; RV64D-LABEL: cttz_zero_undef_nxv4i32:
2968; RV64D:       # %bb.0:
2969; RV64D-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
2970; RV64D-NEXT:    vrsub.vi v10, v8, 0
2971; RV64D-NEXT:    vand.vv v8, v8, v10
2972; RV64D-NEXT:    vfwcvt.f.xu.v v12, v8
2973; RV64D-NEXT:    li a0, 52
2974; RV64D-NEXT:    vsetvli zero, zero, e64, m4, ta, mu
2975; RV64D-NEXT:    vsrl.vx v8, v12, a0
2976; RV64D-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
2977; RV64D-NEXT:    vnsrl.wx v12, v8, zero
2978; RV64D-NEXT:    li a0, 1023
2979; RV64D-NEXT:    vsub.vx v8, v12, a0
2980; RV64D-NEXT:    ret
2981  %a = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 true)
2982  ret <vscale x 4 x i32> %a
2983}
2984
2985define <vscale x 8 x i32> @cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
2986; RV32I-LABEL: cttz_zero_undef_nxv8i32:
2987; RV32I:       # %bb.0:
2988; RV32I-NEXT:    li a0, 1
2989; RV32I-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
2990; RV32I-NEXT:    vsub.vx v12, v8, a0
2991; RV32I-NEXT:    vxor.vi v8, v8, -1
2992; RV32I-NEXT:    vand.vv v8, v8, v12
2993; RV32I-NEXT:    vsrl.vi v12, v8, 1
2994; RV32I-NEXT:    lui a0, 349525
2995; RV32I-NEXT:    addi a0, a0, 1365
2996; RV32I-NEXT:    vand.vx v12, v12, a0
2997; RV32I-NEXT:    vsub.vv v8, v8, v12
2998; RV32I-NEXT:    lui a0, 209715
2999; RV32I-NEXT:    addi a0, a0, 819
3000; RV32I-NEXT:    vand.vx v12, v8, a0
3001; RV32I-NEXT:    vsrl.vi v8, v8, 2
3002; RV32I-NEXT:    vand.vx v8, v8, a0
3003; RV32I-NEXT:    vadd.vv v8, v12, v8
3004; RV32I-NEXT:    vsrl.vi v12, v8, 4
3005; RV32I-NEXT:    vadd.vv v8, v8, v12
3006; RV32I-NEXT:    lui a0, 61681
3007; RV32I-NEXT:    addi a0, a0, -241
3008; RV32I-NEXT:    vand.vx v8, v8, a0
3009; RV32I-NEXT:    lui a0, 4112
3010; RV32I-NEXT:    addi a0, a0, 257
3011; RV32I-NEXT:    vmul.vx v8, v8, a0
3012; RV32I-NEXT:    vsrl.vi v8, v8, 24
3013; RV32I-NEXT:    ret
3014;
3015; RV64I-LABEL: cttz_zero_undef_nxv8i32:
3016; RV64I:       # %bb.0:
3017; RV64I-NEXT:    li a0, 1
3018; RV64I-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
3019; RV64I-NEXT:    vsub.vx v12, v8, a0
3020; RV64I-NEXT:    vxor.vi v8, v8, -1
3021; RV64I-NEXT:    vand.vv v8, v8, v12
3022; RV64I-NEXT:    vsrl.vi v12, v8, 1
3023; RV64I-NEXT:    lui a0, 349525
3024; RV64I-NEXT:    addiw a0, a0, 1365
3025; RV64I-NEXT:    vand.vx v12, v12, a0
3026; RV64I-NEXT:    vsub.vv v8, v8, v12
3027; RV64I-NEXT:    lui a0, 209715
3028; RV64I-NEXT:    addiw a0, a0, 819
3029; RV64I-NEXT:    vand.vx v12, v8, a0
3030; RV64I-NEXT:    vsrl.vi v8, v8, 2
3031; RV64I-NEXT:    vand.vx v8, v8, a0
3032; RV64I-NEXT:    vadd.vv v8, v12, v8
3033; RV64I-NEXT:    vsrl.vi v12, v8, 4
3034; RV64I-NEXT:    vadd.vv v8, v8, v12
3035; RV64I-NEXT:    lui a0, 61681
3036; RV64I-NEXT:    addiw a0, a0, -241
3037; RV64I-NEXT:    vand.vx v8, v8, a0
3038; RV64I-NEXT:    lui a0, 4112
3039; RV64I-NEXT:    addiw a0, a0, 257
3040; RV64I-NEXT:    vmul.vx v8, v8, a0
3041; RV64I-NEXT:    vsrl.vi v8, v8, 24
3042; RV64I-NEXT:    ret
3043;
3044; RV32D-LABEL: cttz_zero_undef_nxv8i32:
3045; RV32D:       # %bb.0:
3046; RV32D-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
3047; RV32D-NEXT:    vrsub.vi v12, v8, 0
3048; RV32D-NEXT:    vand.vv v8, v8, v12
3049; RV32D-NEXT:    vfwcvt.f.xu.v v16, v8
3050; RV32D-NEXT:    li a0, 52
3051; RV32D-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
3052; RV32D-NEXT:    vsrl.vx v8, v16, a0
3053; RV32D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
3054; RV32D-NEXT:    vnsrl.wx v16, v8, zero
3055; RV32D-NEXT:    li a0, 1023
3056; RV32D-NEXT:    vsub.vx v8, v16, a0
3057; RV32D-NEXT:    ret
3058;
3059; RV64D-LABEL: cttz_zero_undef_nxv8i32:
3060; RV64D:       # %bb.0:
3061; RV64D-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
3062; RV64D-NEXT:    vrsub.vi v12, v8, 0
3063; RV64D-NEXT:    vand.vv v8, v8, v12
3064; RV64D-NEXT:    vfwcvt.f.xu.v v16, v8
3065; RV64D-NEXT:    li a0, 52
3066; RV64D-NEXT:    vsetvli zero, zero, e64, m8, ta, mu
3067; RV64D-NEXT:    vsrl.vx v8, v16, a0
3068; RV64D-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
3069; RV64D-NEXT:    vnsrl.wx v16, v8, zero
3070; RV64D-NEXT:    li a0, 1023
3071; RV64D-NEXT:    vsub.vx v8, v16, a0
3072; RV64D-NEXT:    ret
3073  %a = call <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 true)
3074  ret <vscale x 8 x i32> %a
3075}
3076
3077define <vscale x 16 x i32> @cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) {
3078; RV32-LABEL: cttz_zero_undef_nxv16i32:
3079; RV32:       # %bb.0:
3080; RV32-NEXT:    li a0, 1
3081; RV32-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
3082; RV32-NEXT:    vsub.vx v16, v8, a0
3083; RV32-NEXT:    vxor.vi v8, v8, -1
3084; RV32-NEXT:    vand.vv v8, v8, v16
3085; RV32-NEXT:    vsrl.vi v16, v8, 1
3086; RV32-NEXT:    lui a0, 349525
3087; RV32-NEXT:    addi a0, a0, 1365
3088; RV32-NEXT:    vand.vx v16, v16, a0
3089; RV32-NEXT:    vsub.vv v8, v8, v16
3090; RV32-NEXT:    lui a0, 209715
3091; RV32-NEXT:    addi a0, a0, 819
3092; RV32-NEXT:    vand.vx v16, v8, a0
3093; RV32-NEXT:    vsrl.vi v8, v8, 2
3094; RV32-NEXT:    vand.vx v8, v8, a0
3095; RV32-NEXT:    vadd.vv v8, v16, v8
3096; RV32-NEXT:    vsrl.vi v16, v8, 4
3097; RV32-NEXT:    vadd.vv v8, v8, v16
3098; RV32-NEXT:    lui a0, 61681
3099; RV32-NEXT:    addi a0, a0, -241
3100; RV32-NEXT:    vand.vx v8, v8, a0
3101; RV32-NEXT:    lui a0, 4112
3102; RV32-NEXT:    addi a0, a0, 257
3103; RV32-NEXT:    vmul.vx v8, v8, a0
3104; RV32-NEXT:    vsrl.vi v8, v8, 24
3105; RV32-NEXT:    ret
3106;
3107; RV64-LABEL: cttz_zero_undef_nxv16i32:
3108; RV64:       # %bb.0:
3109; RV64-NEXT:    li a0, 1
3110; RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
3111; RV64-NEXT:    vsub.vx v16, v8, a0
3112; RV64-NEXT:    vxor.vi v8, v8, -1
3113; RV64-NEXT:    vand.vv v8, v8, v16
3114; RV64-NEXT:    vsrl.vi v16, v8, 1
3115; RV64-NEXT:    lui a0, 349525
3116; RV64-NEXT:    addiw a0, a0, 1365
3117; RV64-NEXT:    vand.vx v16, v16, a0
3118; RV64-NEXT:    vsub.vv v8, v8, v16
3119; RV64-NEXT:    lui a0, 209715
3120; RV64-NEXT:    addiw a0, a0, 819
3121; RV64-NEXT:    vand.vx v16, v8, a0
3122; RV64-NEXT:    vsrl.vi v8, v8, 2
3123; RV64-NEXT:    vand.vx v8, v8, a0
3124; RV64-NEXT:    vadd.vv v8, v16, v8
3125; RV64-NEXT:    vsrl.vi v16, v8, 4
3126; RV64-NEXT:    vadd.vv v8, v8, v16
3127; RV64-NEXT:    lui a0, 61681
3128; RV64-NEXT:    addiw a0, a0, -241
3129; RV64-NEXT:    vand.vx v8, v8, a0
3130; RV64-NEXT:    lui a0, 4112
3131; RV64-NEXT:    addiw a0, a0, 257
3132; RV64-NEXT:    vmul.vx v8, v8, a0
3133; RV64-NEXT:    vsrl.vi v8, v8, 24
3134; RV64-NEXT:    ret
3135  %a = call <vscale x 16 x i32> @llvm.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 true)
3136  ret <vscale x 16 x i32> %a
3137}
3138
3139define <vscale x 1 x i64> @cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
3140; RV32-LABEL: cttz_zero_undef_nxv1i64:
3141; RV32:       # %bb.0:
3142; RV32-NEXT:    addi sp, sp, -16
3143; RV32-NEXT:    .cfi_def_cfa_offset 16
3144; RV32-NEXT:    lui a0, 349525
3145; RV32-NEXT:    addi a0, a0, 1365
3146; RV32-NEXT:    sw a0, 12(sp)
3147; RV32-NEXT:    sw a0, 8(sp)
3148; RV32-NEXT:    lui a0, 209715
3149; RV32-NEXT:    addi a0, a0, 819
3150; RV32-NEXT:    sw a0, 12(sp)
3151; RV32-NEXT:    sw a0, 8(sp)
3152; RV32-NEXT:    lui a0, 61681
3153; RV32-NEXT:    addi a0, a0, -241
3154; RV32-NEXT:    sw a0, 12(sp)
3155; RV32-NEXT:    sw a0, 8(sp)
3156; RV32-NEXT:    lui a0, 4112
3157; RV32-NEXT:    addi a0, a0, 257
3158; RV32-NEXT:    sw a0, 12(sp)
3159; RV32-NEXT:    sw a0, 8(sp)
3160; RV32-NEXT:    li a0, 1
3161; RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
3162; RV32-NEXT:    vsub.vx v9, v8, a0
3163; RV32-NEXT:    vxor.vi v8, v8, -1
3164; RV32-NEXT:    addi a0, sp, 8
3165; RV32-NEXT:    vlse64.v v10, (a0), zero
3166; RV32-NEXT:    vand.vv v8, v8, v9
3167; RV32-NEXT:    addi a0, sp, 8
3168; RV32-NEXT:    vlse64.v v9, (a0), zero
3169; RV32-NEXT:    vsrl.vi v11, v8, 1
3170; RV32-NEXT:    vand.vv v10, v11, v10
3171; RV32-NEXT:    vsub.vv v8, v8, v10
3172; RV32-NEXT:    vand.vv v10, v8, v9
3173; RV32-NEXT:    vsrl.vi v8, v8, 2
3174; RV32-NEXT:    vand.vv v8, v8, v9
3175; RV32-NEXT:    vadd.vv v8, v10, v8
3176; RV32-NEXT:    addi a0, sp, 8
3177; RV32-NEXT:    vlse64.v v9, (a0), zero
3178; RV32-NEXT:    addi a0, sp, 8
3179; RV32-NEXT:    vlse64.v v10, (a0), zero
3180; RV32-NEXT:    vsrl.vi v11, v8, 4
3181; RV32-NEXT:    vadd.vv v8, v8, v11
3182; RV32-NEXT:    vand.vv v8, v8, v9
3183; RV32-NEXT:    vmul.vv v8, v8, v10
3184; RV32-NEXT:    li a0, 56
3185; RV32-NEXT:    vsrl.vx v8, v8, a0
3186; RV32-NEXT:    addi sp, sp, 16
3187; RV32-NEXT:    ret
3188;
3189; RV64-LABEL: cttz_zero_undef_nxv1i64:
3190; RV64:       # %bb.0:
3191; RV64-NEXT:    li a0, 1
3192; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
3193; RV64-NEXT:    vsub.vx v9, v8, a0
3194; RV64-NEXT:    vxor.vi v8, v8, -1
3195; RV64-NEXT:    vand.vv v8, v8, v9
3196; RV64-NEXT:    lui a0, %hi(.LCPI40_0)
3197; RV64-NEXT:    ld a0, %lo(.LCPI40_0)(a0)
3198; RV64-NEXT:    lui a1, %hi(.LCPI40_1)
3199; RV64-NEXT:    ld a1, %lo(.LCPI40_1)(a1)
3200; RV64-NEXT:    vsrl.vi v9, v8, 1
3201; RV64-NEXT:    vand.vx v9, v9, a0
3202; RV64-NEXT:    vsub.vv v8, v8, v9
3203; RV64-NEXT:    vand.vx v9, v8, a1
3204; RV64-NEXT:    vsrl.vi v8, v8, 2
3205; RV64-NEXT:    vand.vx v8, v8, a1
3206; RV64-NEXT:    vadd.vv v8, v9, v8
3207; RV64-NEXT:    lui a0, %hi(.LCPI40_2)
3208; RV64-NEXT:    ld a0, %lo(.LCPI40_2)(a0)
3209; RV64-NEXT:    lui a1, %hi(.LCPI40_3)
3210; RV64-NEXT:    ld a1, %lo(.LCPI40_3)(a1)
3211; RV64-NEXT:    vsrl.vi v9, v8, 4
3212; RV64-NEXT:    vadd.vv v8, v8, v9
3213; RV64-NEXT:    vand.vx v8, v8, a0
3214; RV64-NEXT:    vmul.vx v8, v8, a1
3215; RV64-NEXT:    li a0, 56
3216; RV64-NEXT:    vsrl.vx v8, v8, a0
3217; RV64-NEXT:    ret
3218  %a = call <vscale x 1 x i64> @llvm.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 true)
3219  ret <vscale x 1 x i64> %a
3220}
3221
3222define <vscale x 2 x i64> @cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
3223; RV32-LABEL: cttz_zero_undef_nxv2i64:
3224; RV32:       # %bb.0:
3225; RV32-NEXT:    addi sp, sp, -16
3226; RV32-NEXT:    .cfi_def_cfa_offset 16
3227; RV32-NEXT:    lui a0, 349525
3228; RV32-NEXT:    addi a0, a0, 1365
3229; RV32-NEXT:    sw a0, 12(sp)
3230; RV32-NEXT:    sw a0, 8(sp)
3231; RV32-NEXT:    lui a0, 209715
3232; RV32-NEXT:    addi a0, a0, 819
3233; RV32-NEXT:    sw a0, 12(sp)
3234; RV32-NEXT:    sw a0, 8(sp)
3235; RV32-NEXT:    lui a0, 61681
3236; RV32-NEXT:    addi a0, a0, -241
3237; RV32-NEXT:    sw a0, 12(sp)
3238; RV32-NEXT:    sw a0, 8(sp)
3239; RV32-NEXT:    lui a0, 4112
3240; RV32-NEXT:    addi a0, a0, 257
3241; RV32-NEXT:    sw a0, 12(sp)
3242; RV32-NEXT:    sw a0, 8(sp)
3243; RV32-NEXT:    li a0, 1
3244; RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
3245; RV32-NEXT:    vsub.vx v10, v8, a0
3246; RV32-NEXT:    vxor.vi v8, v8, -1
3247; RV32-NEXT:    addi a0, sp, 8
3248; RV32-NEXT:    vlse64.v v12, (a0), zero
3249; RV32-NEXT:    vand.vv v8, v8, v10
3250; RV32-NEXT:    addi a0, sp, 8
3251; RV32-NEXT:    vlse64.v v10, (a0), zero
3252; RV32-NEXT:    vsrl.vi v14, v8, 1
3253; RV32-NEXT:    vand.vv v12, v14, v12
3254; RV32-NEXT:    vsub.vv v8, v8, v12
3255; RV32-NEXT:    vand.vv v12, v8, v10
3256; RV32-NEXT:    vsrl.vi v8, v8, 2
3257; RV32-NEXT:    vand.vv v8, v8, v10
3258; RV32-NEXT:    vadd.vv v8, v12, v8
3259; RV32-NEXT:    addi a0, sp, 8
3260; RV32-NEXT:    vlse64.v v10, (a0), zero
3261; RV32-NEXT:    addi a0, sp, 8
3262; RV32-NEXT:    vlse64.v v12, (a0), zero
3263; RV32-NEXT:    vsrl.vi v14, v8, 4
3264; RV32-NEXT:    vadd.vv v8, v8, v14
3265; RV32-NEXT:    vand.vv v8, v8, v10
3266; RV32-NEXT:    vmul.vv v8, v8, v12
3267; RV32-NEXT:    li a0, 56
3268; RV32-NEXT:    vsrl.vx v8, v8, a0
3269; RV32-NEXT:    addi sp, sp, 16
3270; RV32-NEXT:    ret
3271;
3272; RV64-LABEL: cttz_zero_undef_nxv2i64:
3273; RV64:       # %bb.0:
3274; RV64-NEXT:    li a0, 1
3275; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
3276; RV64-NEXT:    vsub.vx v10, v8, a0
3277; RV64-NEXT:    vxor.vi v8, v8, -1
3278; RV64-NEXT:    vand.vv v8, v8, v10
3279; RV64-NEXT:    lui a0, %hi(.LCPI41_0)
3280; RV64-NEXT:    ld a0, %lo(.LCPI41_0)(a0)
3281; RV64-NEXT:    lui a1, %hi(.LCPI41_1)
3282; RV64-NEXT:    ld a1, %lo(.LCPI41_1)(a1)
3283; RV64-NEXT:    vsrl.vi v10, v8, 1
3284; RV64-NEXT:    vand.vx v10, v10, a0
3285; RV64-NEXT:    vsub.vv v8, v8, v10
3286; RV64-NEXT:    vand.vx v10, v8, a1
3287; RV64-NEXT:    vsrl.vi v8, v8, 2
3288; RV64-NEXT:    vand.vx v8, v8, a1
3289; RV64-NEXT:    vadd.vv v8, v10, v8
3290; RV64-NEXT:    lui a0, %hi(.LCPI41_2)
3291; RV64-NEXT:    ld a0, %lo(.LCPI41_2)(a0)
3292; RV64-NEXT:    lui a1, %hi(.LCPI41_3)
3293; RV64-NEXT:    ld a1, %lo(.LCPI41_3)(a1)
3294; RV64-NEXT:    vsrl.vi v10, v8, 4
3295; RV64-NEXT:    vadd.vv v8, v8, v10
3296; RV64-NEXT:    vand.vx v8, v8, a0
3297; RV64-NEXT:    vmul.vx v8, v8, a1
3298; RV64-NEXT:    li a0, 56
3299; RV64-NEXT:    vsrl.vx v8, v8, a0
3300; RV64-NEXT:    ret
3301  %a = call <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 true)
3302  ret <vscale x 2 x i64> %a
3303}
3304
3305define <vscale x 4 x i64> @cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
3306; RV32-LABEL: cttz_zero_undef_nxv4i64:
3307; RV32:       # %bb.0:
3308; RV32-NEXT:    addi sp, sp, -16
3309; RV32-NEXT:    .cfi_def_cfa_offset 16
3310; RV32-NEXT:    lui a0, 349525
3311; RV32-NEXT:    addi a0, a0, 1365
3312; RV32-NEXT:    sw a0, 12(sp)
3313; RV32-NEXT:    sw a0, 8(sp)
3314; RV32-NEXT:    lui a0, 209715
3315; RV32-NEXT:    addi a0, a0, 819
3316; RV32-NEXT:    sw a0, 12(sp)
3317; RV32-NEXT:    sw a0, 8(sp)
3318; RV32-NEXT:    lui a0, 61681
3319; RV32-NEXT:    addi a0, a0, -241
3320; RV32-NEXT:    sw a0, 12(sp)
3321; RV32-NEXT:    sw a0, 8(sp)
3322; RV32-NEXT:    lui a0, 4112
3323; RV32-NEXT:    addi a0, a0, 257
3324; RV32-NEXT:    sw a0, 12(sp)
3325; RV32-NEXT:    sw a0, 8(sp)
3326; RV32-NEXT:    li a0, 1
3327; RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
3328; RV32-NEXT:    vsub.vx v12, v8, a0
3329; RV32-NEXT:    vxor.vi v8, v8, -1
3330; RV32-NEXT:    addi a0, sp, 8
3331; RV32-NEXT:    vlse64.v v16, (a0), zero
3332; RV32-NEXT:    vand.vv v8, v8, v12
3333; RV32-NEXT:    addi a0, sp, 8
3334; RV32-NEXT:    vlse64.v v12, (a0), zero
3335; RV32-NEXT:    vsrl.vi v20, v8, 1
3336; RV32-NEXT:    vand.vv v16, v20, v16
3337; RV32-NEXT:    vsub.vv v8, v8, v16
3338; RV32-NEXT:    vand.vv v16, v8, v12
3339; RV32-NEXT:    vsrl.vi v8, v8, 2
3340; RV32-NEXT:    vand.vv v8, v8, v12
3341; RV32-NEXT:    vadd.vv v8, v16, v8
3342; RV32-NEXT:    addi a0, sp, 8
3343; RV32-NEXT:    vlse64.v v12, (a0), zero
3344; RV32-NEXT:    addi a0, sp, 8
3345; RV32-NEXT:    vlse64.v v16, (a0), zero
3346; RV32-NEXT:    vsrl.vi v20, v8, 4
3347; RV32-NEXT:    vadd.vv v8, v8, v20
3348; RV32-NEXT:    vand.vv v8, v8, v12
3349; RV32-NEXT:    vmul.vv v8, v8, v16
3350; RV32-NEXT:    li a0, 56
3351; RV32-NEXT:    vsrl.vx v8, v8, a0
3352; RV32-NEXT:    addi sp, sp, 16
3353; RV32-NEXT:    ret
3354;
3355; RV64-LABEL: cttz_zero_undef_nxv4i64:
3356; RV64:       # %bb.0:
3357; RV64-NEXT:    li a0, 1
3358; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
3359; RV64-NEXT:    vsub.vx v12, v8, a0
3360; RV64-NEXT:    vxor.vi v8, v8, -1
3361; RV64-NEXT:    vand.vv v8, v8, v12
3362; RV64-NEXT:    lui a0, %hi(.LCPI42_0)
3363; RV64-NEXT:    ld a0, %lo(.LCPI42_0)(a0)
3364; RV64-NEXT:    lui a1, %hi(.LCPI42_1)
3365; RV64-NEXT:    ld a1, %lo(.LCPI42_1)(a1)
3366; RV64-NEXT:    vsrl.vi v12, v8, 1
3367; RV64-NEXT:    vand.vx v12, v12, a0
3368; RV64-NEXT:    vsub.vv v8, v8, v12
3369; RV64-NEXT:    vand.vx v12, v8, a1
3370; RV64-NEXT:    vsrl.vi v8, v8, 2
3371; RV64-NEXT:    vand.vx v8, v8, a1
3372; RV64-NEXT:    vadd.vv v8, v12, v8
3373; RV64-NEXT:    lui a0, %hi(.LCPI42_2)
3374; RV64-NEXT:    ld a0, %lo(.LCPI42_2)(a0)
3375; RV64-NEXT:    lui a1, %hi(.LCPI42_3)
3376; RV64-NEXT:    ld a1, %lo(.LCPI42_3)(a1)
3377; RV64-NEXT:    vsrl.vi v12, v8, 4
3378; RV64-NEXT:    vadd.vv v8, v8, v12
3379; RV64-NEXT:    vand.vx v8, v8, a0
3380; RV64-NEXT:    vmul.vx v8, v8, a1
3381; RV64-NEXT:    li a0, 56
3382; RV64-NEXT:    vsrl.vx v8, v8, a0
3383; RV64-NEXT:    ret
3384  %a = call <vscale x 4 x i64> @llvm.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 true)
3385  ret <vscale x 4 x i64> %a
3386}
3387
3388define <vscale x 8 x i64> @cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
3389; RV32-LABEL: cttz_zero_undef_nxv8i64:
3390; RV32:       # %bb.0:
3391; RV32-NEXT:    addi sp, sp, -16
3392; RV32-NEXT:    .cfi_def_cfa_offset 16
3393; RV32-NEXT:    lui a0, 349525
3394; RV32-NEXT:    addi a0, a0, 1365
3395; RV32-NEXT:    sw a0, 12(sp)
3396; RV32-NEXT:    sw a0, 8(sp)
3397; RV32-NEXT:    lui a0, 209715
3398; RV32-NEXT:    addi a0, a0, 819
3399; RV32-NEXT:    sw a0, 12(sp)
3400; RV32-NEXT:    sw a0, 8(sp)
3401; RV32-NEXT:    lui a0, 61681
3402; RV32-NEXT:    addi a0, a0, -241
3403; RV32-NEXT:    sw a0, 12(sp)
3404; RV32-NEXT:    sw a0, 8(sp)
3405; RV32-NEXT:    lui a0, 4112
3406; RV32-NEXT:    addi a0, a0, 257
3407; RV32-NEXT:    sw a0, 12(sp)
3408; RV32-NEXT:    sw a0, 8(sp)
3409; RV32-NEXT:    li a0, 1
3410; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
3411; RV32-NEXT:    vsub.vx v16, v8, a0
3412; RV32-NEXT:    vxor.vi v8, v8, -1
3413; RV32-NEXT:    addi a0, sp, 8
3414; RV32-NEXT:    vlse64.v v24, (a0), zero
3415; RV32-NEXT:    vand.vv v8, v8, v16
3416; RV32-NEXT:    addi a0, sp, 8
3417; RV32-NEXT:    vlse64.v v16, (a0), zero
3418; RV32-NEXT:    vsrl.vi v0, v8, 1
3419; RV32-NEXT:    vand.vv v24, v0, v24
3420; RV32-NEXT:    vsub.vv v8, v8, v24
3421; RV32-NEXT:    vand.vv v24, v8, v16
3422; RV32-NEXT:    vsrl.vi v8, v8, 2
3423; RV32-NEXT:    vand.vv v8, v8, v16
3424; RV32-NEXT:    vadd.vv v8, v24, v8
3425; RV32-NEXT:    addi a0, sp, 8
3426; RV32-NEXT:    vlse64.v v16, (a0), zero
3427; RV32-NEXT:    addi a0, sp, 8
3428; RV32-NEXT:    vlse64.v v24, (a0), zero
3429; RV32-NEXT:    vsrl.vi v0, v8, 4
3430; RV32-NEXT:    vadd.vv v8, v8, v0
3431; RV32-NEXT:    vand.vv v8, v8, v16
3432; RV32-NEXT:    vmul.vv v8, v8, v24
3433; RV32-NEXT:    li a0, 56
3434; RV32-NEXT:    vsrl.vx v8, v8, a0
3435; RV32-NEXT:    addi sp, sp, 16
3436; RV32-NEXT:    ret
3437;
3438; RV64-LABEL: cttz_zero_undef_nxv8i64:
3439; RV64:       # %bb.0:
3440; RV64-NEXT:    li a0, 1
3441; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
3442; RV64-NEXT:    vsub.vx v16, v8, a0
3443; RV64-NEXT:    vxor.vi v8, v8, -1
3444; RV64-NEXT:    vand.vv v8, v8, v16
3445; RV64-NEXT:    lui a0, %hi(.LCPI43_0)
3446; RV64-NEXT:    ld a0, %lo(.LCPI43_0)(a0)
3447; RV64-NEXT:    lui a1, %hi(.LCPI43_1)
3448; RV64-NEXT:    ld a1, %lo(.LCPI43_1)(a1)
3449; RV64-NEXT:    vsrl.vi v16, v8, 1
3450; RV64-NEXT:    vand.vx v16, v16, a0
3451; RV64-NEXT:    vsub.vv v8, v8, v16
3452; RV64-NEXT:    vand.vx v16, v8, a1
3453; RV64-NEXT:    vsrl.vi v8, v8, 2
3454; RV64-NEXT:    vand.vx v8, v8, a1
3455; RV64-NEXT:    vadd.vv v8, v16, v8
3456; RV64-NEXT:    lui a0, %hi(.LCPI43_2)
3457; RV64-NEXT:    ld a0, %lo(.LCPI43_2)(a0)
3458; RV64-NEXT:    lui a1, %hi(.LCPI43_3)
3459; RV64-NEXT:    ld a1, %lo(.LCPI43_3)(a1)
3460; RV64-NEXT:    vsrl.vi v16, v8, 4
3461; RV64-NEXT:    vadd.vv v8, v8, v16
3462; RV64-NEXT:    vand.vx v8, v8, a0
3463; RV64-NEXT:    vmul.vx v8, v8, a1
3464; RV64-NEXT:    li a0, 56
3465; RV64-NEXT:    vsrl.vx v8, v8, a0
3466; RV64-NEXT:    ret
3467  %a = call <vscale x 8 x i64> @llvm.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 true)
3468  ret <vscale x 8 x i64> %a
3469}
3470