1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
3; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
4
5define <vscale x 1 x i8> @ctpop_nxv1i8(<vscale x 1 x i8> %va) {
6; CHECK-LABEL: ctpop_nxv1i8:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
9; CHECK-NEXT:    vsrl.vi v9, v8, 1
10; CHECK-NEXT:    addi a0, zero, 85
11; CHECK-NEXT:    vand.vx v9, v9, a0
12; CHECK-NEXT:    vsub.vv v8, v8, v9
13; CHECK-NEXT:    addi a0, zero, 51
14; CHECK-NEXT:    vand.vx v9, v8, a0
15; CHECK-NEXT:    vsrl.vi v8, v8, 2
16; CHECK-NEXT:    vand.vx v8, v8, a0
17; CHECK-NEXT:    vadd.vv v8, v9, v8
18; CHECK-NEXT:    vsrl.vi v9, v8, 4
19; CHECK-NEXT:    vadd.vv v8, v8, v9
20; CHECK-NEXT:    vand.vi v8, v8, 15
21; CHECK-NEXT:    ret
22  %a = call <vscale x 1 x i8> @llvm.ctpop.nxv1i8(<vscale x 1 x i8> %va)
23  ret <vscale x 1 x i8> %a
24}
25declare <vscale x 1 x i8> @llvm.ctpop.nxv1i8(<vscale x 1 x i8>)
26
27define <vscale x 2 x i8> @ctpop_nxv2i8(<vscale x 2 x i8> %va) {
28; CHECK-LABEL: ctpop_nxv2i8:
29; CHECK:       # %bb.0:
30; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, mu
31; CHECK-NEXT:    vsrl.vi v9, v8, 1
32; CHECK-NEXT:    addi a0, zero, 85
33; CHECK-NEXT:    vand.vx v9, v9, a0
34; CHECK-NEXT:    vsub.vv v8, v8, v9
35; CHECK-NEXT:    addi a0, zero, 51
36; CHECK-NEXT:    vand.vx v9, v8, a0
37; CHECK-NEXT:    vsrl.vi v8, v8, 2
38; CHECK-NEXT:    vand.vx v8, v8, a0
39; CHECK-NEXT:    vadd.vv v8, v9, v8
40; CHECK-NEXT:    vsrl.vi v9, v8, 4
41; CHECK-NEXT:    vadd.vv v8, v8, v9
42; CHECK-NEXT:    vand.vi v8, v8, 15
43; CHECK-NEXT:    ret
44  %a = call <vscale x 2 x i8> @llvm.ctpop.nxv2i8(<vscale x 2 x i8> %va)
45  ret <vscale x 2 x i8> %a
46}
47declare <vscale x 2 x i8> @llvm.ctpop.nxv2i8(<vscale x 2 x i8>)
48
49define <vscale x 4 x i8> @ctpop_nxv4i8(<vscale x 4 x i8> %va) {
50; CHECK-LABEL: ctpop_nxv4i8:
51; CHECK:       # %bb.0:
52; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, mu
53; CHECK-NEXT:    vsrl.vi v9, v8, 1
54; CHECK-NEXT:    addi a0, zero, 85
55; CHECK-NEXT:    vand.vx v9, v9, a0
56; CHECK-NEXT:    vsub.vv v8, v8, v9
57; CHECK-NEXT:    addi a0, zero, 51
58; CHECK-NEXT:    vand.vx v9, v8, a0
59; CHECK-NEXT:    vsrl.vi v8, v8, 2
60; CHECK-NEXT:    vand.vx v8, v8, a0
61; CHECK-NEXT:    vadd.vv v8, v9, v8
62; CHECK-NEXT:    vsrl.vi v9, v8, 4
63; CHECK-NEXT:    vadd.vv v8, v8, v9
64; CHECK-NEXT:    vand.vi v8, v8, 15
65; CHECK-NEXT:    ret
66  %a = call <vscale x 4 x i8> @llvm.ctpop.nxv4i8(<vscale x 4 x i8> %va)
67  ret <vscale x 4 x i8> %a
68}
69declare <vscale x 4 x i8> @llvm.ctpop.nxv4i8(<vscale x 4 x i8>)
70
71define <vscale x 8 x i8> @ctpop_nxv8i8(<vscale x 8 x i8> %va) {
72; CHECK-LABEL: ctpop_nxv8i8:
73; CHECK:       # %bb.0:
74; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
75; CHECK-NEXT:    vsrl.vi v9, v8, 1
76; CHECK-NEXT:    addi a0, zero, 85
77; CHECK-NEXT:    vand.vx v9, v9, a0
78; CHECK-NEXT:    vsub.vv v8, v8, v9
79; CHECK-NEXT:    addi a0, zero, 51
80; CHECK-NEXT:    vand.vx v9, v8, a0
81; CHECK-NEXT:    vsrl.vi v8, v8, 2
82; CHECK-NEXT:    vand.vx v8, v8, a0
83; CHECK-NEXT:    vadd.vv v8, v9, v8
84; CHECK-NEXT:    vsrl.vi v9, v8, 4
85; CHECK-NEXT:    vadd.vv v8, v8, v9
86; CHECK-NEXT:    vand.vi v8, v8, 15
87; CHECK-NEXT:    ret
88  %a = call <vscale x 8 x i8> @llvm.ctpop.nxv8i8(<vscale x 8 x i8> %va)
89  ret <vscale x 8 x i8> %a
90}
91declare <vscale x 8 x i8> @llvm.ctpop.nxv8i8(<vscale x 8 x i8>)
92
93define <vscale x 16 x i8> @ctpop_nxv16i8(<vscale x 16 x i8> %va) {
94; CHECK-LABEL: ctpop_nxv16i8:
95; CHECK:       # %bb.0:
96; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, mu
97; CHECK-NEXT:    vsrl.vi v10, v8, 1
98; CHECK-NEXT:    addi a0, zero, 85
99; CHECK-NEXT:    vand.vx v10, v10, a0
100; CHECK-NEXT:    vsub.vv v8, v8, v10
101; CHECK-NEXT:    addi a0, zero, 51
102; CHECK-NEXT:    vand.vx v10, v8, a0
103; CHECK-NEXT:    vsrl.vi v8, v8, 2
104; CHECK-NEXT:    vand.vx v8, v8, a0
105; CHECK-NEXT:    vadd.vv v8, v10, v8
106; CHECK-NEXT:    vsrl.vi v10, v8, 4
107; CHECK-NEXT:    vadd.vv v8, v8, v10
108; CHECK-NEXT:    vand.vi v8, v8, 15
109; CHECK-NEXT:    ret
110  %a = call <vscale x 16 x i8> @llvm.ctpop.nxv16i8(<vscale x 16 x i8> %va)
111  ret <vscale x 16 x i8> %a
112}
113declare <vscale x 16 x i8> @llvm.ctpop.nxv16i8(<vscale x 16 x i8>)
114
115define <vscale x 32 x i8> @ctpop_nxv32i8(<vscale x 32 x i8> %va) {
116; CHECK-LABEL: ctpop_nxv32i8:
117; CHECK:       # %bb.0:
118; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, mu
119; CHECK-NEXT:    vsrl.vi v12, v8, 1
120; CHECK-NEXT:    addi a0, zero, 85
121; CHECK-NEXT:    vand.vx v12, v12, a0
122; CHECK-NEXT:    vsub.vv v8, v8, v12
123; CHECK-NEXT:    addi a0, zero, 51
124; CHECK-NEXT:    vand.vx v12, v8, a0
125; CHECK-NEXT:    vsrl.vi v8, v8, 2
126; CHECK-NEXT:    vand.vx v8, v8, a0
127; CHECK-NEXT:    vadd.vv v8, v12, v8
128; CHECK-NEXT:    vsrl.vi v12, v8, 4
129; CHECK-NEXT:    vadd.vv v8, v8, v12
130; CHECK-NEXT:    vand.vi v8, v8, 15
131; CHECK-NEXT:    ret
132  %a = call <vscale x 32 x i8> @llvm.ctpop.nxv32i8(<vscale x 32 x i8> %va)
133  ret <vscale x 32 x i8> %a
134}
135declare <vscale x 32 x i8> @llvm.ctpop.nxv32i8(<vscale x 32 x i8>)
136
137define <vscale x 64 x i8> @ctpop_nxv64i8(<vscale x 64 x i8> %va) {
138; CHECK-LABEL: ctpop_nxv64i8:
139; CHECK:       # %bb.0:
140; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, mu
141; CHECK-NEXT:    vsrl.vi v16, v8, 1
142; CHECK-NEXT:    addi a0, zero, 85
143; CHECK-NEXT:    vand.vx v16, v16, a0
144; CHECK-NEXT:    vsub.vv v8, v8, v16
145; CHECK-NEXT:    addi a0, zero, 51
146; CHECK-NEXT:    vand.vx v16, v8, a0
147; CHECK-NEXT:    vsrl.vi v8, v8, 2
148; CHECK-NEXT:    vand.vx v8, v8, a0
149; CHECK-NEXT:    vadd.vv v8, v16, v8
150; CHECK-NEXT:    vsrl.vi v16, v8, 4
151; CHECK-NEXT:    vadd.vv v8, v8, v16
152; CHECK-NEXT:    vand.vi v8, v8, 15
153; CHECK-NEXT:    ret
154  %a = call <vscale x 64 x i8> @llvm.ctpop.nxv64i8(<vscale x 64 x i8> %va)
155  ret <vscale x 64 x i8> %a
156}
157declare <vscale x 64 x i8> @llvm.ctpop.nxv64i8(<vscale x 64 x i8>)
158
159define <vscale x 1 x i16> @ctpop_nxv1i16(<vscale x 1 x i16> %va) {
160; RV32-LABEL: ctpop_nxv1i16:
161; RV32:       # %bb.0:
162; RV32-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
163; RV32-NEXT:    vsrl.vi v9, v8, 1
164; RV32-NEXT:    lui a0, 5
165; RV32-NEXT:    addi a0, a0, 1365
166; RV32-NEXT:    vand.vx v9, v9, a0
167; RV32-NEXT:    vsub.vv v8, v8, v9
168; RV32-NEXT:    lui a0, 3
169; RV32-NEXT:    addi a0, a0, 819
170; RV32-NEXT:    vand.vx v9, v8, a0
171; RV32-NEXT:    vsrl.vi v8, v8, 2
172; RV32-NEXT:    vand.vx v8, v8, a0
173; RV32-NEXT:    vadd.vv v8, v9, v8
174; RV32-NEXT:    vsrl.vi v9, v8, 4
175; RV32-NEXT:    vadd.vv v8, v8, v9
176; RV32-NEXT:    lui a0, 1
177; RV32-NEXT:    addi a0, a0, -241
178; RV32-NEXT:    vand.vx v8, v8, a0
179; RV32-NEXT:    addi a0, zero, 257
180; RV32-NEXT:    vmul.vx v8, v8, a0
181; RV32-NEXT:    vsrl.vi v8, v8, 8
182; RV32-NEXT:    ret
183;
184; RV64-LABEL: ctpop_nxv1i16:
185; RV64:       # %bb.0:
186; RV64-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
187; RV64-NEXT:    vsrl.vi v9, v8, 1
188; RV64-NEXT:    lui a0, 5
189; RV64-NEXT:    addiw a0, a0, 1365
190; RV64-NEXT:    vand.vx v9, v9, a0
191; RV64-NEXT:    vsub.vv v8, v8, v9
192; RV64-NEXT:    lui a0, 3
193; RV64-NEXT:    addiw a0, a0, 819
194; RV64-NEXT:    vand.vx v9, v8, a0
195; RV64-NEXT:    vsrl.vi v8, v8, 2
196; RV64-NEXT:    vand.vx v8, v8, a0
197; RV64-NEXT:    vadd.vv v8, v9, v8
198; RV64-NEXT:    vsrl.vi v9, v8, 4
199; RV64-NEXT:    vadd.vv v8, v8, v9
200; RV64-NEXT:    lui a0, 1
201; RV64-NEXT:    addiw a0, a0, -241
202; RV64-NEXT:    vand.vx v8, v8, a0
203; RV64-NEXT:    addi a0, zero, 257
204; RV64-NEXT:    vmul.vx v8, v8, a0
205; RV64-NEXT:    vsrl.vi v8, v8, 8
206; RV64-NEXT:    ret
207  %a = call <vscale x 1 x i16> @llvm.ctpop.nxv1i16(<vscale x 1 x i16> %va)
208  ret <vscale x 1 x i16> %a
209}
210declare <vscale x 1 x i16> @llvm.ctpop.nxv1i16(<vscale x 1 x i16>)
211
212define <vscale x 2 x i16> @ctpop_nxv2i16(<vscale x 2 x i16> %va) {
213; RV32-LABEL: ctpop_nxv2i16:
214; RV32:       # %bb.0:
215; RV32-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
216; RV32-NEXT:    vsrl.vi v9, v8, 1
217; RV32-NEXT:    lui a0, 5
218; RV32-NEXT:    addi a0, a0, 1365
219; RV32-NEXT:    vand.vx v9, v9, a0
220; RV32-NEXT:    vsub.vv v8, v8, v9
221; RV32-NEXT:    lui a0, 3
222; RV32-NEXT:    addi a0, a0, 819
223; RV32-NEXT:    vand.vx v9, v8, a0
224; RV32-NEXT:    vsrl.vi v8, v8, 2
225; RV32-NEXT:    vand.vx v8, v8, a0
226; RV32-NEXT:    vadd.vv v8, v9, v8
227; RV32-NEXT:    vsrl.vi v9, v8, 4
228; RV32-NEXT:    vadd.vv v8, v8, v9
229; RV32-NEXT:    lui a0, 1
230; RV32-NEXT:    addi a0, a0, -241
231; RV32-NEXT:    vand.vx v8, v8, a0
232; RV32-NEXT:    addi a0, zero, 257
233; RV32-NEXT:    vmul.vx v8, v8, a0
234; RV32-NEXT:    vsrl.vi v8, v8, 8
235; RV32-NEXT:    ret
236;
237; RV64-LABEL: ctpop_nxv2i16:
238; RV64:       # %bb.0:
239; RV64-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
240; RV64-NEXT:    vsrl.vi v9, v8, 1
241; RV64-NEXT:    lui a0, 5
242; RV64-NEXT:    addiw a0, a0, 1365
243; RV64-NEXT:    vand.vx v9, v9, a0
244; RV64-NEXT:    vsub.vv v8, v8, v9
245; RV64-NEXT:    lui a0, 3
246; RV64-NEXT:    addiw a0, a0, 819
247; RV64-NEXT:    vand.vx v9, v8, a0
248; RV64-NEXT:    vsrl.vi v8, v8, 2
249; RV64-NEXT:    vand.vx v8, v8, a0
250; RV64-NEXT:    vadd.vv v8, v9, v8
251; RV64-NEXT:    vsrl.vi v9, v8, 4
252; RV64-NEXT:    vadd.vv v8, v8, v9
253; RV64-NEXT:    lui a0, 1
254; RV64-NEXT:    addiw a0, a0, -241
255; RV64-NEXT:    vand.vx v8, v8, a0
256; RV64-NEXT:    addi a0, zero, 257
257; RV64-NEXT:    vmul.vx v8, v8, a0
258; RV64-NEXT:    vsrl.vi v8, v8, 8
259; RV64-NEXT:    ret
260  %a = call <vscale x 2 x i16> @llvm.ctpop.nxv2i16(<vscale x 2 x i16> %va)
261  ret <vscale x 2 x i16> %a
262}
263declare <vscale x 2 x i16> @llvm.ctpop.nxv2i16(<vscale x 2 x i16>)
264
265define <vscale x 4 x i16> @ctpop_nxv4i16(<vscale x 4 x i16> %va) {
266; RV32-LABEL: ctpop_nxv4i16:
267; RV32:       # %bb.0:
268; RV32-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
269; RV32-NEXT:    vsrl.vi v9, v8, 1
270; RV32-NEXT:    lui a0, 5
271; RV32-NEXT:    addi a0, a0, 1365
272; RV32-NEXT:    vand.vx v9, v9, a0
273; RV32-NEXT:    vsub.vv v8, v8, v9
274; RV32-NEXT:    lui a0, 3
275; RV32-NEXT:    addi a0, a0, 819
276; RV32-NEXT:    vand.vx v9, v8, a0
277; RV32-NEXT:    vsrl.vi v8, v8, 2
278; RV32-NEXT:    vand.vx v8, v8, a0
279; RV32-NEXT:    vadd.vv v8, v9, v8
280; RV32-NEXT:    vsrl.vi v9, v8, 4
281; RV32-NEXT:    vadd.vv v8, v8, v9
282; RV32-NEXT:    lui a0, 1
283; RV32-NEXT:    addi a0, a0, -241
284; RV32-NEXT:    vand.vx v8, v8, a0
285; RV32-NEXT:    addi a0, zero, 257
286; RV32-NEXT:    vmul.vx v8, v8, a0
287; RV32-NEXT:    vsrl.vi v8, v8, 8
288; RV32-NEXT:    ret
289;
290; RV64-LABEL: ctpop_nxv4i16:
291; RV64:       # %bb.0:
292; RV64-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
293; RV64-NEXT:    vsrl.vi v9, v8, 1
294; RV64-NEXT:    lui a0, 5
295; RV64-NEXT:    addiw a0, a0, 1365
296; RV64-NEXT:    vand.vx v9, v9, a0
297; RV64-NEXT:    vsub.vv v8, v8, v9
298; RV64-NEXT:    lui a0, 3
299; RV64-NEXT:    addiw a0, a0, 819
300; RV64-NEXT:    vand.vx v9, v8, a0
301; RV64-NEXT:    vsrl.vi v8, v8, 2
302; RV64-NEXT:    vand.vx v8, v8, a0
303; RV64-NEXT:    vadd.vv v8, v9, v8
304; RV64-NEXT:    vsrl.vi v9, v8, 4
305; RV64-NEXT:    vadd.vv v8, v8, v9
306; RV64-NEXT:    lui a0, 1
307; RV64-NEXT:    addiw a0, a0, -241
308; RV64-NEXT:    vand.vx v8, v8, a0
309; RV64-NEXT:    addi a0, zero, 257
310; RV64-NEXT:    vmul.vx v8, v8, a0
311; RV64-NEXT:    vsrl.vi v8, v8, 8
312; RV64-NEXT:    ret
313  %a = call <vscale x 4 x i16> @llvm.ctpop.nxv4i16(<vscale x 4 x i16> %va)
314  ret <vscale x 4 x i16> %a
315}
316declare <vscale x 4 x i16> @llvm.ctpop.nxv4i16(<vscale x 4 x i16>)
317
318define <vscale x 8 x i16> @ctpop_nxv8i16(<vscale x 8 x i16> %va) {
319; RV32-LABEL: ctpop_nxv8i16:
320; RV32:       # %bb.0:
321; RV32-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
322; RV32-NEXT:    vsrl.vi v10, v8, 1
323; RV32-NEXT:    lui a0, 5
324; RV32-NEXT:    addi a0, a0, 1365
325; RV32-NEXT:    vand.vx v10, v10, a0
326; RV32-NEXT:    vsub.vv v8, v8, v10
327; RV32-NEXT:    lui a0, 3
328; RV32-NEXT:    addi a0, a0, 819
329; RV32-NEXT:    vand.vx v10, v8, a0
330; RV32-NEXT:    vsrl.vi v8, v8, 2
331; RV32-NEXT:    vand.vx v8, v8, a0
332; RV32-NEXT:    vadd.vv v8, v10, v8
333; RV32-NEXT:    vsrl.vi v10, v8, 4
334; RV32-NEXT:    vadd.vv v8, v8, v10
335; RV32-NEXT:    lui a0, 1
336; RV32-NEXT:    addi a0, a0, -241
337; RV32-NEXT:    vand.vx v8, v8, a0
338; RV32-NEXT:    addi a0, zero, 257
339; RV32-NEXT:    vmul.vx v8, v8, a0
340; RV32-NEXT:    vsrl.vi v8, v8, 8
341; RV32-NEXT:    ret
342;
343; RV64-LABEL: ctpop_nxv8i16:
344; RV64:       # %bb.0:
345; RV64-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
346; RV64-NEXT:    vsrl.vi v10, v8, 1
347; RV64-NEXT:    lui a0, 5
348; RV64-NEXT:    addiw a0, a0, 1365
349; RV64-NEXT:    vand.vx v10, v10, a0
350; RV64-NEXT:    vsub.vv v8, v8, v10
351; RV64-NEXT:    lui a0, 3
352; RV64-NEXT:    addiw a0, a0, 819
353; RV64-NEXT:    vand.vx v10, v8, a0
354; RV64-NEXT:    vsrl.vi v8, v8, 2
355; RV64-NEXT:    vand.vx v8, v8, a0
356; RV64-NEXT:    vadd.vv v8, v10, v8
357; RV64-NEXT:    vsrl.vi v10, v8, 4
358; RV64-NEXT:    vadd.vv v8, v8, v10
359; RV64-NEXT:    lui a0, 1
360; RV64-NEXT:    addiw a0, a0, -241
361; RV64-NEXT:    vand.vx v8, v8, a0
362; RV64-NEXT:    addi a0, zero, 257
363; RV64-NEXT:    vmul.vx v8, v8, a0
364; RV64-NEXT:    vsrl.vi v8, v8, 8
365; RV64-NEXT:    ret
366  %a = call <vscale x 8 x i16> @llvm.ctpop.nxv8i16(<vscale x 8 x i16> %va)
367  ret <vscale x 8 x i16> %a
368}
369declare <vscale x 8 x i16> @llvm.ctpop.nxv8i16(<vscale x 8 x i16>)
370
371define <vscale x 16 x i16> @ctpop_nxv16i16(<vscale x 16 x i16> %va) {
372; RV32-LABEL: ctpop_nxv16i16:
373; RV32:       # %bb.0:
374; RV32-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
375; RV32-NEXT:    vsrl.vi v12, v8, 1
376; RV32-NEXT:    lui a0, 5
377; RV32-NEXT:    addi a0, a0, 1365
378; RV32-NEXT:    vand.vx v12, v12, a0
379; RV32-NEXT:    vsub.vv v8, v8, v12
380; RV32-NEXT:    lui a0, 3
381; RV32-NEXT:    addi a0, a0, 819
382; RV32-NEXT:    vand.vx v12, v8, a0
383; RV32-NEXT:    vsrl.vi v8, v8, 2
384; RV32-NEXT:    vand.vx v8, v8, a0
385; RV32-NEXT:    vadd.vv v8, v12, v8
386; RV32-NEXT:    vsrl.vi v12, v8, 4
387; RV32-NEXT:    vadd.vv v8, v8, v12
388; RV32-NEXT:    lui a0, 1
389; RV32-NEXT:    addi a0, a0, -241
390; RV32-NEXT:    vand.vx v8, v8, a0
391; RV32-NEXT:    addi a0, zero, 257
392; RV32-NEXT:    vmul.vx v8, v8, a0
393; RV32-NEXT:    vsrl.vi v8, v8, 8
394; RV32-NEXT:    ret
395;
396; RV64-LABEL: ctpop_nxv16i16:
397; RV64:       # %bb.0:
398; RV64-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
399; RV64-NEXT:    vsrl.vi v12, v8, 1
400; RV64-NEXT:    lui a0, 5
401; RV64-NEXT:    addiw a0, a0, 1365
402; RV64-NEXT:    vand.vx v12, v12, a0
403; RV64-NEXT:    vsub.vv v8, v8, v12
404; RV64-NEXT:    lui a0, 3
405; RV64-NEXT:    addiw a0, a0, 819
406; RV64-NEXT:    vand.vx v12, v8, a0
407; RV64-NEXT:    vsrl.vi v8, v8, 2
408; RV64-NEXT:    vand.vx v8, v8, a0
409; RV64-NEXT:    vadd.vv v8, v12, v8
410; RV64-NEXT:    vsrl.vi v12, v8, 4
411; RV64-NEXT:    vadd.vv v8, v8, v12
412; RV64-NEXT:    lui a0, 1
413; RV64-NEXT:    addiw a0, a0, -241
414; RV64-NEXT:    vand.vx v8, v8, a0
415; RV64-NEXT:    addi a0, zero, 257
416; RV64-NEXT:    vmul.vx v8, v8, a0
417; RV64-NEXT:    vsrl.vi v8, v8, 8
418; RV64-NEXT:    ret
419  %a = call <vscale x 16 x i16> @llvm.ctpop.nxv16i16(<vscale x 16 x i16> %va)
420  ret <vscale x 16 x i16> %a
421}
422declare <vscale x 16 x i16> @llvm.ctpop.nxv16i16(<vscale x 16 x i16>)
423
424define <vscale x 32 x i16> @ctpop_nxv32i16(<vscale x 32 x i16> %va) {
425; RV32-LABEL: ctpop_nxv32i16:
426; RV32:       # %bb.0:
427; RV32-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
428; RV32-NEXT:    vsrl.vi v16, v8, 1
429; RV32-NEXT:    lui a0, 5
430; RV32-NEXT:    addi a0, a0, 1365
431; RV32-NEXT:    vand.vx v16, v16, a0
432; RV32-NEXT:    vsub.vv v8, v8, v16
433; RV32-NEXT:    lui a0, 3
434; RV32-NEXT:    addi a0, a0, 819
435; RV32-NEXT:    vand.vx v16, v8, a0
436; RV32-NEXT:    vsrl.vi v8, v8, 2
437; RV32-NEXT:    vand.vx v8, v8, a0
438; RV32-NEXT:    vadd.vv v8, v16, v8
439; RV32-NEXT:    vsrl.vi v16, v8, 4
440; RV32-NEXT:    vadd.vv v8, v8, v16
441; RV32-NEXT:    lui a0, 1
442; RV32-NEXT:    addi a0, a0, -241
443; RV32-NEXT:    vand.vx v8, v8, a0
444; RV32-NEXT:    addi a0, zero, 257
445; RV32-NEXT:    vmul.vx v8, v8, a0
446; RV32-NEXT:    vsrl.vi v8, v8, 8
447; RV32-NEXT:    ret
448;
449; RV64-LABEL: ctpop_nxv32i16:
450; RV64:       # %bb.0:
451; RV64-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
452; RV64-NEXT:    vsrl.vi v16, v8, 1
453; RV64-NEXT:    lui a0, 5
454; RV64-NEXT:    addiw a0, a0, 1365
455; RV64-NEXT:    vand.vx v16, v16, a0
456; RV64-NEXT:    vsub.vv v8, v8, v16
457; RV64-NEXT:    lui a0, 3
458; RV64-NEXT:    addiw a0, a0, 819
459; RV64-NEXT:    vand.vx v16, v8, a0
460; RV64-NEXT:    vsrl.vi v8, v8, 2
461; RV64-NEXT:    vand.vx v8, v8, a0
462; RV64-NEXT:    vadd.vv v8, v16, v8
463; RV64-NEXT:    vsrl.vi v16, v8, 4
464; RV64-NEXT:    vadd.vv v8, v8, v16
465; RV64-NEXT:    lui a0, 1
466; RV64-NEXT:    addiw a0, a0, -241
467; RV64-NEXT:    vand.vx v8, v8, a0
468; RV64-NEXT:    addi a0, zero, 257
469; RV64-NEXT:    vmul.vx v8, v8, a0
470; RV64-NEXT:    vsrl.vi v8, v8, 8
471; RV64-NEXT:    ret
472  %a = call <vscale x 32 x i16> @llvm.ctpop.nxv32i16(<vscale x 32 x i16> %va)
473  ret <vscale x 32 x i16> %a
474}
475declare <vscale x 32 x i16> @llvm.ctpop.nxv32i16(<vscale x 32 x i16>)
476
477define <vscale x 1 x i32> @ctpop_nxv1i32(<vscale x 1 x i32> %va) {
478; RV32-LABEL: ctpop_nxv1i32:
479; RV32:       # %bb.0:
480; RV32-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
481; RV32-NEXT:    vsrl.vi v9, v8, 1
482; RV32-NEXT:    lui a0, 349525
483; RV32-NEXT:    addi a0, a0, 1365
484; RV32-NEXT:    vand.vx v9, v9, a0
485; RV32-NEXT:    vsub.vv v8, v8, v9
486; RV32-NEXT:    lui a0, 209715
487; RV32-NEXT:    addi a0, a0, 819
488; RV32-NEXT:    vand.vx v9, v8, a0
489; RV32-NEXT:    vsrl.vi v8, v8, 2
490; RV32-NEXT:    vand.vx v8, v8, a0
491; RV32-NEXT:    vadd.vv v8, v9, v8
492; RV32-NEXT:    vsrl.vi v9, v8, 4
493; RV32-NEXT:    vadd.vv v8, v8, v9
494; RV32-NEXT:    lui a0, 61681
495; RV32-NEXT:    addi a0, a0, -241
496; RV32-NEXT:    vand.vx v8, v8, a0
497; RV32-NEXT:    lui a0, 4112
498; RV32-NEXT:    addi a0, a0, 257
499; RV32-NEXT:    vmul.vx v8, v8, a0
500; RV32-NEXT:    vsrl.vi v8, v8, 24
501; RV32-NEXT:    ret
502;
503; RV64-LABEL: ctpop_nxv1i32:
504; RV64:       # %bb.0:
505; RV64-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
506; RV64-NEXT:    vsrl.vi v9, v8, 1
507; RV64-NEXT:    lui a0, 349525
508; RV64-NEXT:    addiw a0, a0, 1365
509; RV64-NEXT:    vand.vx v9, v9, a0
510; RV64-NEXT:    vsub.vv v8, v8, v9
511; RV64-NEXT:    lui a0, 209715
512; RV64-NEXT:    addiw a0, a0, 819
513; RV64-NEXT:    vand.vx v9, v8, a0
514; RV64-NEXT:    vsrl.vi v8, v8, 2
515; RV64-NEXT:    vand.vx v8, v8, a0
516; RV64-NEXT:    vadd.vv v8, v9, v8
517; RV64-NEXT:    vsrl.vi v9, v8, 4
518; RV64-NEXT:    vadd.vv v8, v8, v9
519; RV64-NEXT:    lui a0, 61681
520; RV64-NEXT:    addiw a0, a0, -241
521; RV64-NEXT:    vand.vx v8, v8, a0
522; RV64-NEXT:    lui a0, 4112
523; RV64-NEXT:    addiw a0, a0, 257
524; RV64-NEXT:    vmul.vx v8, v8, a0
525; RV64-NEXT:    vsrl.vi v8, v8, 24
526; RV64-NEXT:    ret
527  %a = call <vscale x 1 x i32> @llvm.ctpop.nxv1i32(<vscale x 1 x i32> %va)
528  ret <vscale x 1 x i32> %a
529}
530declare <vscale x 1 x i32> @llvm.ctpop.nxv1i32(<vscale x 1 x i32>)
531
532define <vscale x 2 x i32> @ctpop_nxv2i32(<vscale x 2 x i32> %va) {
533; RV32-LABEL: ctpop_nxv2i32:
534; RV32:       # %bb.0:
535; RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
536; RV32-NEXT:    vsrl.vi v9, v8, 1
537; RV32-NEXT:    lui a0, 349525
538; RV32-NEXT:    addi a0, a0, 1365
539; RV32-NEXT:    vand.vx v9, v9, a0
540; RV32-NEXT:    vsub.vv v8, v8, v9
541; RV32-NEXT:    lui a0, 209715
542; RV32-NEXT:    addi a0, a0, 819
543; RV32-NEXT:    vand.vx v9, v8, a0
544; RV32-NEXT:    vsrl.vi v8, v8, 2
545; RV32-NEXT:    vand.vx v8, v8, a0
546; RV32-NEXT:    vadd.vv v8, v9, v8
547; RV32-NEXT:    vsrl.vi v9, v8, 4
548; RV32-NEXT:    vadd.vv v8, v8, v9
549; RV32-NEXT:    lui a0, 61681
550; RV32-NEXT:    addi a0, a0, -241
551; RV32-NEXT:    vand.vx v8, v8, a0
552; RV32-NEXT:    lui a0, 4112
553; RV32-NEXT:    addi a0, a0, 257
554; RV32-NEXT:    vmul.vx v8, v8, a0
555; RV32-NEXT:    vsrl.vi v8, v8, 24
556; RV32-NEXT:    ret
557;
558; RV64-LABEL: ctpop_nxv2i32:
559; RV64:       # %bb.0:
560; RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
561; RV64-NEXT:    vsrl.vi v9, v8, 1
562; RV64-NEXT:    lui a0, 349525
563; RV64-NEXT:    addiw a0, a0, 1365
564; RV64-NEXT:    vand.vx v9, v9, a0
565; RV64-NEXT:    vsub.vv v8, v8, v9
566; RV64-NEXT:    lui a0, 209715
567; RV64-NEXT:    addiw a0, a0, 819
568; RV64-NEXT:    vand.vx v9, v8, a0
569; RV64-NEXT:    vsrl.vi v8, v8, 2
570; RV64-NEXT:    vand.vx v8, v8, a0
571; RV64-NEXT:    vadd.vv v8, v9, v8
572; RV64-NEXT:    vsrl.vi v9, v8, 4
573; RV64-NEXT:    vadd.vv v8, v8, v9
574; RV64-NEXT:    lui a0, 61681
575; RV64-NEXT:    addiw a0, a0, -241
576; RV64-NEXT:    vand.vx v8, v8, a0
577; RV64-NEXT:    lui a0, 4112
578; RV64-NEXT:    addiw a0, a0, 257
579; RV64-NEXT:    vmul.vx v8, v8, a0
580; RV64-NEXT:    vsrl.vi v8, v8, 24
581; RV64-NEXT:    ret
582  %a = call <vscale x 2 x i32> @llvm.ctpop.nxv2i32(<vscale x 2 x i32> %va)
583  ret <vscale x 2 x i32> %a
584}
585declare <vscale x 2 x i32> @llvm.ctpop.nxv2i32(<vscale x 2 x i32>)
586
587define <vscale x 4 x i32> @ctpop_nxv4i32(<vscale x 4 x i32> %va) {
588; RV32-LABEL: ctpop_nxv4i32:
589; RV32:       # %bb.0:
590; RV32-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
591; RV32-NEXT:    vsrl.vi v10, v8, 1
592; RV32-NEXT:    lui a0, 349525
593; RV32-NEXT:    addi a0, a0, 1365
594; RV32-NEXT:    vand.vx v10, v10, a0
595; RV32-NEXT:    vsub.vv v8, v8, v10
596; RV32-NEXT:    lui a0, 209715
597; RV32-NEXT:    addi a0, a0, 819
598; RV32-NEXT:    vand.vx v10, v8, a0
599; RV32-NEXT:    vsrl.vi v8, v8, 2
600; RV32-NEXT:    vand.vx v8, v8, a0
601; RV32-NEXT:    vadd.vv v8, v10, v8
602; RV32-NEXT:    vsrl.vi v10, v8, 4
603; RV32-NEXT:    vadd.vv v8, v8, v10
604; RV32-NEXT:    lui a0, 61681
605; RV32-NEXT:    addi a0, a0, -241
606; RV32-NEXT:    vand.vx v8, v8, a0
607; RV32-NEXT:    lui a0, 4112
608; RV32-NEXT:    addi a0, a0, 257
609; RV32-NEXT:    vmul.vx v8, v8, a0
610; RV32-NEXT:    vsrl.vi v8, v8, 24
611; RV32-NEXT:    ret
612;
613; RV64-LABEL: ctpop_nxv4i32:
614; RV64:       # %bb.0:
615; RV64-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
616; RV64-NEXT:    vsrl.vi v10, v8, 1
617; RV64-NEXT:    lui a0, 349525
618; RV64-NEXT:    addiw a0, a0, 1365
619; RV64-NEXT:    vand.vx v10, v10, a0
620; RV64-NEXT:    vsub.vv v8, v8, v10
621; RV64-NEXT:    lui a0, 209715
622; RV64-NEXT:    addiw a0, a0, 819
623; RV64-NEXT:    vand.vx v10, v8, a0
624; RV64-NEXT:    vsrl.vi v8, v8, 2
625; RV64-NEXT:    vand.vx v8, v8, a0
626; RV64-NEXT:    vadd.vv v8, v10, v8
627; RV64-NEXT:    vsrl.vi v10, v8, 4
628; RV64-NEXT:    vadd.vv v8, v8, v10
629; RV64-NEXT:    lui a0, 61681
630; RV64-NEXT:    addiw a0, a0, -241
631; RV64-NEXT:    vand.vx v8, v8, a0
632; RV64-NEXT:    lui a0, 4112
633; RV64-NEXT:    addiw a0, a0, 257
634; RV64-NEXT:    vmul.vx v8, v8, a0
635; RV64-NEXT:    vsrl.vi v8, v8, 24
636; RV64-NEXT:    ret
637  %a = call <vscale x 4 x i32> @llvm.ctpop.nxv4i32(<vscale x 4 x i32> %va)
638  ret <vscale x 4 x i32> %a
639}
640declare <vscale x 4 x i32> @llvm.ctpop.nxv4i32(<vscale x 4 x i32>)
641
642define <vscale x 8 x i32> @ctpop_nxv8i32(<vscale x 8 x i32> %va) {
643; RV32-LABEL: ctpop_nxv8i32:
644; RV32:       # %bb.0:
645; RV32-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
646; RV32-NEXT:    vsrl.vi v12, v8, 1
647; RV32-NEXT:    lui a0, 349525
648; RV32-NEXT:    addi a0, a0, 1365
649; RV32-NEXT:    vand.vx v12, v12, a0
650; RV32-NEXT:    vsub.vv v8, v8, v12
651; RV32-NEXT:    lui a0, 209715
652; RV32-NEXT:    addi a0, a0, 819
653; RV32-NEXT:    vand.vx v12, v8, a0
654; RV32-NEXT:    vsrl.vi v8, v8, 2
655; RV32-NEXT:    vand.vx v8, v8, a0
656; RV32-NEXT:    vadd.vv v8, v12, v8
657; RV32-NEXT:    vsrl.vi v12, v8, 4
658; RV32-NEXT:    vadd.vv v8, v8, v12
659; RV32-NEXT:    lui a0, 61681
660; RV32-NEXT:    addi a0, a0, -241
661; RV32-NEXT:    vand.vx v8, v8, a0
662; RV32-NEXT:    lui a0, 4112
663; RV32-NEXT:    addi a0, a0, 257
664; RV32-NEXT:    vmul.vx v8, v8, a0
665; RV32-NEXT:    vsrl.vi v8, v8, 24
666; RV32-NEXT:    ret
667;
668; RV64-LABEL: ctpop_nxv8i32:
669; RV64:       # %bb.0:
670; RV64-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
671; RV64-NEXT:    vsrl.vi v12, v8, 1
672; RV64-NEXT:    lui a0, 349525
673; RV64-NEXT:    addiw a0, a0, 1365
674; RV64-NEXT:    vand.vx v12, v12, a0
675; RV64-NEXT:    vsub.vv v8, v8, v12
676; RV64-NEXT:    lui a0, 209715
677; RV64-NEXT:    addiw a0, a0, 819
678; RV64-NEXT:    vand.vx v12, v8, a0
679; RV64-NEXT:    vsrl.vi v8, v8, 2
680; RV64-NEXT:    vand.vx v8, v8, a0
681; RV64-NEXT:    vadd.vv v8, v12, v8
682; RV64-NEXT:    vsrl.vi v12, v8, 4
683; RV64-NEXT:    vadd.vv v8, v8, v12
684; RV64-NEXT:    lui a0, 61681
685; RV64-NEXT:    addiw a0, a0, -241
686; RV64-NEXT:    vand.vx v8, v8, a0
687; RV64-NEXT:    lui a0, 4112
688; RV64-NEXT:    addiw a0, a0, 257
689; RV64-NEXT:    vmul.vx v8, v8, a0
690; RV64-NEXT:    vsrl.vi v8, v8, 24
691; RV64-NEXT:    ret
692  %a = call <vscale x 8 x i32> @llvm.ctpop.nxv8i32(<vscale x 8 x i32> %va)
693  ret <vscale x 8 x i32> %a
694}
695declare <vscale x 8 x i32> @llvm.ctpop.nxv8i32(<vscale x 8 x i32>)
696
697define <vscale x 16 x i32> @ctpop_nxv16i32(<vscale x 16 x i32> %va) {
698; RV32-LABEL: ctpop_nxv16i32:
699; RV32:       # %bb.0:
700; RV32-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
701; RV32-NEXT:    vsrl.vi v16, v8, 1
702; RV32-NEXT:    lui a0, 349525
703; RV32-NEXT:    addi a0, a0, 1365
704; RV32-NEXT:    vand.vx v16, v16, a0
705; RV32-NEXT:    vsub.vv v8, v8, v16
706; RV32-NEXT:    lui a0, 209715
707; RV32-NEXT:    addi a0, a0, 819
708; RV32-NEXT:    vand.vx v16, v8, a0
709; RV32-NEXT:    vsrl.vi v8, v8, 2
710; RV32-NEXT:    vand.vx v8, v8, a0
711; RV32-NEXT:    vadd.vv v8, v16, v8
712; RV32-NEXT:    vsrl.vi v16, v8, 4
713; RV32-NEXT:    vadd.vv v8, v8, v16
714; RV32-NEXT:    lui a0, 61681
715; RV32-NEXT:    addi a0, a0, -241
716; RV32-NEXT:    vand.vx v8, v8, a0
717; RV32-NEXT:    lui a0, 4112
718; RV32-NEXT:    addi a0, a0, 257
719; RV32-NEXT:    vmul.vx v8, v8, a0
720; RV32-NEXT:    vsrl.vi v8, v8, 24
721; RV32-NEXT:    ret
722;
723; RV64-LABEL: ctpop_nxv16i32:
724; RV64:       # %bb.0:
725; RV64-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
726; RV64-NEXT:    vsrl.vi v16, v8, 1
727; RV64-NEXT:    lui a0, 349525
728; RV64-NEXT:    addiw a0, a0, 1365
729; RV64-NEXT:    vand.vx v16, v16, a0
730; RV64-NEXT:    vsub.vv v8, v8, v16
731; RV64-NEXT:    lui a0, 209715
732; RV64-NEXT:    addiw a0, a0, 819
733; RV64-NEXT:    vand.vx v16, v8, a0
734; RV64-NEXT:    vsrl.vi v8, v8, 2
735; RV64-NEXT:    vand.vx v8, v8, a0
736; RV64-NEXT:    vadd.vv v8, v16, v8
737; RV64-NEXT:    vsrl.vi v16, v8, 4
738; RV64-NEXT:    vadd.vv v8, v8, v16
739; RV64-NEXT:    lui a0, 61681
740; RV64-NEXT:    addiw a0, a0, -241
741; RV64-NEXT:    vand.vx v8, v8, a0
742; RV64-NEXT:    lui a0, 4112
743; RV64-NEXT:    addiw a0, a0, 257
744; RV64-NEXT:    vmul.vx v8, v8, a0
745; RV64-NEXT:    vsrl.vi v8, v8, 24
746; RV64-NEXT:    ret
747  %a = call <vscale x 16 x i32> @llvm.ctpop.nxv16i32(<vscale x 16 x i32> %va)
748  ret <vscale x 16 x i32> %a
749}
750declare <vscale x 16 x i32> @llvm.ctpop.nxv16i32(<vscale x 16 x i32>)
751
752define <vscale x 1 x i64> @ctpop_nxv1i64(<vscale x 1 x i64> %va) {
753; RV32-LABEL: ctpop_nxv1i64:
754; RV32:       # %bb.0:
755; RV32-NEXT:    addi sp, sp, -16
756; RV32-NEXT:    .cfi_def_cfa_offset 16
757; RV32-NEXT:    lui a0, 349525
758; RV32-NEXT:    addi a0, a0, 1365
759; RV32-NEXT:    sw a0, 12(sp)
760; RV32-NEXT:    sw a0, 8(sp)
761; RV32-NEXT:    lui a0, 209715
762; RV32-NEXT:    addi a0, a0, 819
763; RV32-NEXT:    sw a0, 12(sp)
764; RV32-NEXT:    sw a0, 8(sp)
765; RV32-NEXT:    lui a0, 61681
766; RV32-NEXT:    addi a0, a0, -241
767; RV32-NEXT:    sw a0, 12(sp)
768; RV32-NEXT:    sw a0, 8(sp)
769; RV32-NEXT:    lui a0, 4112
770; RV32-NEXT:    addi a0, a0, 257
771; RV32-NEXT:    sw a0, 12(sp)
772; RV32-NEXT:    sw a0, 8(sp)
773; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
774; RV32-NEXT:    addi a0, sp, 8
775; RV32-NEXT:    vlse64.v v9, (a0), zero
776; RV32-NEXT:    addi a0, sp, 8
777; RV32-NEXT:    vlse64.v v10, (a0), zero
778; RV32-NEXT:    vsrl.vi v11, v8, 1
779; RV32-NEXT:    vand.vv v9, v11, v9
780; RV32-NEXT:    vsub.vv v8, v8, v9
781; RV32-NEXT:    vand.vv v9, v8, v10
782; RV32-NEXT:    vsrl.vi v8, v8, 2
783; RV32-NEXT:    vand.vv v8, v8, v10
784; RV32-NEXT:    vadd.vv v8, v9, v8
785; RV32-NEXT:    addi a0, sp, 8
786; RV32-NEXT:    vlse64.v v9, (a0), zero
787; RV32-NEXT:    addi a0, sp, 8
788; RV32-NEXT:    vlse64.v v10, (a0), zero
789; RV32-NEXT:    vsrl.vi v11, v8, 4
790; RV32-NEXT:    vadd.vv v8, v8, v11
791; RV32-NEXT:    vand.vv v8, v8, v9
792; RV32-NEXT:    vmul.vv v8, v8, v10
793; RV32-NEXT:    addi a0, zero, 56
794; RV32-NEXT:    vsrl.vx v8, v8, a0
795; RV32-NEXT:    addi sp, sp, 16
796; RV32-NEXT:    ret
797;
798; RV64-LABEL: ctpop_nxv1i64:
799; RV64:       # %bb.0:
800; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
801; RV64-NEXT:    vsrl.vi v9, v8, 1
802; RV64-NEXT:    lui a0, 21845
803; RV64-NEXT:    addiw a0, a0, 1365
804; RV64-NEXT:    slli a0, a0, 12
805; RV64-NEXT:    addi a0, a0, 1365
806; RV64-NEXT:    slli a0, a0, 12
807; RV64-NEXT:    addi a0, a0, 1365
808; RV64-NEXT:    slli a0, a0, 12
809; RV64-NEXT:    addi a0, a0, 1365
810; RV64-NEXT:    vand.vx v9, v9, a0
811; RV64-NEXT:    vsub.vv v8, v8, v9
812; RV64-NEXT:    lui a0, 13107
813; RV64-NEXT:    addiw a0, a0, 819
814; RV64-NEXT:    slli a0, a0, 12
815; RV64-NEXT:    addi a0, a0, 819
816; RV64-NEXT:    slli a0, a0, 12
817; RV64-NEXT:    addi a0, a0, 819
818; RV64-NEXT:    slli a0, a0, 12
819; RV64-NEXT:    addi a0, a0, 819
820; RV64-NEXT:    vand.vx v9, v8, a0
821; RV64-NEXT:    vsrl.vi v8, v8, 2
822; RV64-NEXT:    vand.vx v8, v8, a0
823; RV64-NEXT:    vadd.vv v8, v9, v8
824; RV64-NEXT:    vsrl.vi v9, v8, 4
825; RV64-NEXT:    vadd.vv v8, v8, v9
826; RV64-NEXT:    lui a0, 3855
827; RV64-NEXT:    addiw a0, a0, 241
828; RV64-NEXT:    slli a0, a0, 12
829; RV64-NEXT:    addi a0, a0, -241
830; RV64-NEXT:    slli a0, a0, 12
831; RV64-NEXT:    addi a0, a0, 241
832; RV64-NEXT:    slli a0, a0, 12
833; RV64-NEXT:    addi a0, a0, -241
834; RV64-NEXT:    vand.vx v8, v8, a0
835; RV64-NEXT:    lui a0, 4112
836; RV64-NEXT:    addiw a0, a0, 257
837; RV64-NEXT:    slli a0, a0, 16
838; RV64-NEXT:    addi a0, a0, 257
839; RV64-NEXT:    slli a0, a0, 16
840; RV64-NEXT:    addi a0, a0, 257
841; RV64-NEXT:    vmul.vx v8, v8, a0
842; RV64-NEXT:    addi a0, zero, 56
843; RV64-NEXT:    vsrl.vx v8, v8, a0
844; RV64-NEXT:    ret
845  %a = call <vscale x 1 x i64> @llvm.ctpop.nxv1i64(<vscale x 1 x i64> %va)
846  ret <vscale x 1 x i64> %a
847}
848declare <vscale x 1 x i64> @llvm.ctpop.nxv1i64(<vscale x 1 x i64>)
849
850define <vscale x 2 x i64> @ctpop_nxv2i64(<vscale x 2 x i64> %va) {
851; RV32-LABEL: ctpop_nxv2i64:
852; RV32:       # %bb.0:
853; RV32-NEXT:    addi sp, sp, -16
854; RV32-NEXT:    .cfi_def_cfa_offset 16
855; RV32-NEXT:    lui a0, 349525
856; RV32-NEXT:    addi a0, a0, 1365
857; RV32-NEXT:    sw a0, 12(sp)
858; RV32-NEXT:    sw a0, 8(sp)
859; RV32-NEXT:    lui a0, 209715
860; RV32-NEXT:    addi a0, a0, 819
861; RV32-NEXT:    sw a0, 12(sp)
862; RV32-NEXT:    sw a0, 8(sp)
863; RV32-NEXT:    lui a0, 61681
864; RV32-NEXT:    addi a0, a0, -241
865; RV32-NEXT:    sw a0, 12(sp)
866; RV32-NEXT:    sw a0, 8(sp)
867; RV32-NEXT:    lui a0, 4112
868; RV32-NEXT:    addi a0, a0, 257
869; RV32-NEXT:    sw a0, 12(sp)
870; RV32-NEXT:    sw a0, 8(sp)
871; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
872; RV32-NEXT:    addi a0, sp, 8
873; RV32-NEXT:    vlse64.v v10, (a0), zero
874; RV32-NEXT:    addi a0, sp, 8
875; RV32-NEXT:    vlse64.v v12, (a0), zero
876; RV32-NEXT:    vsrl.vi v14, v8, 1
877; RV32-NEXT:    vand.vv v10, v14, v10
878; RV32-NEXT:    vsub.vv v8, v8, v10
879; RV32-NEXT:    vand.vv v10, v8, v12
880; RV32-NEXT:    vsrl.vi v8, v8, 2
881; RV32-NEXT:    vand.vv v8, v8, v12
882; RV32-NEXT:    vadd.vv v8, v10, v8
883; RV32-NEXT:    addi a0, sp, 8
884; RV32-NEXT:    vlse64.v v10, (a0), zero
885; RV32-NEXT:    addi a0, sp, 8
886; RV32-NEXT:    vlse64.v v12, (a0), zero
887; RV32-NEXT:    vsrl.vi v14, v8, 4
888; RV32-NEXT:    vadd.vv v8, v8, v14
889; RV32-NEXT:    vand.vv v8, v8, v10
890; RV32-NEXT:    vmul.vv v8, v8, v12
891; RV32-NEXT:    addi a0, zero, 56
892; RV32-NEXT:    vsrl.vx v8, v8, a0
893; RV32-NEXT:    addi sp, sp, 16
894; RV32-NEXT:    ret
895;
896; RV64-LABEL: ctpop_nxv2i64:
897; RV64:       # %bb.0:
898; RV64-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
899; RV64-NEXT:    vsrl.vi v10, v8, 1
900; RV64-NEXT:    lui a0, 21845
901; RV64-NEXT:    addiw a0, a0, 1365
902; RV64-NEXT:    slli a0, a0, 12
903; RV64-NEXT:    addi a0, a0, 1365
904; RV64-NEXT:    slli a0, a0, 12
905; RV64-NEXT:    addi a0, a0, 1365
906; RV64-NEXT:    slli a0, a0, 12
907; RV64-NEXT:    addi a0, a0, 1365
908; RV64-NEXT:    vand.vx v10, v10, a0
909; RV64-NEXT:    vsub.vv v8, v8, v10
910; RV64-NEXT:    lui a0, 13107
911; RV64-NEXT:    addiw a0, a0, 819
912; RV64-NEXT:    slli a0, a0, 12
913; RV64-NEXT:    addi a0, a0, 819
914; RV64-NEXT:    slli a0, a0, 12
915; RV64-NEXT:    addi a0, a0, 819
916; RV64-NEXT:    slli a0, a0, 12
917; RV64-NEXT:    addi a0, a0, 819
918; RV64-NEXT:    vand.vx v10, v8, a0
919; RV64-NEXT:    vsrl.vi v8, v8, 2
920; RV64-NEXT:    vand.vx v8, v8, a0
921; RV64-NEXT:    vadd.vv v8, v10, v8
922; RV64-NEXT:    vsrl.vi v10, v8, 4
923; RV64-NEXT:    vadd.vv v8, v8, v10
924; RV64-NEXT:    lui a0, 3855
925; RV64-NEXT:    addiw a0, a0, 241
926; RV64-NEXT:    slli a0, a0, 12
927; RV64-NEXT:    addi a0, a0, -241
928; RV64-NEXT:    slli a0, a0, 12
929; RV64-NEXT:    addi a0, a0, 241
930; RV64-NEXT:    slli a0, a0, 12
931; RV64-NEXT:    addi a0, a0, -241
932; RV64-NEXT:    vand.vx v8, v8, a0
933; RV64-NEXT:    lui a0, 4112
934; RV64-NEXT:    addiw a0, a0, 257
935; RV64-NEXT:    slli a0, a0, 16
936; RV64-NEXT:    addi a0, a0, 257
937; RV64-NEXT:    slli a0, a0, 16
938; RV64-NEXT:    addi a0, a0, 257
939; RV64-NEXT:    vmul.vx v8, v8, a0
940; RV64-NEXT:    addi a0, zero, 56
941; RV64-NEXT:    vsrl.vx v8, v8, a0
942; RV64-NEXT:    ret
943  %a = call <vscale x 2 x i64> @llvm.ctpop.nxv2i64(<vscale x 2 x i64> %va)
944  ret <vscale x 2 x i64> %a
945}
946declare <vscale x 2 x i64> @llvm.ctpop.nxv2i64(<vscale x 2 x i64>)
947
948define <vscale x 4 x i64> @ctpop_nxv4i64(<vscale x 4 x i64> %va) {
949; RV32-LABEL: ctpop_nxv4i64:
950; RV32:       # %bb.0:
951; RV32-NEXT:    addi sp, sp, -16
952; RV32-NEXT:    .cfi_def_cfa_offset 16
953; RV32-NEXT:    lui a0, 349525
954; RV32-NEXT:    addi a0, a0, 1365
955; RV32-NEXT:    sw a0, 12(sp)
956; RV32-NEXT:    sw a0, 8(sp)
957; RV32-NEXT:    lui a0, 209715
958; RV32-NEXT:    addi a0, a0, 819
959; RV32-NEXT:    sw a0, 12(sp)
960; RV32-NEXT:    sw a0, 8(sp)
961; RV32-NEXT:    lui a0, 61681
962; RV32-NEXT:    addi a0, a0, -241
963; RV32-NEXT:    sw a0, 12(sp)
964; RV32-NEXT:    sw a0, 8(sp)
965; RV32-NEXT:    lui a0, 4112
966; RV32-NEXT:    addi a0, a0, 257
967; RV32-NEXT:    sw a0, 12(sp)
968; RV32-NEXT:    sw a0, 8(sp)
969; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
970; RV32-NEXT:    addi a0, sp, 8
971; RV32-NEXT:    vlse64.v v12, (a0), zero
972; RV32-NEXT:    addi a0, sp, 8
973; RV32-NEXT:    vlse64.v v16, (a0), zero
974; RV32-NEXT:    vsrl.vi v20, v8, 1
975; RV32-NEXT:    vand.vv v12, v20, v12
976; RV32-NEXT:    vsub.vv v8, v8, v12
977; RV32-NEXT:    vand.vv v12, v8, v16
978; RV32-NEXT:    vsrl.vi v8, v8, 2
979; RV32-NEXT:    vand.vv v8, v8, v16
980; RV32-NEXT:    vadd.vv v8, v12, v8
981; RV32-NEXT:    addi a0, sp, 8
982; RV32-NEXT:    vlse64.v v12, (a0), zero
983; RV32-NEXT:    addi a0, sp, 8
984; RV32-NEXT:    vlse64.v v16, (a0), zero
985; RV32-NEXT:    vsrl.vi v20, v8, 4
986; RV32-NEXT:    vadd.vv v8, v8, v20
987; RV32-NEXT:    vand.vv v8, v8, v12
988; RV32-NEXT:    vmul.vv v8, v8, v16
989; RV32-NEXT:    addi a0, zero, 56
990; RV32-NEXT:    vsrl.vx v8, v8, a0
991; RV32-NEXT:    addi sp, sp, 16
992; RV32-NEXT:    ret
993;
994; RV64-LABEL: ctpop_nxv4i64:
995; RV64:       # %bb.0:
996; RV64-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
997; RV64-NEXT:    vsrl.vi v12, v8, 1
998; RV64-NEXT:    lui a0, 21845
999; RV64-NEXT:    addiw a0, a0, 1365
1000; RV64-NEXT:    slli a0, a0, 12
1001; RV64-NEXT:    addi a0, a0, 1365
1002; RV64-NEXT:    slli a0, a0, 12
1003; RV64-NEXT:    addi a0, a0, 1365
1004; RV64-NEXT:    slli a0, a0, 12
1005; RV64-NEXT:    addi a0, a0, 1365
1006; RV64-NEXT:    vand.vx v12, v12, a0
1007; RV64-NEXT:    vsub.vv v8, v8, v12
1008; RV64-NEXT:    lui a0, 13107
1009; RV64-NEXT:    addiw a0, a0, 819
1010; RV64-NEXT:    slli a0, a0, 12
1011; RV64-NEXT:    addi a0, a0, 819
1012; RV64-NEXT:    slli a0, a0, 12
1013; RV64-NEXT:    addi a0, a0, 819
1014; RV64-NEXT:    slli a0, a0, 12
1015; RV64-NEXT:    addi a0, a0, 819
1016; RV64-NEXT:    vand.vx v12, v8, a0
1017; RV64-NEXT:    vsrl.vi v8, v8, 2
1018; RV64-NEXT:    vand.vx v8, v8, a0
1019; RV64-NEXT:    vadd.vv v8, v12, v8
1020; RV64-NEXT:    vsrl.vi v12, v8, 4
1021; RV64-NEXT:    vadd.vv v8, v8, v12
1022; RV64-NEXT:    lui a0, 3855
1023; RV64-NEXT:    addiw a0, a0, 241
1024; RV64-NEXT:    slli a0, a0, 12
1025; RV64-NEXT:    addi a0, a0, -241
1026; RV64-NEXT:    slli a0, a0, 12
1027; RV64-NEXT:    addi a0, a0, 241
1028; RV64-NEXT:    slli a0, a0, 12
1029; RV64-NEXT:    addi a0, a0, -241
1030; RV64-NEXT:    vand.vx v8, v8, a0
1031; RV64-NEXT:    lui a0, 4112
1032; RV64-NEXT:    addiw a0, a0, 257
1033; RV64-NEXT:    slli a0, a0, 16
1034; RV64-NEXT:    addi a0, a0, 257
1035; RV64-NEXT:    slli a0, a0, 16
1036; RV64-NEXT:    addi a0, a0, 257
1037; RV64-NEXT:    vmul.vx v8, v8, a0
1038; RV64-NEXT:    addi a0, zero, 56
1039; RV64-NEXT:    vsrl.vx v8, v8, a0
1040; RV64-NEXT:    ret
1041  %a = call <vscale x 4 x i64> @llvm.ctpop.nxv4i64(<vscale x 4 x i64> %va)
1042  ret <vscale x 4 x i64> %a
1043}
1044declare <vscale x 4 x i64> @llvm.ctpop.nxv4i64(<vscale x 4 x i64>)
1045
1046define <vscale x 8 x i64> @ctpop_nxv8i64(<vscale x 8 x i64> %va) {
1047; RV32-LABEL: ctpop_nxv8i64:
1048; RV32:       # %bb.0:
1049; RV32-NEXT:    addi sp, sp, -16
1050; RV32-NEXT:    .cfi_def_cfa_offset 16
1051; RV32-NEXT:    lui a0, 349525
1052; RV32-NEXT:    addi a0, a0, 1365
1053; RV32-NEXT:    sw a0, 12(sp)
1054; RV32-NEXT:    sw a0, 8(sp)
1055; RV32-NEXT:    lui a0, 209715
1056; RV32-NEXT:    addi a0, a0, 819
1057; RV32-NEXT:    sw a0, 12(sp)
1058; RV32-NEXT:    sw a0, 8(sp)
1059; RV32-NEXT:    lui a0, 61681
1060; RV32-NEXT:    addi a0, a0, -241
1061; RV32-NEXT:    sw a0, 12(sp)
1062; RV32-NEXT:    sw a0, 8(sp)
1063; RV32-NEXT:    lui a0, 4112
1064; RV32-NEXT:    addi a0, a0, 257
1065; RV32-NEXT:    sw a0, 12(sp)
1066; RV32-NEXT:    sw a0, 8(sp)
1067; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
1068; RV32-NEXT:    addi a0, sp, 8
1069; RV32-NEXT:    vlse64.v v16, (a0), zero
1070; RV32-NEXT:    addi a0, sp, 8
1071; RV32-NEXT:    vlse64.v v24, (a0), zero
1072; RV32-NEXT:    vsrl.vi v0, v8, 1
1073; RV32-NEXT:    vand.vv v16, v0, v16
1074; RV32-NEXT:    vsub.vv v8, v8, v16
1075; RV32-NEXT:    vand.vv v16, v8, v24
1076; RV32-NEXT:    vsrl.vi v8, v8, 2
1077; RV32-NEXT:    vand.vv v8, v8, v24
1078; RV32-NEXT:    vadd.vv v8, v16, v8
1079; RV32-NEXT:    addi a0, sp, 8
1080; RV32-NEXT:    vlse64.v v16, (a0), zero
1081; RV32-NEXT:    addi a0, sp, 8
1082; RV32-NEXT:    vlse64.v v24, (a0), zero
1083; RV32-NEXT:    vsrl.vi v0, v8, 4
1084; RV32-NEXT:    vadd.vv v8, v8, v0
1085; RV32-NEXT:    vand.vv v8, v8, v16
1086; RV32-NEXT:    vmul.vv v8, v8, v24
1087; RV32-NEXT:    addi a0, zero, 56
1088; RV32-NEXT:    vsrl.vx v8, v8, a0
1089; RV32-NEXT:    addi sp, sp, 16
1090; RV32-NEXT:    ret
1091;
1092; RV64-LABEL: ctpop_nxv8i64:
1093; RV64:       # %bb.0:
1094; RV64-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
1095; RV64-NEXT:    vsrl.vi v16, v8, 1
1096; RV64-NEXT:    lui a0, 21845
1097; RV64-NEXT:    addiw a0, a0, 1365
1098; RV64-NEXT:    slli a0, a0, 12
1099; RV64-NEXT:    addi a0, a0, 1365
1100; RV64-NEXT:    slli a0, a0, 12
1101; RV64-NEXT:    addi a0, a0, 1365
1102; RV64-NEXT:    slli a0, a0, 12
1103; RV64-NEXT:    addi a0, a0, 1365
1104; RV64-NEXT:    vand.vx v16, v16, a0
1105; RV64-NEXT:    vsub.vv v8, v8, v16
1106; RV64-NEXT:    lui a0, 13107
1107; RV64-NEXT:    addiw a0, a0, 819
1108; RV64-NEXT:    slli a0, a0, 12
1109; RV64-NEXT:    addi a0, a0, 819
1110; RV64-NEXT:    slli a0, a0, 12
1111; RV64-NEXT:    addi a0, a0, 819
1112; RV64-NEXT:    slli a0, a0, 12
1113; RV64-NEXT:    addi a0, a0, 819
1114; RV64-NEXT:    vand.vx v16, v8, a0
1115; RV64-NEXT:    vsrl.vi v8, v8, 2
1116; RV64-NEXT:    vand.vx v8, v8, a0
1117; RV64-NEXT:    vadd.vv v8, v16, v8
1118; RV64-NEXT:    vsrl.vi v16, v8, 4
1119; RV64-NEXT:    vadd.vv v8, v8, v16
1120; RV64-NEXT:    lui a0, 3855
1121; RV64-NEXT:    addiw a0, a0, 241
1122; RV64-NEXT:    slli a0, a0, 12
1123; RV64-NEXT:    addi a0, a0, -241
1124; RV64-NEXT:    slli a0, a0, 12
1125; RV64-NEXT:    addi a0, a0, 241
1126; RV64-NEXT:    slli a0, a0, 12
1127; RV64-NEXT:    addi a0, a0, -241
1128; RV64-NEXT:    vand.vx v8, v8, a0
1129; RV64-NEXT:    lui a0, 4112
1130; RV64-NEXT:    addiw a0, a0, 257
1131; RV64-NEXT:    slli a0, a0, 16
1132; RV64-NEXT:    addi a0, a0, 257
1133; RV64-NEXT:    slli a0, a0, 16
1134; RV64-NEXT:    addi a0, a0, 257
1135; RV64-NEXT:    vmul.vx v8, v8, a0
1136; RV64-NEXT:    addi a0, zero, 56
1137; RV64-NEXT:    vsrl.vx v8, v8, a0
1138; RV64-NEXT:    ret
1139  %a = call <vscale x 8 x i64> @llvm.ctpop.nxv8i64(<vscale x 8 x i64> %va)
1140  ret <vscale x 8 x i64> %a
1141}
1142declare <vscale x 8 x i64> @llvm.ctpop.nxv8i64(<vscale x 8 x i64>)
1143