1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
4
5define <vscale x 1 x i16> @bswap_nxv1i16(<vscale x 1 x i16> %va) {
6; CHECK-LABEL: bswap_nxv1i16:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
9; CHECK-NEXT:    vsrl.vi v9, v8, 8
10; CHECK-NEXT:    vsll.vi v8, v8, 8
11; CHECK-NEXT:    vor.vv v8, v8, v9
12; CHECK-NEXT:    ret
13  %a = call <vscale x 1 x i16> @llvm.bswap.nxv1i16(<vscale x 1 x i16> %va)
14  ret <vscale x 1 x i16> %a
15}
16declare <vscale x 1 x i16> @llvm.bswap.nxv1i16(<vscale x 1 x i16>)
17
18define <vscale x 2 x i16> @bswap_nxv2i16(<vscale x 2 x i16> %va) {
19; CHECK-LABEL: bswap_nxv2i16:
20; CHECK:       # %bb.0:
21; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, mu
22; CHECK-NEXT:    vsrl.vi v9, v8, 8
23; CHECK-NEXT:    vsll.vi v8, v8, 8
24; CHECK-NEXT:    vor.vv v8, v8, v9
25; CHECK-NEXT:    ret
26  %a = call <vscale x 2 x i16> @llvm.bswap.nxv2i16(<vscale x 2 x i16> %va)
27  ret <vscale x 2 x i16> %a
28}
29declare <vscale x 2 x i16> @llvm.bswap.nxv2i16(<vscale x 2 x i16>)
30
31define <vscale x 4 x i16> @bswap_nxv4i16(<vscale x 4 x i16> %va) {
32; CHECK-LABEL: bswap_nxv4i16:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, mu
35; CHECK-NEXT:    vsrl.vi v9, v8, 8
36; CHECK-NEXT:    vsll.vi v8, v8, 8
37; CHECK-NEXT:    vor.vv v8, v8, v9
38; CHECK-NEXT:    ret
39  %a = call <vscale x 4 x i16> @llvm.bswap.nxv4i16(<vscale x 4 x i16> %va)
40  ret <vscale x 4 x i16> %a
41}
42declare <vscale x 4 x i16> @llvm.bswap.nxv4i16(<vscale x 4 x i16>)
43
44define <vscale x 8 x i16> @bswap_nxv8i16(<vscale x 8 x i16> %va) {
45; CHECK-LABEL: bswap_nxv8i16:
46; CHECK:       # %bb.0:
47; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
48; CHECK-NEXT:    vsrl.vi v10, v8, 8
49; CHECK-NEXT:    vsll.vi v8, v8, 8
50; CHECK-NEXT:    vor.vv v8, v8, v10
51; CHECK-NEXT:    ret
52  %a = call <vscale x 8 x i16> @llvm.bswap.nxv8i16(<vscale x 8 x i16> %va)
53  ret <vscale x 8 x i16> %a
54}
55declare <vscale x 8 x i16> @llvm.bswap.nxv8i16(<vscale x 8 x i16>)
56
57define <vscale x 16 x i16> @bswap_nxv16i16(<vscale x 16 x i16> %va) {
58; CHECK-LABEL: bswap_nxv16i16:
59; CHECK:       # %bb.0:
60; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, mu
61; CHECK-NEXT:    vsrl.vi v12, v8, 8
62; CHECK-NEXT:    vsll.vi v8, v8, 8
63; CHECK-NEXT:    vor.vv v8, v8, v12
64; CHECK-NEXT:    ret
65  %a = call <vscale x 16 x i16> @llvm.bswap.nxv16i16(<vscale x 16 x i16> %va)
66  ret <vscale x 16 x i16> %a
67}
68declare <vscale x 16 x i16> @llvm.bswap.nxv16i16(<vscale x 16 x i16>)
69
70define <vscale x 32 x i16> @bswap_nxv32i16(<vscale x 32 x i16> %va) {
71; CHECK-LABEL: bswap_nxv32i16:
72; CHECK:       # %bb.0:
73; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, mu
74; CHECK-NEXT:    vsrl.vi v16, v8, 8
75; CHECK-NEXT:    vsll.vi v8, v8, 8
76; CHECK-NEXT:    vor.vv v8, v8, v16
77; CHECK-NEXT:    ret
78  %a = call <vscale x 32 x i16> @llvm.bswap.nxv32i16(<vscale x 32 x i16> %va)
79  ret <vscale x 32 x i16> %a
80}
81declare <vscale x 32 x i16> @llvm.bswap.nxv32i16(<vscale x 32 x i16>)
82
83define <vscale x 1 x i32> @bswap_nxv1i32(<vscale x 1 x i32> %va) {
84; RV32-LABEL: bswap_nxv1i32:
85; RV32:       # %bb.0:
86; RV32-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
87; RV32-NEXT:    vsrl.vi v9, v8, 8
88; RV32-NEXT:    lui a0, 16
89; RV32-NEXT:    addi a0, a0, -256
90; RV32-NEXT:    vand.vx v9, v9, a0
91; RV32-NEXT:    vsrl.vi v10, v8, 24
92; RV32-NEXT:    vor.vv v9, v9, v10
93; RV32-NEXT:    vsll.vi v10, v8, 8
94; RV32-NEXT:    lui a0, 4080
95; RV32-NEXT:    vand.vx v10, v10, a0
96; RV32-NEXT:    vsll.vi v8, v8, 24
97; RV32-NEXT:    vor.vv v8, v8, v10
98; RV32-NEXT:    vor.vv v8, v8, v9
99; RV32-NEXT:    ret
100;
101; RV64-LABEL: bswap_nxv1i32:
102; RV64:       # %bb.0:
103; RV64-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
104; RV64-NEXT:    vsrl.vi v9, v8, 8
105; RV64-NEXT:    lui a0, 16
106; RV64-NEXT:    addiw a0, a0, -256
107; RV64-NEXT:    vand.vx v9, v9, a0
108; RV64-NEXT:    vsrl.vi v10, v8, 24
109; RV64-NEXT:    vor.vv v9, v9, v10
110; RV64-NEXT:    vsll.vi v10, v8, 8
111; RV64-NEXT:    lui a0, 4080
112; RV64-NEXT:    vand.vx v10, v10, a0
113; RV64-NEXT:    vsll.vi v8, v8, 24
114; RV64-NEXT:    vor.vv v8, v8, v10
115; RV64-NEXT:    vor.vv v8, v8, v9
116; RV64-NEXT:    ret
117  %a = call <vscale x 1 x i32> @llvm.bswap.nxv1i32(<vscale x 1 x i32> %va)
118  ret <vscale x 1 x i32> %a
119}
120declare <vscale x 1 x i32> @llvm.bswap.nxv1i32(<vscale x 1 x i32>)
121
122define <vscale x 2 x i32> @bswap_nxv2i32(<vscale x 2 x i32> %va) {
123; RV32-LABEL: bswap_nxv2i32:
124; RV32:       # %bb.0:
125; RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
126; RV32-NEXT:    vsrl.vi v9, v8, 8
127; RV32-NEXT:    lui a0, 16
128; RV32-NEXT:    addi a0, a0, -256
129; RV32-NEXT:    vand.vx v9, v9, a0
130; RV32-NEXT:    vsrl.vi v10, v8, 24
131; RV32-NEXT:    vor.vv v9, v9, v10
132; RV32-NEXT:    vsll.vi v10, v8, 8
133; RV32-NEXT:    lui a0, 4080
134; RV32-NEXT:    vand.vx v10, v10, a0
135; RV32-NEXT:    vsll.vi v8, v8, 24
136; RV32-NEXT:    vor.vv v8, v8, v10
137; RV32-NEXT:    vor.vv v8, v8, v9
138; RV32-NEXT:    ret
139;
140; RV64-LABEL: bswap_nxv2i32:
141; RV64:       # %bb.0:
142; RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
143; RV64-NEXT:    vsrl.vi v9, v8, 8
144; RV64-NEXT:    lui a0, 16
145; RV64-NEXT:    addiw a0, a0, -256
146; RV64-NEXT:    vand.vx v9, v9, a0
147; RV64-NEXT:    vsrl.vi v10, v8, 24
148; RV64-NEXT:    vor.vv v9, v9, v10
149; RV64-NEXT:    vsll.vi v10, v8, 8
150; RV64-NEXT:    lui a0, 4080
151; RV64-NEXT:    vand.vx v10, v10, a0
152; RV64-NEXT:    vsll.vi v8, v8, 24
153; RV64-NEXT:    vor.vv v8, v8, v10
154; RV64-NEXT:    vor.vv v8, v8, v9
155; RV64-NEXT:    ret
156  %a = call <vscale x 2 x i32> @llvm.bswap.nxv2i32(<vscale x 2 x i32> %va)
157  ret <vscale x 2 x i32> %a
158}
159declare <vscale x 2 x i32> @llvm.bswap.nxv2i32(<vscale x 2 x i32>)
160
161define <vscale x 4 x i32> @bswap_nxv4i32(<vscale x 4 x i32> %va) {
162; RV32-LABEL: bswap_nxv4i32:
163; RV32:       # %bb.0:
164; RV32-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
165; RV32-NEXT:    vsrl.vi v10, v8, 8
166; RV32-NEXT:    lui a0, 16
167; RV32-NEXT:    addi a0, a0, -256
168; RV32-NEXT:    vand.vx v10, v10, a0
169; RV32-NEXT:    vsrl.vi v12, v8, 24
170; RV32-NEXT:    vor.vv v10, v10, v12
171; RV32-NEXT:    vsll.vi v12, v8, 8
172; RV32-NEXT:    lui a0, 4080
173; RV32-NEXT:    vand.vx v12, v12, a0
174; RV32-NEXT:    vsll.vi v8, v8, 24
175; RV32-NEXT:    vor.vv v8, v8, v12
176; RV32-NEXT:    vor.vv v8, v8, v10
177; RV32-NEXT:    ret
178;
179; RV64-LABEL: bswap_nxv4i32:
180; RV64:       # %bb.0:
181; RV64-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
182; RV64-NEXT:    vsrl.vi v10, v8, 8
183; RV64-NEXT:    lui a0, 16
184; RV64-NEXT:    addiw a0, a0, -256
185; RV64-NEXT:    vand.vx v10, v10, a0
186; RV64-NEXT:    vsrl.vi v12, v8, 24
187; RV64-NEXT:    vor.vv v10, v10, v12
188; RV64-NEXT:    vsll.vi v12, v8, 8
189; RV64-NEXT:    lui a0, 4080
190; RV64-NEXT:    vand.vx v12, v12, a0
191; RV64-NEXT:    vsll.vi v8, v8, 24
192; RV64-NEXT:    vor.vv v8, v8, v12
193; RV64-NEXT:    vor.vv v8, v8, v10
194; RV64-NEXT:    ret
195  %a = call <vscale x 4 x i32> @llvm.bswap.nxv4i32(<vscale x 4 x i32> %va)
196  ret <vscale x 4 x i32> %a
197}
198declare <vscale x 4 x i32> @llvm.bswap.nxv4i32(<vscale x 4 x i32>)
199
200define <vscale x 8 x i32> @bswap_nxv8i32(<vscale x 8 x i32> %va) {
201; RV32-LABEL: bswap_nxv8i32:
202; RV32:       # %bb.0:
203; RV32-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
204; RV32-NEXT:    vsrl.vi v12, v8, 8
205; RV32-NEXT:    lui a0, 16
206; RV32-NEXT:    addi a0, a0, -256
207; RV32-NEXT:    vand.vx v12, v12, a0
208; RV32-NEXT:    vsrl.vi v16, v8, 24
209; RV32-NEXT:    vor.vv v12, v12, v16
210; RV32-NEXT:    vsll.vi v16, v8, 8
211; RV32-NEXT:    lui a0, 4080
212; RV32-NEXT:    vand.vx v16, v16, a0
213; RV32-NEXT:    vsll.vi v8, v8, 24
214; RV32-NEXT:    vor.vv v8, v8, v16
215; RV32-NEXT:    vor.vv v8, v8, v12
216; RV32-NEXT:    ret
217;
218; RV64-LABEL: bswap_nxv8i32:
219; RV64:       # %bb.0:
220; RV64-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
221; RV64-NEXT:    vsrl.vi v12, v8, 8
222; RV64-NEXT:    lui a0, 16
223; RV64-NEXT:    addiw a0, a0, -256
224; RV64-NEXT:    vand.vx v12, v12, a0
225; RV64-NEXT:    vsrl.vi v16, v8, 24
226; RV64-NEXT:    vor.vv v12, v12, v16
227; RV64-NEXT:    vsll.vi v16, v8, 8
228; RV64-NEXT:    lui a0, 4080
229; RV64-NEXT:    vand.vx v16, v16, a0
230; RV64-NEXT:    vsll.vi v8, v8, 24
231; RV64-NEXT:    vor.vv v8, v8, v16
232; RV64-NEXT:    vor.vv v8, v8, v12
233; RV64-NEXT:    ret
234  %a = call <vscale x 8 x i32> @llvm.bswap.nxv8i32(<vscale x 8 x i32> %va)
235  ret <vscale x 8 x i32> %a
236}
237declare <vscale x 8 x i32> @llvm.bswap.nxv8i32(<vscale x 8 x i32>)
238
239define <vscale x 16 x i32> @bswap_nxv16i32(<vscale x 16 x i32> %va) {
240; RV32-LABEL: bswap_nxv16i32:
241; RV32:       # %bb.0:
242; RV32-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
243; RV32-NEXT:    vsrl.vi v16, v8, 8
244; RV32-NEXT:    lui a0, 16
245; RV32-NEXT:    addi a0, a0, -256
246; RV32-NEXT:    vand.vx v16, v16, a0
247; RV32-NEXT:    vsrl.vi v24, v8, 24
248; RV32-NEXT:    vor.vv v16, v16, v24
249; RV32-NEXT:    vsll.vi v24, v8, 8
250; RV32-NEXT:    lui a0, 4080
251; RV32-NEXT:    vand.vx v24, v24, a0
252; RV32-NEXT:    vsll.vi v8, v8, 24
253; RV32-NEXT:    vor.vv v8, v8, v24
254; RV32-NEXT:    vor.vv v8, v8, v16
255; RV32-NEXT:    ret
256;
257; RV64-LABEL: bswap_nxv16i32:
258; RV64:       # %bb.0:
259; RV64-NEXT:    vsetvli a0, zero, e32, m8, ta, mu
260; RV64-NEXT:    vsrl.vi v16, v8, 8
261; RV64-NEXT:    lui a0, 16
262; RV64-NEXT:    addiw a0, a0, -256
263; RV64-NEXT:    vand.vx v16, v16, a0
264; RV64-NEXT:    vsrl.vi v24, v8, 24
265; RV64-NEXT:    vor.vv v16, v16, v24
266; RV64-NEXT:    vsll.vi v24, v8, 8
267; RV64-NEXT:    lui a0, 4080
268; RV64-NEXT:    vand.vx v24, v24, a0
269; RV64-NEXT:    vsll.vi v8, v8, 24
270; RV64-NEXT:    vor.vv v8, v8, v24
271; RV64-NEXT:    vor.vv v8, v8, v16
272; RV64-NEXT:    ret
273  %a = call <vscale x 16 x i32> @llvm.bswap.nxv16i32(<vscale x 16 x i32> %va)
274  ret <vscale x 16 x i32> %a
275}
276declare <vscale x 16 x i32> @llvm.bswap.nxv16i32(<vscale x 16 x i32>)
277
278define <vscale x 1 x i64> @bswap_nxv1i64(<vscale x 1 x i64> %va) {
279; RV32-LABEL: bswap_nxv1i64:
280; RV32:       # %bb.0:
281; RV32-NEXT:    addi sp, sp, -16
282; RV32-NEXT:    .cfi_def_cfa_offset 16
283; RV32-NEXT:    sw zero, 12(sp)
284; RV32-NEXT:    lui a0, 1044480
285; RV32-NEXT:    sw a0, 8(sp)
286; RV32-NEXT:    lui a0, 4080
287; RV32-NEXT:    sw a0, 12(sp)
288; RV32-NEXT:    sw zero, 8(sp)
289; RV32-NEXT:    li a1, 255
290; RV32-NEXT:    sw a1, 12(sp)
291; RV32-NEXT:    lui a1, 16
292; RV32-NEXT:    addi a1, a1, -256
293; RV32-NEXT:    sw a1, 12(sp)
294; RV32-NEXT:    li a2, 56
295; RV32-NEXT:    vsetvli a3, zero, e64, m1, ta, mu
296; RV32-NEXT:    vsrl.vx v9, v8, a2
297; RV32-NEXT:    li a3, 40
298; RV32-NEXT:    vsrl.vx v10, v8, a3
299; RV32-NEXT:    vand.vx v10, v10, a1
300; RV32-NEXT:    vor.vv v9, v10, v9
301; RV32-NEXT:    addi a1, sp, 8
302; RV32-NEXT:    vlse64.v v10, (a1), zero
303; RV32-NEXT:    vsrl.vi v11, v8, 24
304; RV32-NEXT:    vand.vx v11, v11, a0
305; RV32-NEXT:    vsrl.vi v12, v8, 8
306; RV32-NEXT:    vand.vv v10, v12, v10
307; RV32-NEXT:    vor.vv v10, v10, v11
308; RV32-NEXT:    addi a0, sp, 8
309; RV32-NEXT:    vlse64.v v11, (a0), zero
310; RV32-NEXT:    vor.vv v9, v10, v9
311; RV32-NEXT:    vsll.vx v10, v8, a2
312; RV32-NEXT:    vsll.vx v12, v8, a3
313; RV32-NEXT:    vand.vv v11, v12, v11
314; RV32-NEXT:    addi a0, sp, 8
315; RV32-NEXT:    vlse64.v v12, (a0), zero
316; RV32-NEXT:    vor.vv v10, v10, v11
317; RV32-NEXT:    addi a0, sp, 8
318; RV32-NEXT:    vlse64.v v11, (a0), zero
319; RV32-NEXT:    vsll.vi v13, v8, 8
320; RV32-NEXT:    vand.vv v12, v13, v12
321; RV32-NEXT:    vsll.vi v8, v8, 24
322; RV32-NEXT:    vand.vv v8, v8, v11
323; RV32-NEXT:    vor.vv v8, v8, v12
324; RV32-NEXT:    vor.vv v8, v10, v8
325; RV32-NEXT:    vor.vv v8, v8, v9
326; RV32-NEXT:    addi sp, sp, 16
327; RV32-NEXT:    ret
328;
329; RV64-LABEL: bswap_nxv1i64:
330; RV64:       # %bb.0:
331; RV64-NEXT:    li a0, 56
332; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
333; RV64-NEXT:    vsrl.vx v9, v8, a0
334; RV64-NEXT:    li a1, 40
335; RV64-NEXT:    vsrl.vx v10, v8, a1
336; RV64-NEXT:    lui a2, 16
337; RV64-NEXT:    addiw a2, a2, -256
338; RV64-NEXT:    vand.vx v10, v10, a2
339; RV64-NEXT:    vor.vv v9, v10, v9
340; RV64-NEXT:    vsrl.vi v10, v8, 24
341; RV64-NEXT:    lui a2, 4080
342; RV64-NEXT:    vand.vx v10, v10, a2
343; RV64-NEXT:    vsrl.vi v11, v8, 8
344; RV64-NEXT:    li a2, 255
345; RV64-NEXT:    slli a3, a2, 24
346; RV64-NEXT:    vand.vx v11, v11, a3
347; RV64-NEXT:    vor.vv v10, v11, v10
348; RV64-NEXT:    vor.vv v9, v10, v9
349; RV64-NEXT:    vsll.vi v10, v8, 8
350; RV64-NEXT:    slli a3, a2, 32
351; RV64-NEXT:    vand.vx v10, v10, a3
352; RV64-NEXT:    vsll.vi v11, v8, 24
353; RV64-NEXT:    slli a3, a2, 40
354; RV64-NEXT:    vand.vx v11, v11, a3
355; RV64-NEXT:    vor.vv v10, v11, v10
356; RV64-NEXT:    vsll.vx v11, v8, a0
357; RV64-NEXT:    vsll.vx v8, v8, a1
358; RV64-NEXT:    slli a0, a2, 48
359; RV64-NEXT:    vand.vx v8, v8, a0
360; RV64-NEXT:    vor.vv v8, v11, v8
361; RV64-NEXT:    vor.vv v8, v8, v10
362; RV64-NEXT:    vor.vv v8, v8, v9
363; RV64-NEXT:    ret
364  %a = call <vscale x 1 x i64> @llvm.bswap.nxv1i64(<vscale x 1 x i64> %va)
365  ret <vscale x 1 x i64> %a
366}
367declare <vscale x 1 x i64> @llvm.bswap.nxv1i64(<vscale x 1 x i64>)
368
369define <vscale x 2 x i64> @bswap_nxv2i64(<vscale x 2 x i64> %va) {
370; RV32-LABEL: bswap_nxv2i64:
371; RV32:       # %bb.0:
372; RV32-NEXT:    addi sp, sp, -16
373; RV32-NEXT:    .cfi_def_cfa_offset 16
374; RV32-NEXT:    sw zero, 12(sp)
375; RV32-NEXT:    lui a0, 1044480
376; RV32-NEXT:    sw a0, 8(sp)
377; RV32-NEXT:    lui a0, 4080
378; RV32-NEXT:    sw a0, 12(sp)
379; RV32-NEXT:    sw zero, 8(sp)
380; RV32-NEXT:    li a1, 255
381; RV32-NEXT:    sw a1, 12(sp)
382; RV32-NEXT:    lui a1, 16
383; RV32-NEXT:    addi a1, a1, -256
384; RV32-NEXT:    sw a1, 12(sp)
385; RV32-NEXT:    li a2, 56
386; RV32-NEXT:    vsetvli a3, zero, e64, m2, ta, mu
387; RV32-NEXT:    vsrl.vx v10, v8, a2
388; RV32-NEXT:    li a3, 40
389; RV32-NEXT:    vsrl.vx v12, v8, a3
390; RV32-NEXT:    vand.vx v12, v12, a1
391; RV32-NEXT:    vor.vv v10, v12, v10
392; RV32-NEXT:    addi a1, sp, 8
393; RV32-NEXT:    vlse64.v v12, (a1), zero
394; RV32-NEXT:    vsrl.vi v14, v8, 24
395; RV32-NEXT:    vand.vx v14, v14, a0
396; RV32-NEXT:    vsrl.vi v16, v8, 8
397; RV32-NEXT:    vand.vv v12, v16, v12
398; RV32-NEXT:    vor.vv v12, v12, v14
399; RV32-NEXT:    addi a0, sp, 8
400; RV32-NEXT:    vlse64.v v14, (a0), zero
401; RV32-NEXT:    vor.vv v10, v12, v10
402; RV32-NEXT:    vsll.vx v12, v8, a2
403; RV32-NEXT:    vsll.vx v16, v8, a3
404; RV32-NEXT:    vand.vv v14, v16, v14
405; RV32-NEXT:    addi a0, sp, 8
406; RV32-NEXT:    vlse64.v v16, (a0), zero
407; RV32-NEXT:    vor.vv v12, v12, v14
408; RV32-NEXT:    addi a0, sp, 8
409; RV32-NEXT:    vlse64.v v14, (a0), zero
410; RV32-NEXT:    vsll.vi v18, v8, 8
411; RV32-NEXT:    vand.vv v16, v18, v16
412; RV32-NEXT:    vsll.vi v8, v8, 24
413; RV32-NEXT:    vand.vv v8, v8, v14
414; RV32-NEXT:    vor.vv v8, v8, v16
415; RV32-NEXT:    vor.vv v8, v12, v8
416; RV32-NEXT:    vor.vv v8, v8, v10
417; RV32-NEXT:    addi sp, sp, 16
418; RV32-NEXT:    ret
419;
420; RV64-LABEL: bswap_nxv2i64:
421; RV64:       # %bb.0:
422; RV64-NEXT:    li a0, 56
423; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
424; RV64-NEXT:    vsrl.vx v10, v8, a0
425; RV64-NEXT:    li a1, 40
426; RV64-NEXT:    vsrl.vx v12, v8, a1
427; RV64-NEXT:    lui a2, 16
428; RV64-NEXT:    addiw a2, a2, -256
429; RV64-NEXT:    vand.vx v12, v12, a2
430; RV64-NEXT:    vor.vv v10, v12, v10
431; RV64-NEXT:    vsrl.vi v12, v8, 24
432; RV64-NEXT:    lui a2, 4080
433; RV64-NEXT:    vand.vx v12, v12, a2
434; RV64-NEXT:    vsrl.vi v14, v8, 8
435; RV64-NEXT:    li a2, 255
436; RV64-NEXT:    slli a3, a2, 24
437; RV64-NEXT:    vand.vx v14, v14, a3
438; RV64-NEXT:    vor.vv v12, v14, v12
439; RV64-NEXT:    vor.vv v10, v12, v10
440; RV64-NEXT:    vsll.vi v12, v8, 8
441; RV64-NEXT:    slli a3, a2, 32
442; RV64-NEXT:    vand.vx v12, v12, a3
443; RV64-NEXT:    vsll.vi v14, v8, 24
444; RV64-NEXT:    slli a3, a2, 40
445; RV64-NEXT:    vand.vx v14, v14, a3
446; RV64-NEXT:    vor.vv v12, v14, v12
447; RV64-NEXT:    vsll.vx v14, v8, a0
448; RV64-NEXT:    vsll.vx v8, v8, a1
449; RV64-NEXT:    slli a0, a2, 48
450; RV64-NEXT:    vand.vx v8, v8, a0
451; RV64-NEXT:    vor.vv v8, v14, v8
452; RV64-NEXT:    vor.vv v8, v8, v12
453; RV64-NEXT:    vor.vv v8, v8, v10
454; RV64-NEXT:    ret
455  %a = call <vscale x 2 x i64> @llvm.bswap.nxv2i64(<vscale x 2 x i64> %va)
456  ret <vscale x 2 x i64> %a
457}
458declare <vscale x 2 x i64> @llvm.bswap.nxv2i64(<vscale x 2 x i64>)
459
460define <vscale x 4 x i64> @bswap_nxv4i64(<vscale x 4 x i64> %va) {
461; RV32-LABEL: bswap_nxv4i64:
462; RV32:       # %bb.0:
463; RV32-NEXT:    addi sp, sp, -16
464; RV32-NEXT:    .cfi_def_cfa_offset 16
465; RV32-NEXT:    sw zero, 12(sp)
466; RV32-NEXT:    lui a0, 1044480
467; RV32-NEXT:    sw a0, 8(sp)
468; RV32-NEXT:    lui a0, 4080
469; RV32-NEXT:    sw a0, 12(sp)
470; RV32-NEXT:    sw zero, 8(sp)
471; RV32-NEXT:    li a1, 255
472; RV32-NEXT:    sw a1, 12(sp)
473; RV32-NEXT:    lui a1, 16
474; RV32-NEXT:    addi a1, a1, -256
475; RV32-NEXT:    sw a1, 12(sp)
476; RV32-NEXT:    li a2, 56
477; RV32-NEXT:    vsetvli a3, zero, e64, m4, ta, mu
478; RV32-NEXT:    vsrl.vx v12, v8, a2
479; RV32-NEXT:    li a3, 40
480; RV32-NEXT:    vsrl.vx v16, v8, a3
481; RV32-NEXT:    vand.vx v16, v16, a1
482; RV32-NEXT:    vor.vv v12, v16, v12
483; RV32-NEXT:    addi a1, sp, 8
484; RV32-NEXT:    vlse64.v v16, (a1), zero
485; RV32-NEXT:    vsrl.vi v20, v8, 24
486; RV32-NEXT:    vand.vx v20, v20, a0
487; RV32-NEXT:    vsrl.vi v24, v8, 8
488; RV32-NEXT:    vand.vv v16, v24, v16
489; RV32-NEXT:    vor.vv v16, v16, v20
490; RV32-NEXT:    addi a0, sp, 8
491; RV32-NEXT:    vlse64.v v20, (a0), zero
492; RV32-NEXT:    vor.vv v12, v16, v12
493; RV32-NEXT:    vsll.vx v16, v8, a2
494; RV32-NEXT:    vsll.vx v24, v8, a3
495; RV32-NEXT:    vand.vv v20, v24, v20
496; RV32-NEXT:    addi a0, sp, 8
497; RV32-NEXT:    vlse64.v v24, (a0), zero
498; RV32-NEXT:    vor.vv v16, v16, v20
499; RV32-NEXT:    addi a0, sp, 8
500; RV32-NEXT:    vlse64.v v20, (a0), zero
501; RV32-NEXT:    vsll.vi v28, v8, 8
502; RV32-NEXT:    vand.vv v24, v28, v24
503; RV32-NEXT:    vsll.vi v8, v8, 24
504; RV32-NEXT:    vand.vv v8, v8, v20
505; RV32-NEXT:    vor.vv v8, v8, v24
506; RV32-NEXT:    vor.vv v8, v16, v8
507; RV32-NEXT:    vor.vv v8, v8, v12
508; RV32-NEXT:    addi sp, sp, 16
509; RV32-NEXT:    ret
510;
511; RV64-LABEL: bswap_nxv4i64:
512; RV64:       # %bb.0:
513; RV64-NEXT:    li a0, 56
514; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
515; RV64-NEXT:    vsrl.vx v12, v8, a0
516; RV64-NEXT:    li a1, 40
517; RV64-NEXT:    vsrl.vx v16, v8, a1
518; RV64-NEXT:    lui a2, 16
519; RV64-NEXT:    addiw a2, a2, -256
520; RV64-NEXT:    vand.vx v16, v16, a2
521; RV64-NEXT:    vor.vv v12, v16, v12
522; RV64-NEXT:    vsrl.vi v16, v8, 24
523; RV64-NEXT:    lui a2, 4080
524; RV64-NEXT:    vand.vx v16, v16, a2
525; RV64-NEXT:    vsrl.vi v20, v8, 8
526; RV64-NEXT:    li a2, 255
527; RV64-NEXT:    slli a3, a2, 24
528; RV64-NEXT:    vand.vx v20, v20, a3
529; RV64-NEXT:    vor.vv v16, v20, v16
530; RV64-NEXT:    vor.vv v12, v16, v12
531; RV64-NEXT:    vsll.vi v16, v8, 8
532; RV64-NEXT:    slli a3, a2, 32
533; RV64-NEXT:    vand.vx v16, v16, a3
534; RV64-NEXT:    vsll.vi v20, v8, 24
535; RV64-NEXT:    slli a3, a2, 40
536; RV64-NEXT:    vand.vx v20, v20, a3
537; RV64-NEXT:    vor.vv v16, v20, v16
538; RV64-NEXT:    vsll.vx v20, v8, a0
539; RV64-NEXT:    vsll.vx v8, v8, a1
540; RV64-NEXT:    slli a0, a2, 48
541; RV64-NEXT:    vand.vx v8, v8, a0
542; RV64-NEXT:    vor.vv v8, v20, v8
543; RV64-NEXT:    vor.vv v8, v8, v16
544; RV64-NEXT:    vor.vv v8, v8, v12
545; RV64-NEXT:    ret
546  %a = call <vscale x 4 x i64> @llvm.bswap.nxv4i64(<vscale x 4 x i64> %va)
547  ret <vscale x 4 x i64> %a
548}
549declare <vscale x 4 x i64> @llvm.bswap.nxv4i64(<vscale x 4 x i64>)
550
551define <vscale x 8 x i64> @bswap_nxv8i64(<vscale x 8 x i64> %va) {
552; RV32-LABEL: bswap_nxv8i64:
553; RV32:       # %bb.0:
554; RV32-NEXT:    addi sp, sp, -16
555; RV32-NEXT:    .cfi_def_cfa_offset 16
556; RV32-NEXT:    csrr a0, vlenb
557; RV32-NEXT:    slli a0, a0, 4
558; RV32-NEXT:    sub sp, sp, a0
559; RV32-NEXT:    sw zero, 12(sp)
560; RV32-NEXT:    lui a0, 1044480
561; RV32-NEXT:    sw a0, 8(sp)
562; RV32-NEXT:    lui a0, 4080
563; RV32-NEXT:    sw a0, 12(sp)
564; RV32-NEXT:    sw zero, 8(sp)
565; RV32-NEXT:    li a1, 255
566; RV32-NEXT:    sw a1, 12(sp)
567; RV32-NEXT:    lui a1, 16
568; RV32-NEXT:    addi a1, a1, -256
569; RV32-NEXT:    sw a1, 12(sp)
570; RV32-NEXT:    li a2, 56
571; RV32-NEXT:    vsetvli a3, zero, e64, m8, ta, mu
572; RV32-NEXT:    vsrl.vx v16, v8, a2
573; RV32-NEXT:    li a3, 40
574; RV32-NEXT:    vsrl.vx v24, v8, a3
575; RV32-NEXT:    addi a4, sp, 8
576; RV32-NEXT:    vlse64.v v0, (a4), zero
577; RV32-NEXT:    vand.vx v24, v24, a1
578; RV32-NEXT:    vor.vv v16, v24, v16
579; RV32-NEXT:    csrr a1, vlenb
580; RV32-NEXT:    slli a1, a1, 3
581; RV32-NEXT:    add a1, sp, a1
582; RV32-NEXT:    addi a1, a1, 16
583; RV32-NEXT:    vs8r.v v16, (a1) # Unknown-size Folded Spill
584; RV32-NEXT:    vsrl.vi v24, v8, 8
585; RV32-NEXT:    vand.vv v24, v24, v0
586; RV32-NEXT:    vsrl.vi v0, v8, 24
587; RV32-NEXT:    vand.vx v0, v0, a0
588; RV32-NEXT:    addi a0, sp, 8
589; RV32-NEXT:    vlse64.v v16, (a0), zero
590; RV32-NEXT:    vor.vv v24, v24, v0
591; RV32-NEXT:    csrr a0, vlenb
592; RV32-NEXT:    slli a0, a0, 3
593; RV32-NEXT:    add a0, sp, a0
594; RV32-NEXT:    addi a0, a0, 16
595; RV32-NEXT:    vl8re8.v v0, (a0) # Unknown-size Folded Reload
596; RV32-NEXT:    vor.vv v24, v24, v0
597; RV32-NEXT:    csrr a0, vlenb
598; RV32-NEXT:    slli a0, a0, 3
599; RV32-NEXT:    add a0, sp, a0
600; RV32-NEXT:    addi a0, a0, 16
601; RV32-NEXT:    vs8r.v v24, (a0) # Unknown-size Folded Spill
602; RV32-NEXT:    vsll.vx v0, v8, a3
603; RV32-NEXT:    vand.vv v16, v0, v16
604; RV32-NEXT:    vsll.vx v0, v8, a2
605; RV32-NEXT:    addi a0, sp, 8
606; RV32-NEXT:    vlse64.v v24, (a0), zero
607; RV32-NEXT:    vor.vv v16, v0, v16
608; RV32-NEXT:    addi a0, sp, 16
609; RV32-NEXT:    vs8r.v v16, (a0) # Unknown-size Folded Spill
610; RV32-NEXT:    addi a0, sp, 8
611; RV32-NEXT:    vlse64.v v0, (a0), zero
612; RV32-NEXT:    vsll.vi v16, v8, 8
613; RV32-NEXT:    vand.vv v16, v16, v24
614; RV32-NEXT:    vsll.vi v8, v8, 24
615; RV32-NEXT:    vand.vv v8, v8, v0
616; RV32-NEXT:    vor.vv v8, v8, v16
617; RV32-NEXT:    addi a0, sp, 16
618; RV32-NEXT:    vl8re8.v v16, (a0) # Unknown-size Folded Reload
619; RV32-NEXT:    vor.vv v8, v16, v8
620; RV32-NEXT:    csrr a0, vlenb
621; RV32-NEXT:    slli a0, a0, 3
622; RV32-NEXT:    add a0, sp, a0
623; RV32-NEXT:    addi a0, a0, 16
624; RV32-NEXT:    vl8re8.v v16, (a0) # Unknown-size Folded Reload
625; RV32-NEXT:    vor.vv v8, v8, v16
626; RV32-NEXT:    csrr a0, vlenb
627; RV32-NEXT:    slli a0, a0, 4
628; RV32-NEXT:    add sp, sp, a0
629; RV32-NEXT:    addi sp, sp, 16
630; RV32-NEXT:    ret
631;
632; RV64-LABEL: bswap_nxv8i64:
633; RV64:       # %bb.0:
634; RV64-NEXT:    li a0, 56
635; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
636; RV64-NEXT:    vsrl.vx v16, v8, a0
637; RV64-NEXT:    li a1, 40
638; RV64-NEXT:    vsrl.vx v24, v8, a1
639; RV64-NEXT:    lui a2, 16
640; RV64-NEXT:    addiw a2, a2, -256
641; RV64-NEXT:    vand.vx v24, v24, a2
642; RV64-NEXT:    vor.vv v16, v24, v16
643; RV64-NEXT:    vsrl.vi v24, v8, 24
644; RV64-NEXT:    lui a2, 4080
645; RV64-NEXT:    vand.vx v24, v24, a2
646; RV64-NEXT:    vsrl.vi v0, v8, 8
647; RV64-NEXT:    li a2, 255
648; RV64-NEXT:    slli a3, a2, 24
649; RV64-NEXT:    vand.vx v0, v0, a3
650; RV64-NEXT:    vor.vv v24, v0, v24
651; RV64-NEXT:    vor.vv v16, v24, v16
652; RV64-NEXT:    vsll.vi v24, v8, 8
653; RV64-NEXT:    slli a3, a2, 32
654; RV64-NEXT:    vand.vx v24, v24, a3
655; RV64-NEXT:    vsll.vi v0, v8, 24
656; RV64-NEXT:    slli a3, a2, 40
657; RV64-NEXT:    vand.vx v0, v0, a3
658; RV64-NEXT:    vor.vv v24, v0, v24
659; RV64-NEXT:    vsll.vx v0, v8, a0
660; RV64-NEXT:    vsll.vx v8, v8, a1
661; RV64-NEXT:    slli a0, a2, 48
662; RV64-NEXT:    vand.vx v8, v8, a0
663; RV64-NEXT:    vor.vv v8, v0, v8
664; RV64-NEXT:    vor.vv v8, v8, v24
665; RV64-NEXT:    vor.vv v8, v8, v16
666; RV64-NEXT:    ret
667  %a = call <vscale x 8 x i64> @llvm.bswap.nxv8i64(<vscale x 8 x i64> %va)
668  ret <vscale x 8 x i64> %a
669}
670declare <vscale x 8 x i64> @llvm.bswap.nxv8i64(<vscale x 8 x i64>)
671