1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV64I %s
4
5; The test cases check that the single float arguments won't be extended
6; when passing to softfloat functions.
7; RISCV backend using shouldExtendTypeInLibCall target hook to suppress
8; the extension generation.
9
10define float @fadd_s(float %a, float %b) nounwind {
11; RV64I-LABEL: fadd_s:
12; RV64I:       # %bb.0:
13; RV64I-NEXT:    addi sp, sp, -16
14; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
15; RV64I-NEXT:    call __addsf3@plt
16; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
17; RV64I-NEXT:    addi sp, sp, 16
18; RV64I-NEXT:    ret
19  %1 = fadd float %a, %b
20  ret float %1
21}
22
23define float @fsub_s(float %a, float %b) nounwind {
24; RV64I-LABEL: fsub_s:
25; RV64I:       # %bb.0:
26; RV64I-NEXT:    addi sp, sp, -16
27; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
28; RV64I-NEXT:    call __subsf3@plt
29; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
30; RV64I-NEXT:    addi sp, sp, 16
31; RV64I-NEXT:    ret
32  %1 = fsub float %a, %b
33  ret float %1
34}
35
36define float @fmul_s(float %a, float %b) nounwind {
37; RV64I-LABEL: fmul_s:
38; RV64I:       # %bb.0:
39; RV64I-NEXT:    addi sp, sp, -16
40; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
41; RV64I-NEXT:    call __mulsf3@plt
42; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
43; RV64I-NEXT:    addi sp, sp, 16
44; RV64I-NEXT:    ret
45  %1 = fmul float %a, %b
46  ret float %1
47}
48
49define float @fdiv_s(float %a, float %b) nounwind {
50; RV64I-LABEL: fdiv_s:
51; RV64I:       # %bb.0:
52; RV64I-NEXT:    addi sp, sp, -16
53; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
54; RV64I-NEXT:    call __divsf3@plt
55; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
56; RV64I-NEXT:    addi sp, sp, 16
57; RV64I-NEXT:    ret
58  %1 = fdiv float %a, %b
59  ret float %1
60}
61
62define i32 @feq_s(float %a, float %b) nounwind {
63; RV64I-LABEL: feq_s:
64; RV64I:       # %bb.0:
65; RV64I-NEXT:    addi sp, sp, -16
66; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
67; RV64I-NEXT:    call __eqsf2@plt
68; RV64I-NEXT:    seqz a0, a0
69; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
70; RV64I-NEXT:    addi sp, sp, 16
71; RV64I-NEXT:    ret
72  %1 = fcmp oeq float %a, %b
73  %2 = zext i1 %1 to i32
74  ret i32 %2
75}
76
77define i32 @flt_s(float %a, float %b) nounwind {
78; RV64I-LABEL: flt_s:
79; RV64I:       # %bb.0:
80; RV64I-NEXT:    addi sp, sp, -16
81; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
82; RV64I-NEXT:    call __ltsf2@plt
83; RV64I-NEXT:    slti a0, a0, 0
84; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
85; RV64I-NEXT:    addi sp, sp, 16
86; RV64I-NEXT:    ret
87  %1 = fcmp olt float %a, %b
88  %2 = zext i1 %1 to i32
89  ret i32 %2
90}
91
92define i32 @fle_s(float %a, float %b) nounwind {
93; RV64I-LABEL: fle_s:
94; RV64I:       # %bb.0:
95; RV64I-NEXT:    addi sp, sp, -16
96; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
97; RV64I-NEXT:    call __lesf2@plt
98; RV64I-NEXT:    slti a0, a0, 1
99; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
100; RV64I-NEXT:    addi sp, sp, 16
101; RV64I-NEXT:    ret
102  %1 = fcmp ole float %a, %b
103  %2 = zext i1 %1 to i32
104  ret i32 %2
105}
106
107define i32 @fcmp_ogt(float %a, float %b) nounwind {
108; RV64I-LABEL: fcmp_ogt:
109; RV64I:       # %bb.0:
110; RV64I-NEXT:    addi sp, sp, -16
111; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
112; RV64I-NEXT:    call __gtsf2@plt
113; RV64I-NEXT:    sgtz a0, a0
114; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
115; RV64I-NEXT:    addi sp, sp, 16
116; RV64I-NEXT:    ret
117  %1 = fcmp ogt float %a, %b
118  %2 = zext i1 %1 to i32
119  ret i32 %2
120}
121
122define i32 @fcmp_oge(float %a, float %b) nounwind {
123; RV64I-LABEL: fcmp_oge:
124; RV64I:       # %bb.0:
125; RV64I-NEXT:    addi sp, sp, -16
126; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
127; RV64I-NEXT:    call __gesf2@plt
128; RV64I-NEXT:    addi a1, zero, -1
129; RV64I-NEXT:    slt a0, a1, a0
130; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
131; RV64I-NEXT:    addi sp, sp, 16
132; RV64I-NEXT:    ret
133  %1 = fcmp oge float %a, %b
134  %2 = zext i1 %1 to i32
135  ret i32 %2
136}
137
138define i32 @fcmp_ord(float %a, float %b) nounwind {
139; RV64I-LABEL: fcmp_ord:
140; RV64I:       # %bb.0:
141; RV64I-NEXT:    addi sp, sp, -16
142; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
143; RV64I-NEXT:    call __unordsf2@plt
144; RV64I-NEXT:    seqz a0, a0
145; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
146; RV64I-NEXT:    addi sp, sp, 16
147; RV64I-NEXT:    ret
148  %1 = fcmp ord float %a, %b
149  %2 = zext i1 %1 to i32
150  ret i32 %2
151}
152
153define i32 @fcmp_une(float %a, float %b) nounwind {
154; RV64I-LABEL: fcmp_une:
155; RV64I:       # %bb.0:
156; RV64I-NEXT:    addi sp, sp, -16
157; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
158; RV64I-NEXT:    call __nesf2@plt
159; RV64I-NEXT:    snez a0, a0
160; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
161; RV64I-NEXT:    addi sp, sp, 16
162; RV64I-NEXT:    ret
163  %1 = fcmp une float %a, %b
164  %2 = zext i1 %1 to i32
165  ret i32 %2
166}
167
168define i32 @fcvt_w_s(float %a) nounwind {
169; RV64I-LABEL: fcvt_w_s:
170; RV64I:       # %bb.0:
171; RV64I-NEXT:    addi sp, sp, -16
172; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
173; RV64I-NEXT:    call __fixsfsi@plt
174; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
175; RV64I-NEXT:    addi sp, sp, 16
176; RV64I-NEXT:    ret
177  %1 = fptosi float %a to i32
178  ret i32 %1
179}
180
181define i32 @fcvt_wu_s(float %a) nounwind {
182; RV64I-LABEL: fcvt_wu_s:
183; RV64I:       # %bb.0:
184; RV64I-NEXT:    addi sp, sp, -16
185; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
186; RV64I-NEXT:    call __fixunssfsi@plt
187; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
188; RV64I-NEXT:    addi sp, sp, 16
189; RV64I-NEXT:    ret
190  %1 = fptoui float %a to i32
191  ret i32 %1
192}
193
194define float @fcvt_s_w(i32 %a) nounwind {
195; RV64I-LABEL: fcvt_s_w:
196; RV64I:       # %bb.0:
197; RV64I-NEXT:    addi sp, sp, -16
198; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
199; RV64I-NEXT:    sext.w a0, a0
200; RV64I-NEXT:    call __floatsisf@plt
201; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
202; RV64I-NEXT:    addi sp, sp, 16
203; RV64I-NEXT:    ret
204  %1 = sitofp i32 %a to float
205  ret float %1
206}
207
208define float @fcvt_s_wu(i32 %a) nounwind {
209; RV64I-LABEL: fcvt_s_wu:
210; RV64I:       # %bb.0:
211; RV64I-NEXT:    addi sp, sp, -16
212; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
213; RV64I-NEXT:    sext.w a0, a0
214; RV64I-NEXT:    call __floatunsisf@plt
215; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
216; RV64I-NEXT:    addi sp, sp, 16
217; RV64I-NEXT:    ret
218  %1 = uitofp i32 %a to float
219  ret float %1
220}
221
222define i64 @fcvt_l_s(float %a) nounwind {
223; RV64I-LABEL: fcvt_l_s:
224; RV64I:       # %bb.0:
225; RV64I-NEXT:    addi sp, sp, -16
226; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
227; RV64I-NEXT:    call __fixsfdi@plt
228; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
229; RV64I-NEXT:    addi sp, sp, 16
230; RV64I-NEXT:    ret
231  %1 = fptosi float %a to i64
232  ret i64 %1
233}
234
235define i64 @fcvt_lu_s(float %a) nounwind {
236; RV64I-LABEL: fcvt_lu_s:
237; RV64I:       # %bb.0:
238; RV64I-NEXT:    addi sp, sp, -16
239; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
240; RV64I-NEXT:    call __fixunssfdi@plt
241; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
242; RV64I-NEXT:    addi sp, sp, 16
243; RV64I-NEXT:    ret
244  %1 = fptoui float %a to i64
245  ret i64 %1
246}
247
248define float @fcvt_s_l(i64 %a) nounwind {
249; RV64I-LABEL: fcvt_s_l:
250; RV64I:       # %bb.0:
251; RV64I-NEXT:    addi sp, sp, -16
252; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
253; RV64I-NEXT:    call __floatdisf@plt
254; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
255; RV64I-NEXT:    addi sp, sp, 16
256; RV64I-NEXT:    ret
257  %1 = sitofp i64 %a to float
258  ret float %1
259}
260
261define float @fcvt_s_lu(i64 %a) nounwind {
262; RV64I-LABEL: fcvt_s_lu:
263; RV64I:       # %bb.0:
264; RV64I-NEXT:    addi sp, sp, -16
265; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
266; RV64I-NEXT:    call __floatundisf@plt
267; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
268; RV64I-NEXT:    addi sp, sp, 16
269; RV64I-NEXT:    ret
270  %1 = uitofp i64 %a to float
271  ret float %1
272}
273
274declare float @llvm.sqrt.f32(float)
275
276define float @fsqrt_s(float %a) nounwind {
277; RV64I-LABEL: fsqrt_s:
278; RV64I:       # %bb.0:
279; RV64I-NEXT:    addi sp, sp, -16
280; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
281; RV64I-NEXT:    call sqrtf@plt
282; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
283; RV64I-NEXT:    addi sp, sp, 16
284; RV64I-NEXT:    ret
285  %1 = call float @llvm.sqrt.f32(float %a)
286  ret float %1
287}
288
289declare float @llvm.copysign.f32(float, float)
290
291define float @fsgnj_s(float %a, float %b) nounwind {
292; RV64I-LABEL: fsgnj_s:
293; RV64I:       # %bb.0:
294; RV64I-NEXT:    lui a2, 524288
295; RV64I-NEXT:    and a1, a1, a2
296; RV64I-NEXT:    addiw a2, a2, -1
297; RV64I-NEXT:    and a0, a0, a2
298; RV64I-NEXT:    or a0, a0, a1
299; RV64I-NEXT:    ret
300  %1 = call float @llvm.copysign.f32(float %a, float %b)
301  ret float %1
302}
303
304declare float @llvm.minnum.f32(float, float)
305
306define float @fmin_s(float %a, float %b) nounwind {
307; RV64I-LABEL: fmin_s:
308; RV64I:       # %bb.0:
309; RV64I-NEXT:    addi sp, sp, -16
310; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
311; RV64I-NEXT:    call fminf@plt
312; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
313; RV64I-NEXT:    addi sp, sp, 16
314; RV64I-NEXT:    ret
315  %1 = call float @llvm.minnum.f32(float %a, float %b)
316  ret float %1
317}
318
319declare float @llvm.maxnum.f32(float, float)
320
321define float @fmax_s(float %a, float %b) nounwind {
322; RV64I-LABEL: fmax_s:
323; RV64I:       # %bb.0:
324; RV64I-NEXT:    addi sp, sp, -16
325; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
326; RV64I-NEXT:    call fmaxf@plt
327; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
328; RV64I-NEXT:    addi sp, sp, 16
329; RV64I-NEXT:    ret
330  %1 = call float @llvm.maxnum.f32(float %a, float %b)
331  ret float %1
332}
333
334
335declare float @llvm.fma.f32(float, float, float)
336
337define float @fmadd_s(float %a, float %b, float %c) nounwind {
338; RV64I-LABEL: fmadd_s:
339; RV64I:       # %bb.0:
340; RV64I-NEXT:    addi sp, sp, -16
341; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
342; RV64I-NEXT:    call fmaf@plt
343; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
344; RV64I-NEXT:    addi sp, sp, 16
345; RV64I-NEXT:    ret
346  %1 = call float @llvm.fma.f32(float %a, float %b, float %c)
347  ret float %1
348}
349
350define float @fmsub_s(float %a, float %b, float %c) nounwind {
351; RV64I-LABEL: fmsub_s:
352; RV64I:       # %bb.0:
353; RV64I-NEXT:    addi sp, sp, -32
354; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
355; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
356; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
357; RV64I-NEXT:    mv s0, a1
358; RV64I-NEXT:    mv s1, a0
359; RV64I-NEXT:    mv a0, a2
360; RV64I-NEXT:    mv a1, zero
361; RV64I-NEXT:    call __addsf3@plt
362; RV64I-NEXT:    lui a1, 524288
363; RV64I-NEXT:    xor a2, a0, a1
364; RV64I-NEXT:    mv a0, s1
365; RV64I-NEXT:    mv a1, s0
366; RV64I-NEXT:    call fmaf@plt
367; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
368; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
369; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
370; RV64I-NEXT:    addi sp, sp, 32
371; RV64I-NEXT:    ret
372  %c_ = fadd float 0.0, %c ; avoid negation using xor
373  %negc = fsub float -0.0, %c_
374  %1 = call float @llvm.fma.f32(float %a, float %b, float %negc)
375  ret float %1
376}
377
378define float @fnmadd_s(float %a, float %b, float %c) nounwind {
379; RV64I-LABEL: fnmadd_s:
380; RV64I:       # %bb.0:
381; RV64I-NEXT:    addi sp, sp, -32
382; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
383; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
384; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
385; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
386; RV64I-NEXT:    mv s0, a2
387; RV64I-NEXT:    mv s2, a1
388; RV64I-NEXT:    mv a1, zero
389; RV64I-NEXT:    call __addsf3@plt
390; RV64I-NEXT:    mv s1, a0
391; RV64I-NEXT:    mv a0, s0
392; RV64I-NEXT:    mv a1, zero
393; RV64I-NEXT:    call __addsf3@plt
394; RV64I-NEXT:    lui a2, 524288
395; RV64I-NEXT:    xor a1, s1, a2
396; RV64I-NEXT:    xor a2, a0, a2
397; RV64I-NEXT:    mv a0, a1
398; RV64I-NEXT:    mv a1, s2
399; RV64I-NEXT:    call fmaf@plt
400; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
401; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
402; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
403; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
404; RV64I-NEXT:    addi sp, sp, 32
405; RV64I-NEXT:    ret
406  %a_ = fadd float 0.0, %a
407  %c_ = fadd float 0.0, %c
408  %nega = fsub float -0.0, %a_
409  %negc = fsub float -0.0, %c_
410  %1 = call float @llvm.fma.f32(float %nega, float %b, float %negc)
411  ret float %1
412}
413
414define float @fnmsub_s(float %a, float %b, float %c) nounwind {
415; RV64I-LABEL: fnmsub_s:
416; RV64I:       # %bb.0:
417; RV64I-NEXT:    addi sp, sp, -32
418; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
419; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
420; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
421; RV64I-NEXT:    mv s0, a2
422; RV64I-NEXT:    mv s1, a1
423; RV64I-NEXT:    mv a1, zero
424; RV64I-NEXT:    call __addsf3@plt
425; RV64I-NEXT:    lui a1, 524288
426; RV64I-NEXT:    xor a0, a0, a1
427; RV64I-NEXT:    mv a1, s1
428; RV64I-NEXT:    mv a2, s0
429; RV64I-NEXT:    call fmaf@plt
430; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
431; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
432; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
433; RV64I-NEXT:    addi sp, sp, 32
434; RV64I-NEXT:    ret
435  %a_ = fadd float 0.0, %a
436  %nega = fsub float -0.0, %a_
437  %1 = call float @llvm.fma.f32(float %nega, float %b, float %c)
438  ret float %1
439}
440
441declare float @llvm.ceil.f32(float)
442
443define float @fceil_s(float %a) nounwind {
444; RV64I-LABEL: fceil_s:
445; RV64I:       # %bb.0:
446; RV64I-NEXT:    addi sp, sp, -16
447; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
448; RV64I-NEXT:    call ceilf@plt
449; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
450; RV64I-NEXT:    addi sp, sp, 16
451; RV64I-NEXT:    ret
452  %1 = call float @llvm.ceil.f32(float %a)
453  ret float %1
454}
455
456declare float @llvm.cos.f32(float)
457
458define float @fcos_s(float %a) nounwind {
459; RV64I-LABEL: fcos_s:
460; RV64I:       # %bb.0:
461; RV64I-NEXT:    addi sp, sp, -16
462; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
463; RV64I-NEXT:    call cosf@plt
464; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
465; RV64I-NEXT:    addi sp, sp, 16
466; RV64I-NEXT:    ret
467  %1 = call float @llvm.cos.f32(float %a)
468  ret float %1
469}
470
471declare float @llvm.sin.f32(float)
472
473define float @fsin_s(float %a) nounwind {
474; RV64I-LABEL: fsin_s:
475; RV64I:       # %bb.0:
476; RV64I-NEXT:    addi sp, sp, -16
477; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
478; RV64I-NEXT:    call sinf@plt
479; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
480; RV64I-NEXT:    addi sp, sp, 16
481; RV64I-NEXT:    ret
482  %1 = call float @llvm.sin.f32(float %a)
483  ret float %1
484}
485
486declare float @llvm.exp.f32(float)
487
488define float @fexp_s(float %a) nounwind {
489; RV64I-LABEL: fexp_s:
490; RV64I:       # %bb.0:
491; RV64I-NEXT:    addi sp, sp, -16
492; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
493; RV64I-NEXT:    call expf@plt
494; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
495; RV64I-NEXT:    addi sp, sp, 16
496; RV64I-NEXT:    ret
497  %1 = call float @llvm.exp.f32(float %a)
498  ret float %1
499}
500
501declare float @llvm.exp2.f32(float)
502
503define float @fexp2_s(float %a) nounwind {
504; RV64I-LABEL: fexp2_s:
505; RV64I:       # %bb.0:
506; RV64I-NEXT:    addi sp, sp, -16
507; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
508; RV64I-NEXT:    call exp2f@plt
509; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
510; RV64I-NEXT:    addi sp, sp, 16
511; RV64I-NEXT:    ret
512  %1 = call float @llvm.exp2.f32(float %a)
513  ret float %1
514}
515
516declare float @llvm.floor.f32(float)
517
518define float @ffloor_s(float %a) nounwind {
519; RV64I-LABEL: ffloor_s:
520; RV64I:       # %bb.0:
521; RV64I-NEXT:    addi sp, sp, -16
522; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
523; RV64I-NEXT:    call floorf@plt
524; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
525; RV64I-NEXT:    addi sp, sp, 16
526; RV64I-NEXT:    ret
527  %1 = call float @llvm.floor.f32(float %a)
528  ret float %1
529}
530
531declare float @llvm.flog.f32(float)
532
533define float @fflog_s(float %a) nounwind {
534; RV64I-LABEL: fflog_s:
535; RV64I:       # %bb.0:
536; RV64I-NEXT:    addi sp, sp, -16
537; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
538; RV64I-NEXT:    call llvm.flog.f32@plt
539; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
540; RV64I-NEXT:    addi sp, sp, 16
541; RV64I-NEXT:    ret
542  %1 = call float @llvm.flog.f32(float %a)
543  ret float %1
544}
545
546declare float @llvm.flog2.f32(float)
547
548define float @fflog2_s(float %a) nounwind {
549; RV64I-LABEL: fflog2_s:
550; RV64I:       # %bb.0:
551; RV64I-NEXT:    addi sp, sp, -16
552; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
553; RV64I-NEXT:    call llvm.flog2.f32@plt
554; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
555; RV64I-NEXT:    addi sp, sp, 16
556; RV64I-NEXT:    ret
557  %1 = call float @llvm.flog2.f32(float %a)
558  ret float %1
559}
560
561declare float @llvm.flog10.f32(float)
562
563define float @fflog10_s(float %a) nounwind {
564; RV64I-LABEL: fflog10_s:
565; RV64I:       # %bb.0:
566; RV64I-NEXT:    addi sp, sp, -16
567; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
568; RV64I-NEXT:    call llvm.flog10.f32@plt
569; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
570; RV64I-NEXT:    addi sp, sp, 16
571; RV64I-NEXT:    ret
572  %1 = call float @llvm.flog10.f32(float %a)
573  ret float %1
574}
575
576declare float @llvm.fnearbyint.f32(float)
577
578define float @fnearbyint_s(float %a) nounwind {
579; RV64I-LABEL: fnearbyint_s:
580; RV64I:       # %bb.0:
581; RV64I-NEXT:    addi sp, sp, -16
582; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
583; RV64I-NEXT:    call llvm.fnearbyint.f32@plt
584; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
585; RV64I-NEXT:    addi sp, sp, 16
586; RV64I-NEXT:    ret
587  %1 = call float @llvm.fnearbyint.f32(float %a)
588  ret float %1
589}
590
591declare float @llvm.round.f32(float)
592
593define float @fround_s(float %a) nounwind {
594; RV64I-LABEL: fround_s:
595; RV64I:       # %bb.0:
596; RV64I-NEXT:    addi sp, sp, -16
597; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
598; RV64I-NEXT:    call roundf@plt
599; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
600; RV64I-NEXT:    addi sp, sp, 16
601; RV64I-NEXT:    ret
602  %1 = call float @llvm.round.f32(float %a)
603  ret float %1
604}
605
606declare float @llvm.fpround.f32(float)
607
608define float @fpround_s(float %a) nounwind {
609; RV64I-LABEL: fpround_s:
610; RV64I:       # %bb.0:
611; RV64I-NEXT:    addi sp, sp, -16
612; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
613; RV64I-NEXT:    call llvm.fpround.f32@plt
614; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
615; RV64I-NEXT:    addi sp, sp, 16
616; RV64I-NEXT:    ret
617  %1 = call float @llvm.fpround.f32(float %a)
618  ret float %1
619}
620
621declare float @llvm.rint.f32(float)
622
623define float @frint_s(float %a) nounwind {
624; RV64I-LABEL: frint_s:
625; RV64I:       # %bb.0:
626; RV64I-NEXT:    addi sp, sp, -16
627; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
628; RV64I-NEXT:    call rintf@plt
629; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
630; RV64I-NEXT:    addi sp, sp, 16
631; RV64I-NEXT:    ret
632  %1 = call float @llvm.rint.f32(float %a)
633  ret float %1
634}
635
636declare float @llvm.rem.f32(float)
637
638define float @frem_s(float %a) nounwind {
639; RV64I-LABEL: frem_s:
640; RV64I:       # %bb.0:
641; RV64I-NEXT:    addi sp, sp, -16
642; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
643; RV64I-NEXT:    call llvm.rem.f32@plt
644; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
645; RV64I-NEXT:    addi sp, sp, 16
646; RV64I-NEXT:    ret
647  %1 = call float @llvm.rem.f32(float %a)
648  ret float %1
649}
650
651declare float @llvm.pow.f32(float %Val, float %power)
652
653define float @fpow_s(float %a, float %b) nounwind {
654; RV64I-LABEL: fpow_s:
655; RV64I:       # %bb.0:
656; RV64I-NEXT:    addi sp, sp, -16
657; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
658; RV64I-NEXT:    call powf@plt
659; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
660; RV64I-NEXT:    addi sp, sp, 16
661; RV64I-NEXT:    ret
662  %1 = call float @llvm.pow.f32(float %a, float %b)
663  ret float %1
664}
665
666declare float @llvm.powi.f32.i32(float %Val, i32 %power)
667
668define float @fpowi_s(float %a, i32 %b) nounwind {
669; RV64I-LABEL: fpowi_s:
670; RV64I:       # %bb.0:
671; RV64I-NEXT:    addi sp, sp, -16
672; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
673; RV64I-NEXT:    sext.w a1, a1
674; RV64I-NEXT:    call __powisf2@plt
675; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
676; RV64I-NEXT:    addi sp, sp, 16
677; RV64I-NEXT:    ret
678  %1 = call float @llvm.powi.f32.i32(float %a, i32 %b)
679  ret float %1
680}
681
682define double @fp_ext(float %a) nounwind {
683; RV64I-LABEL: fp_ext:
684; RV64I:       # %bb.0:
685; RV64I-NEXT:    addi sp, sp, -16
686; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
687; RV64I-NEXT:    call __extendsfdf2@plt
688; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
689; RV64I-NEXT:    addi sp, sp, 16
690; RV64I-NEXT:    ret
691  %conv = fpext float %a to double
692  ret double %conv
693}
694
695define float @fp_trunc(double %a) nounwind {
696; RV64I-LABEL: fp_trunc:
697; RV64I:       # %bb.0:
698; RV64I-NEXT:    addi sp, sp, -16
699; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
700; RV64I-NEXT:    call __truncdfsf2@plt
701; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
702; RV64I-NEXT:    addi sp, sp, 16
703; RV64I-NEXT:    ret
704  %conv = fptrunc double %a to float
705  ret float %conv
706}
707
708define i32 @fp32_to_ui32(float %a) nounwind {
709; RV64I-LABEL: fp32_to_ui32:
710; RV64I:       # %bb.0: # %entry
711; RV64I-NEXT:    addi sp, sp, -16
712; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
713; RV64I-NEXT:    call __fixunssfsi@plt
714; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
715; RV64I-NEXT:    addi sp, sp, 16
716; RV64I-NEXT:    ret
717entry:
718  %conv = fptoui float %a to i32
719  ret i32 %conv
720}
721
722define i32 @fp32_to_si32(float %a) nounwind  {
723; RV64I-LABEL: fp32_to_si32:
724; RV64I:       # %bb.0: # %entry
725; RV64I-NEXT:    addi sp, sp, -16
726; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
727; RV64I-NEXT:    call __fixsfsi@plt
728; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
729; RV64I-NEXT:    addi sp, sp, 16
730; RV64I-NEXT:    ret
731entry:
732  %conv = fptosi float %a to i32
733  ret i32 %conv
734}
735
736
737
738declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata)
739declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata)
740
741define i32 @strict_fp32_to_ui32(float %a) nounwind strictfp {
742; RV64I-LABEL: strict_fp32_to_ui32:
743; RV64I:       # %bb.0: # %entry
744; RV64I-NEXT:    addi sp, sp, -16
745; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
746; RV64I-NEXT:    call __fixunssfsi@plt
747; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
748; RV64I-NEXT:    addi sp, sp, 16
749; RV64I-NEXT:    ret
750entry:
751  %conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict")
752  ret i32 %conv
753}
754
755define i32 @strict_fp32_to_si32(float %a) nounwind strictfp {
756; RV64I-LABEL: strict_fp32_to_si32:
757; RV64I:       # %bb.0: # %entry
758; RV64I-NEXT:    addi sp, sp, -16
759; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
760; RV64I-NEXT:    call __fixsfsi@plt
761; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
762; RV64I-NEXT:    addi sp, sp, 16
763; RV64I-NEXT:    ret
764entry:
765  %conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict")
766  ret i32 %conv
767}
768