1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV64I %s
4
5; The test cases check that the single float arguments won't be extended
6; when passing to softfloat functions.
7; RISCV backend using shouldExtendTypeInLibCall target hook to suppress
8; the extension generation.
9
10define float @fadd_s(float %a, float %b) nounwind {
11; RV64I-LABEL: fadd_s:
12; RV64I:       # %bb.0:
13; RV64I-NEXT:    addi sp, sp, -16
14; RV64I-NEXT:    sd ra, 8(sp)
15; RV64I-NEXT:    call __addsf3
16; RV64I-NEXT:    ld ra, 8(sp)
17; RV64I-NEXT:    addi sp, sp, 16
18; RV64I-NEXT:    ret
19  %1 = fadd float %a, %b
20  ret float %1
21}
22
23define float @fsub_s(float %a, float %b) nounwind {
24; RV64I-LABEL: fsub_s:
25; RV64I:       # %bb.0:
26; RV64I-NEXT:    addi sp, sp, -16
27; RV64I-NEXT:    sd ra, 8(sp)
28; RV64I-NEXT:    call __subsf3
29; RV64I-NEXT:    ld ra, 8(sp)
30; RV64I-NEXT:    addi sp, sp, 16
31; RV64I-NEXT:    ret
32  %1 = fsub float %a, %b
33  ret float %1
34}
35
36define float @fmul_s(float %a, float %b) nounwind {
37; RV64I-LABEL: fmul_s:
38; RV64I:       # %bb.0:
39; RV64I-NEXT:    addi sp, sp, -16
40; RV64I-NEXT:    sd ra, 8(sp)
41; RV64I-NEXT:    call __mulsf3
42; RV64I-NEXT:    ld ra, 8(sp)
43; RV64I-NEXT:    addi sp, sp, 16
44; RV64I-NEXT:    ret
45  %1 = fmul float %a, %b
46  ret float %1
47}
48
49define float @fdiv_s(float %a, float %b) nounwind {
50; RV64I-LABEL: fdiv_s:
51; RV64I:       # %bb.0:
52; RV64I-NEXT:    addi sp, sp, -16
53; RV64I-NEXT:    sd ra, 8(sp)
54; RV64I-NEXT:    call __divsf3
55; RV64I-NEXT:    ld ra, 8(sp)
56; RV64I-NEXT:    addi sp, sp, 16
57; RV64I-NEXT:    ret
58  %1 = fdiv float %a, %b
59  ret float %1
60}
61
62define i32 @feq_s(float %a, float %b) nounwind {
63; RV64I-LABEL: feq_s:
64; RV64I:       # %bb.0:
65; RV64I-NEXT:    addi sp, sp, -16
66; RV64I-NEXT:    sd ra, 8(sp)
67; RV64I-NEXT:    call __eqsf2
68; RV64I-NEXT:    seqz a0, a0
69; RV64I-NEXT:    ld ra, 8(sp)
70; RV64I-NEXT:    addi sp, sp, 16
71; RV64I-NEXT:    ret
72  %1 = fcmp oeq float %a, %b
73  %2 = zext i1 %1 to i32
74  ret i32 %2
75}
76
77define i32 @flt_s(float %a, float %b) nounwind {
78; RV64I-LABEL: flt_s:
79; RV64I:       # %bb.0:
80; RV64I-NEXT:    addi sp, sp, -16
81; RV64I-NEXT:    sd ra, 8(sp)
82; RV64I-NEXT:    call __ltsf2
83; RV64I-NEXT:    sext.w a0, a0
84; RV64I-NEXT:    slti a0, a0, 0
85; RV64I-NEXT:    ld ra, 8(sp)
86; RV64I-NEXT:    addi sp, sp, 16
87; RV64I-NEXT:    ret
88  %1 = fcmp olt float %a, %b
89  %2 = zext i1 %1 to i32
90  ret i32 %2
91}
92
93define i32 @fle_s(float %a, float %b) nounwind {
94; RV64I-LABEL: fle_s:
95; RV64I:       # %bb.0:
96; RV64I-NEXT:    addi sp, sp, -16
97; RV64I-NEXT:    sd ra, 8(sp)
98; RV64I-NEXT:    call __lesf2
99; RV64I-NEXT:    sext.w a0, a0
100; RV64I-NEXT:    slti a0, a0, 1
101; RV64I-NEXT:    ld ra, 8(sp)
102; RV64I-NEXT:    addi sp, sp, 16
103; RV64I-NEXT:    ret
104  %1 = fcmp ole float %a, %b
105  %2 = zext i1 %1 to i32
106  ret i32 %2
107}
108
109define i32 @fcmp_ogt(float %a, float %b) nounwind {
110; RV64I-LABEL: fcmp_ogt:
111; RV64I:       # %bb.0:
112; RV64I-NEXT:    addi sp, sp, -16
113; RV64I-NEXT:    sd ra, 8(sp)
114; RV64I-NEXT:    call __gtsf2
115; RV64I-NEXT:    sext.w a0, a0
116; RV64I-NEXT:    sgtz a0, a0
117; RV64I-NEXT:    ld ra, 8(sp)
118; RV64I-NEXT:    addi sp, sp, 16
119; RV64I-NEXT:    ret
120  %1 = fcmp ogt float %a, %b
121  %2 = zext i1 %1 to i32
122  ret i32 %2
123}
124
125define i32 @fcmp_oge(float %a, float %b) nounwind {
126; RV64I-LABEL: fcmp_oge:
127; RV64I:       # %bb.0:
128; RV64I-NEXT:    addi sp, sp, -16
129; RV64I-NEXT:    sd ra, 8(sp)
130; RV64I-NEXT:    call __gesf2
131; RV64I-NEXT:    sext.w a0, a0
132; RV64I-NEXT:    addi a1, zero, -1
133; RV64I-NEXT:    slt a0, a1, a0
134; RV64I-NEXT:    ld ra, 8(sp)
135; RV64I-NEXT:    addi sp, sp, 16
136; RV64I-NEXT:    ret
137  %1 = fcmp oge float %a, %b
138  %2 = zext i1 %1 to i32
139  ret i32 %2
140}
141
142define i32 @fcmp_ord(float %a, float %b) nounwind {
143; RV64I-LABEL: fcmp_ord:
144; RV64I:       # %bb.0:
145; RV64I-NEXT:    addi sp, sp, -16
146; RV64I-NEXT:    sd ra, 8(sp)
147; RV64I-NEXT:    call __unordsf2
148; RV64I-NEXT:    seqz a0, a0
149; RV64I-NEXT:    ld ra, 8(sp)
150; RV64I-NEXT:    addi sp, sp, 16
151; RV64I-NEXT:    ret
152  %1 = fcmp ord float %a, %b
153  %2 = zext i1 %1 to i32
154  ret i32 %2
155}
156
157define i32 @fcmp_une(float %a, float %b) nounwind {
158; RV64I-LABEL: fcmp_une:
159; RV64I:       # %bb.0:
160; RV64I-NEXT:    addi sp, sp, -16
161; RV64I-NEXT:    sd ra, 8(sp)
162; RV64I-NEXT:    call __nesf2
163; RV64I-NEXT:    snez a0, a0
164; RV64I-NEXT:    ld ra, 8(sp)
165; RV64I-NEXT:    addi sp, sp, 16
166; RV64I-NEXT:    ret
167  %1 = fcmp une float %a, %b
168  %2 = zext i1 %1 to i32
169  ret i32 %2
170}
171
172define i32 @fcvt_w_s(float %a) nounwind {
173; RV64I-LABEL: fcvt_w_s:
174; RV64I:       # %bb.0:
175; RV64I-NEXT:    addi sp, sp, -16
176; RV64I-NEXT:    sd ra, 8(sp)
177; RV64I-NEXT:    call __fixsfsi
178; RV64I-NEXT:    ld ra, 8(sp)
179; RV64I-NEXT:    addi sp, sp, 16
180; RV64I-NEXT:    ret
181  %1 = fptosi float %a to i32
182  ret i32 %1
183}
184
185define i32 @fcvt_wu_s(float %a) nounwind {
186; RV64I-LABEL: fcvt_wu_s:
187; RV64I:       # %bb.0:
188; RV64I-NEXT:    addi sp, sp, -16
189; RV64I-NEXT:    sd ra, 8(sp)
190; RV64I-NEXT:    call __fixunssfsi
191; RV64I-NEXT:    ld ra, 8(sp)
192; RV64I-NEXT:    addi sp, sp, 16
193; RV64I-NEXT:    ret
194  %1 = fptoui float %a to i32
195  ret i32 %1
196}
197
198define float @fcvt_s_w(i32 %a) nounwind {
199; RV64I-LABEL: fcvt_s_w:
200; RV64I:       # %bb.0:
201; RV64I-NEXT:    addi sp, sp, -16
202; RV64I-NEXT:    sd ra, 8(sp)
203; RV64I-NEXT:    sext.w a0, a0
204; RV64I-NEXT:    call __floatsisf
205; RV64I-NEXT:    ld ra, 8(sp)
206; RV64I-NEXT:    addi sp, sp, 16
207; RV64I-NEXT:    ret
208  %1 = sitofp i32 %a to float
209  ret float %1
210}
211
212define float @fcvt_s_wu(i32 %a) nounwind {
213; RV64I-LABEL: fcvt_s_wu:
214; RV64I:       # %bb.0:
215; RV64I-NEXT:    addi sp, sp, -16
216; RV64I-NEXT:    sd ra, 8(sp)
217; RV64I-NEXT:    slli a0, a0, 32
218; RV64I-NEXT:    srli a0, a0, 32
219; RV64I-NEXT:    call __floatunsisf
220; RV64I-NEXT:    ld ra, 8(sp)
221; RV64I-NEXT:    addi sp, sp, 16
222; RV64I-NEXT:    ret
223  %1 = uitofp i32 %a to float
224  ret float %1
225}
226
227define i64 @fcvt_l_s(float %a) nounwind {
228; RV64I-LABEL: fcvt_l_s:
229; RV64I:       # %bb.0:
230; RV64I-NEXT:    addi sp, sp, -16
231; RV64I-NEXT:    sd ra, 8(sp)
232; RV64I-NEXT:    call __fixsfdi
233; RV64I-NEXT:    ld ra, 8(sp)
234; RV64I-NEXT:    addi sp, sp, 16
235; RV64I-NEXT:    ret
236  %1 = fptosi float %a to i64
237  ret i64 %1
238}
239
240define i64 @fcvt_lu_s(float %a) nounwind {
241; RV64I-LABEL: fcvt_lu_s:
242; RV64I:       # %bb.0:
243; RV64I-NEXT:    addi sp, sp, -16
244; RV64I-NEXT:    sd ra, 8(sp)
245; RV64I-NEXT:    call __fixunssfdi
246; RV64I-NEXT:    ld ra, 8(sp)
247; RV64I-NEXT:    addi sp, sp, 16
248; RV64I-NEXT:    ret
249  %1 = fptoui float %a to i64
250  ret i64 %1
251}
252
253define float @fcvt_s_l(i64 %a) nounwind {
254; RV64I-LABEL: fcvt_s_l:
255; RV64I:       # %bb.0:
256; RV64I-NEXT:    addi sp, sp, -16
257; RV64I-NEXT:    sd ra, 8(sp)
258; RV64I-NEXT:    call __floatdisf
259; RV64I-NEXT:    ld ra, 8(sp)
260; RV64I-NEXT:    addi sp, sp, 16
261; RV64I-NEXT:    ret
262  %1 = sitofp i64 %a to float
263  ret float %1
264}
265
266define float @fcvt_s_lu(i64 %a) nounwind {
267; RV64I-LABEL: fcvt_s_lu:
268; RV64I:       # %bb.0:
269; RV64I-NEXT:    addi sp, sp, -16
270; RV64I-NEXT:    sd ra, 8(sp)
271; RV64I-NEXT:    call __floatundisf
272; RV64I-NEXT:    ld ra, 8(sp)
273; RV64I-NEXT:    addi sp, sp, 16
274; RV64I-NEXT:    ret
275  %1 = uitofp i64 %a to float
276  ret float %1
277}
278
279declare float @llvm.sqrt.f32(float)
280
281define float @fsqrt_s(float %a) nounwind {
282; RV64I-LABEL: fsqrt_s:
283; RV64I:       # %bb.0:
284; RV64I-NEXT:    addi sp, sp, -16
285; RV64I-NEXT:    sd ra, 8(sp)
286; RV64I-NEXT:    call sqrtf
287; RV64I-NEXT:    ld ra, 8(sp)
288; RV64I-NEXT:    addi sp, sp, 16
289; RV64I-NEXT:    ret
290  %1 = call float @llvm.sqrt.f32(float %a)
291  ret float %1
292}
293
294declare float @llvm.copysign.f32(float, float)
295
296define float @fsgnj_s(float %a, float %b) nounwind {
297; RV64I-LABEL: fsgnj_s:
298; RV64I:       # %bb.0:
299; RV64I-NEXT:    lui a2, 524288
300; RV64I-NEXT:    and a1, a1, a2
301; RV64I-NEXT:    addiw a2, a2, -1
302; RV64I-NEXT:    and a0, a0, a2
303; RV64I-NEXT:    or a0, a0, a1
304; RV64I-NEXT:    ret
305  %1 = call float @llvm.copysign.f32(float %a, float %b)
306  ret float %1
307}
308
309declare float @llvm.minnum.f32(float, float)
310
311define float @fmin_s(float %a, float %b) nounwind {
312; RV64I-LABEL: fmin_s:
313; RV64I:       # %bb.0:
314; RV64I-NEXT:    addi sp, sp, -16
315; RV64I-NEXT:    sd ra, 8(sp)
316; RV64I-NEXT:    call fminf
317; RV64I-NEXT:    ld ra, 8(sp)
318; RV64I-NEXT:    addi sp, sp, 16
319; RV64I-NEXT:    ret
320  %1 = call float @llvm.minnum.f32(float %a, float %b)
321  ret float %1
322}
323
324declare float @llvm.maxnum.f32(float, float)
325
326define float @fmax_s(float %a, float %b) nounwind {
327; RV64I-LABEL: fmax_s:
328; RV64I:       # %bb.0:
329; RV64I-NEXT:    addi sp, sp, -16
330; RV64I-NEXT:    sd ra, 8(sp)
331; RV64I-NEXT:    call fmaxf
332; RV64I-NEXT:    ld ra, 8(sp)
333; RV64I-NEXT:    addi sp, sp, 16
334; RV64I-NEXT:    ret
335  %1 = call float @llvm.maxnum.f32(float %a, float %b)
336  ret float %1
337}
338
339
340declare float @llvm.fma.f32(float, float, float)
341
342define float @fmadd_s(float %a, float %b, float %c) nounwind {
343; RV64I-LABEL: fmadd_s:
344; RV64I:       # %bb.0:
345; RV64I-NEXT:    addi sp, sp, -16
346; RV64I-NEXT:    sd ra, 8(sp)
347; RV64I-NEXT:    call fmaf
348; RV64I-NEXT:    ld ra, 8(sp)
349; RV64I-NEXT:    addi sp, sp, 16
350; RV64I-NEXT:    ret
351  %1 = call float @llvm.fma.f32(float %a, float %b, float %c)
352  ret float %1
353}
354
355define float @fmsub_s(float %a, float %b, float %c) nounwind {
356; RV64I-LABEL: fmsub_s:
357; RV64I:       # %bb.0:
358; RV64I-NEXT:    addi sp, sp, -32
359; RV64I-NEXT:    sd ra, 24(sp)
360; RV64I-NEXT:    sd s0, 16(sp)
361; RV64I-NEXT:    sd s1, 8(sp)
362; RV64I-NEXT:    mv s0, a1
363; RV64I-NEXT:    mv s1, a0
364; RV64I-NEXT:    mv a0, a2
365; RV64I-NEXT:    mv a1, zero
366; RV64I-NEXT:    call __addsf3
367; RV64I-NEXT:    lui a1, 524288
368; RV64I-NEXT:    xor a2, a0, a1
369; RV64I-NEXT:    mv a0, s1
370; RV64I-NEXT:    mv a1, s0
371; RV64I-NEXT:    call fmaf
372; RV64I-NEXT:    ld s1, 8(sp)
373; RV64I-NEXT:    ld s0, 16(sp)
374; RV64I-NEXT:    ld ra, 24(sp)
375; RV64I-NEXT:    addi sp, sp, 32
376; RV64I-NEXT:    ret
377  %c_ = fadd float 0.0, %c ; avoid negation using xor
378  %negc = fsub float -0.0, %c_
379  %1 = call float @llvm.fma.f32(float %a, float %b, float %negc)
380  ret float %1
381}
382
383define float @fnmadd_s(float %a, float %b, float %c) nounwind {
384; RV64I-LABEL: fnmadd_s:
385; RV64I:       # %bb.0:
386; RV64I-NEXT:    addi sp, sp, -32
387; RV64I-NEXT:    sd ra, 24(sp)
388; RV64I-NEXT:    sd s0, 16(sp)
389; RV64I-NEXT:    sd s1, 8(sp)
390; RV64I-NEXT:    sd s2, 0(sp)
391; RV64I-NEXT:    mv s0, a2
392; RV64I-NEXT:    mv s2, a1
393; RV64I-NEXT:    mv a1, zero
394; RV64I-NEXT:    call __addsf3
395; RV64I-NEXT:    mv s1, a0
396; RV64I-NEXT:    mv a0, s0
397; RV64I-NEXT:    mv a1, zero
398; RV64I-NEXT:    call __addsf3
399; RV64I-NEXT:    lui a2, 524288
400; RV64I-NEXT:    xor a1, s1, a2
401; RV64I-NEXT:    xor a2, a0, a2
402; RV64I-NEXT:    mv a0, a1
403; RV64I-NEXT:    mv a1, s2
404; RV64I-NEXT:    call fmaf
405; RV64I-NEXT:    ld s2, 0(sp)
406; RV64I-NEXT:    ld s1, 8(sp)
407; RV64I-NEXT:    ld s0, 16(sp)
408; RV64I-NEXT:    ld ra, 24(sp)
409; RV64I-NEXT:    addi sp, sp, 32
410; RV64I-NEXT:    ret
411  %a_ = fadd float 0.0, %a
412  %c_ = fadd float 0.0, %c
413  %nega = fsub float -0.0, %a_
414  %negc = fsub float -0.0, %c_
415  %1 = call float @llvm.fma.f32(float %nega, float %b, float %negc)
416  ret float %1
417}
418
419define float @fnmsub_s(float %a, float %b, float %c) nounwind {
420; RV64I-LABEL: fnmsub_s:
421; RV64I:       # %bb.0:
422; RV64I-NEXT:    addi sp, sp, -32
423; RV64I-NEXT:    sd ra, 24(sp)
424; RV64I-NEXT:    sd s0, 16(sp)
425; RV64I-NEXT:    sd s1, 8(sp)
426; RV64I-NEXT:    mv s0, a2
427; RV64I-NEXT:    mv s1, a1
428; RV64I-NEXT:    mv a1, zero
429; RV64I-NEXT:    call __addsf3
430; RV64I-NEXT:    lui a1, 524288
431; RV64I-NEXT:    xor a0, a0, a1
432; RV64I-NEXT:    mv a1, s1
433; RV64I-NEXT:    mv a2, s0
434; RV64I-NEXT:    call fmaf
435; RV64I-NEXT:    ld s1, 8(sp)
436; RV64I-NEXT:    ld s0, 16(sp)
437; RV64I-NEXT:    ld ra, 24(sp)
438; RV64I-NEXT:    addi sp, sp, 32
439; RV64I-NEXT:    ret
440  %a_ = fadd float 0.0, %a
441  %nega = fsub float -0.0, %a_
442  %1 = call float @llvm.fma.f32(float %nega, float %b, float %c)
443  ret float %1
444}
445
446declare float @llvm.ceil.f32(float)
447
448define float @fceil_s(float %a) nounwind {
449; RV64I-LABEL: fceil_s:
450; RV64I:       # %bb.0:
451; RV64I-NEXT:    addi sp, sp, -16
452; RV64I-NEXT:    sd ra, 8(sp)
453; RV64I-NEXT:    call ceilf
454; RV64I-NEXT:    ld ra, 8(sp)
455; RV64I-NEXT:    addi sp, sp, 16
456; RV64I-NEXT:    ret
457  %1 = call float @llvm.ceil.f32(float %a)
458  ret float %1
459}
460
461declare float @llvm.cos.f32(float)
462
463define float @fcos_s(float %a) nounwind {
464; RV64I-LABEL: fcos_s:
465; RV64I:       # %bb.0:
466; RV64I-NEXT:    addi sp, sp, -16
467; RV64I-NEXT:    sd ra, 8(sp)
468; RV64I-NEXT:    call cosf
469; RV64I-NEXT:    ld ra, 8(sp)
470; RV64I-NEXT:    addi sp, sp, 16
471; RV64I-NEXT:    ret
472  %1 = call float @llvm.cos.f32(float %a)
473  ret float %1
474}
475
476declare float @llvm.sin.f32(float)
477
478define float @fsin_s(float %a) nounwind {
479; RV64I-LABEL: fsin_s:
480; RV64I:       # %bb.0:
481; RV64I-NEXT:    addi sp, sp, -16
482; RV64I-NEXT:    sd ra, 8(sp)
483; RV64I-NEXT:    call sinf
484; RV64I-NEXT:    ld ra, 8(sp)
485; RV64I-NEXT:    addi sp, sp, 16
486; RV64I-NEXT:    ret
487  %1 = call float @llvm.sin.f32(float %a)
488  ret float %1
489}
490
491declare float @llvm.exp.f32(float)
492
493define float @fexp_s(float %a) nounwind {
494; RV64I-LABEL: fexp_s:
495; RV64I:       # %bb.0:
496; RV64I-NEXT:    addi sp, sp, -16
497; RV64I-NEXT:    sd ra, 8(sp)
498; RV64I-NEXT:    call expf
499; RV64I-NEXT:    ld ra, 8(sp)
500; RV64I-NEXT:    addi sp, sp, 16
501; RV64I-NEXT:    ret
502  %1 = call float @llvm.exp.f32(float %a)
503  ret float %1
504}
505
506declare float @llvm.exp2.f32(float)
507
508define float @fexp2_s(float %a) nounwind {
509; RV64I-LABEL: fexp2_s:
510; RV64I:       # %bb.0:
511; RV64I-NEXT:    addi sp, sp, -16
512; RV64I-NEXT:    sd ra, 8(sp)
513; RV64I-NEXT:    call exp2f
514; RV64I-NEXT:    ld ra, 8(sp)
515; RV64I-NEXT:    addi sp, sp, 16
516; RV64I-NEXT:    ret
517  %1 = call float @llvm.exp2.f32(float %a)
518  ret float %1
519}
520
521declare float @llvm.floor.f32(float)
522
523define float @ffloor_s(float %a) nounwind {
524; RV64I-LABEL: ffloor_s:
525; RV64I:       # %bb.0:
526; RV64I-NEXT:    addi sp, sp, -16
527; RV64I-NEXT:    sd ra, 8(sp)
528; RV64I-NEXT:    call floorf
529; RV64I-NEXT:    ld ra, 8(sp)
530; RV64I-NEXT:    addi sp, sp, 16
531; RV64I-NEXT:    ret
532  %1 = call float @llvm.floor.f32(float %a)
533  ret float %1
534}
535
536declare float @llvm.flog.f32(float)
537
538define float @fflog_s(float %a) nounwind {
539; RV64I-LABEL: fflog_s:
540; RV64I:       # %bb.0:
541; RV64I-NEXT:    addi sp, sp, -16
542; RV64I-NEXT:    sd ra, 8(sp)
543; RV64I-NEXT:    call llvm.flog.f32
544; RV64I-NEXT:    ld ra, 8(sp)
545; RV64I-NEXT:    addi sp, sp, 16
546; RV64I-NEXT:    ret
547  %1 = call float @llvm.flog.f32(float %a)
548  ret float %1
549}
550
551declare float @llvm.flog2.f32(float)
552
553define float @fflog2_s(float %a) nounwind {
554; RV64I-LABEL: fflog2_s:
555; RV64I:       # %bb.0:
556; RV64I-NEXT:    addi sp, sp, -16
557; RV64I-NEXT:    sd ra, 8(sp)
558; RV64I-NEXT:    call llvm.flog2.f32
559; RV64I-NEXT:    ld ra, 8(sp)
560; RV64I-NEXT:    addi sp, sp, 16
561; RV64I-NEXT:    ret
562  %1 = call float @llvm.flog2.f32(float %a)
563  ret float %1
564}
565
566declare float @llvm.flog10.f32(float)
567
568define float @fflog10_s(float %a) nounwind {
569; RV64I-LABEL: fflog10_s:
570; RV64I:       # %bb.0:
571; RV64I-NEXT:    addi sp, sp, -16
572; RV64I-NEXT:    sd ra, 8(sp)
573; RV64I-NEXT:    call llvm.flog10.f32
574; RV64I-NEXT:    ld ra, 8(sp)
575; RV64I-NEXT:    addi sp, sp, 16
576; RV64I-NEXT:    ret
577  %1 = call float @llvm.flog10.f32(float %a)
578  ret float %1
579}
580
581declare float @llvm.fnearbyint.f32(float)
582
583define float @fnearbyint_s(float %a) nounwind {
584; RV64I-LABEL: fnearbyint_s:
585; RV64I:       # %bb.0:
586; RV64I-NEXT:    addi sp, sp, -16
587; RV64I-NEXT:    sd ra, 8(sp)
588; RV64I-NEXT:    call llvm.fnearbyint.f32
589; RV64I-NEXT:    ld ra, 8(sp)
590; RV64I-NEXT:    addi sp, sp, 16
591; RV64I-NEXT:    ret
592  %1 = call float @llvm.fnearbyint.f32(float %a)
593  ret float %1
594}
595
596declare float @llvm.round.f32(float)
597
598define float @fround_s(float %a) nounwind {
599; RV64I-LABEL: fround_s:
600; RV64I:       # %bb.0:
601; RV64I-NEXT:    addi sp, sp, -16
602; RV64I-NEXT:    sd ra, 8(sp)
603; RV64I-NEXT:    call roundf
604; RV64I-NEXT:    ld ra, 8(sp)
605; RV64I-NEXT:    addi sp, sp, 16
606; RV64I-NEXT:    ret
607  %1 = call float @llvm.round.f32(float %a)
608  ret float %1
609}
610
611declare float @llvm.fpround.f32(float)
612
613define float @fpround_s(float %a) nounwind {
614; RV64I-LABEL: fpround_s:
615; RV64I:       # %bb.0:
616; RV64I-NEXT:    addi sp, sp, -16
617; RV64I-NEXT:    sd ra, 8(sp)
618; RV64I-NEXT:    call llvm.fpround.f32
619; RV64I-NEXT:    ld ra, 8(sp)
620; RV64I-NEXT:    addi sp, sp, 16
621; RV64I-NEXT:    ret
622  %1 = call float @llvm.fpround.f32(float %a)
623  ret float %1
624}
625
626declare float @llvm.rint.f32(float)
627
628define float @frint_s(float %a) nounwind {
629; RV64I-LABEL: frint_s:
630; RV64I:       # %bb.0:
631; RV64I-NEXT:    addi sp, sp, -16
632; RV64I-NEXT:    sd ra, 8(sp)
633; RV64I-NEXT:    call rintf
634; RV64I-NEXT:    ld ra, 8(sp)
635; RV64I-NEXT:    addi sp, sp, 16
636; RV64I-NEXT:    ret
637  %1 = call float @llvm.rint.f32(float %a)
638  ret float %1
639}
640
641declare float @llvm.rem.f32(float)
642
643define float @frem_s(float %a) nounwind {
644; RV64I-LABEL: frem_s:
645; RV64I:       # %bb.0:
646; RV64I-NEXT:    addi sp, sp, -16
647; RV64I-NEXT:    sd ra, 8(sp)
648; RV64I-NEXT:    call llvm.rem.f32
649; RV64I-NEXT:    ld ra, 8(sp)
650; RV64I-NEXT:    addi sp, sp, 16
651; RV64I-NEXT:    ret
652  %1 = call float @llvm.rem.f32(float %a)
653  ret float %1
654}
655
656declare float @llvm.pow.f32(float %Val, float %power)
657
658define float @fpow_s(float %a, float %b) nounwind {
659; RV64I-LABEL: fpow_s:
660; RV64I:       # %bb.0:
661; RV64I-NEXT:    addi sp, sp, -16
662; RV64I-NEXT:    sd ra, 8(sp)
663; RV64I-NEXT:    call powf
664; RV64I-NEXT:    ld ra, 8(sp)
665; RV64I-NEXT:    addi sp, sp, 16
666; RV64I-NEXT:    ret
667  %1 = call float @llvm.pow.f32(float %a, float %b)
668  ret float %1
669}
670
671declare float @llvm.powi.f32(float %Val, i32 %power)
672
673define float @fpowi_s(float %a, i32 %b) nounwind {
674; RV64I-LABEL: fpowi_s:
675; RV64I:       # %bb.0:
676; RV64I-NEXT:    addi sp, sp, -16
677; RV64I-NEXT:    sd ra, 8(sp)
678; RV64I-NEXT:    slli a1, a1, 32
679; RV64I-NEXT:    srli a1, a1, 32
680; RV64I-NEXT:    call __powisf2
681; RV64I-NEXT:    ld ra, 8(sp)
682; RV64I-NEXT:    addi sp, sp, 16
683; RV64I-NEXT:    ret
684  %1 = call float @llvm.powi.f32(float %a, i32 %b)
685  ret float %1
686}
687
688define double @fp_ext(float %a) nounwind {
689; RV64I-LABEL: fp_ext:
690; RV64I:       # %bb.0:
691; RV64I-NEXT:    addi sp, sp, -16
692; RV64I-NEXT:    sd ra, 8(sp)
693; RV64I-NEXT:    call __extendsfdf2
694; RV64I-NEXT:    ld ra, 8(sp)
695; RV64I-NEXT:    addi sp, sp, 16
696; RV64I-NEXT:    ret
697  %conv = fpext float %a to double
698  ret double %conv
699}
700
701define float @fp_trunc(double %a) nounwind {
702; RV64I-LABEL: fp_trunc:
703; RV64I:       # %bb.0:
704; RV64I-NEXT:    addi sp, sp, -16
705; RV64I-NEXT:    sd ra, 8(sp)
706; RV64I-NEXT:    call __truncdfsf2
707; RV64I-NEXT:    ld ra, 8(sp)
708; RV64I-NEXT:    addi sp, sp, 16
709; RV64I-NEXT:    ret
710  %conv = fptrunc double %a to float
711  ret float %conv
712}
713
714define i32 @fp32_to_ui32(float %a) nounwind {
715; RV64I-LABEL: fp32_to_ui32:
716; RV64I:       # %bb.0: # %entry
717; RV64I-NEXT:    addi sp, sp, -16
718; RV64I-NEXT:    sd ra, 8(sp)
719; RV64I-NEXT:    call __fixunssfsi
720; RV64I-NEXT:    ld ra, 8(sp)
721; RV64I-NEXT:    addi sp, sp, 16
722; RV64I-NEXT:    ret
723entry:
724  %conv = fptoui float %a to i32
725  ret i32 %conv
726}
727
728define i32 @fp32_to_si32(float %a) nounwind  {
729; RV64I-LABEL: fp32_to_si32:
730; RV64I:       # %bb.0: # %entry
731; RV64I-NEXT:    addi sp, sp, -16
732; RV64I-NEXT:    sd ra, 8(sp)
733; RV64I-NEXT:    call __fixsfsi
734; RV64I-NEXT:    ld ra, 8(sp)
735; RV64I-NEXT:    addi sp, sp, 16
736; RV64I-NEXT:    ret
737entry:
738  %conv = fptosi float %a to i32
739  ret i32 %conv
740}
741
742define i32 @fp64_to_ui32(double %a) nounwind {
743; RV64I-LABEL: fp64_to_ui32:
744; RV64I:       # %bb.0: # %entry
745; RV64I-NEXT:    addi sp, sp, -16
746; RV64I-NEXT:    sd ra, 8(sp)
747; RV64I-NEXT:    call __fixunsdfsi
748; RV64I-NEXT:    ld ra, 8(sp)
749; RV64I-NEXT:    addi sp, sp, 16
750; RV64I-NEXT:    ret
751entry:
752  %conv = fptoui double %a to i32
753  ret i32 %conv
754}
755
756define i32 @fp64_to_si32(double %a) nounwind {
757; RV64I-LABEL: fp64_to_si32:
758; RV64I:       # %bb.0: # %entry
759; RV64I-NEXT:    addi sp, sp, -16
760; RV64I-NEXT:    sd ra, 8(sp)
761; RV64I-NEXT:    call __fixdfsi
762; RV64I-NEXT:    ld ra, 8(sp)
763; RV64I-NEXT:    addi sp, sp, 16
764; RV64I-NEXT:    ret
765entry:
766  %conv = fptosi double %a to i32
767  ret i32 %conv
768}
769
770
771
772declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata)
773declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata)
774declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)
775declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata)
776
777define i32 @strict_fp32_to_ui32(float %a) nounwind strictfp {
778; RV64I-LABEL: strict_fp32_to_ui32:
779; RV64I:       # %bb.0: # %entry
780; RV64I-NEXT:    addi sp, sp, -16
781; RV64I-NEXT:    sd ra, 8(sp)
782; RV64I-NEXT:    call __fixunssfsi
783; RV64I-NEXT:    ld ra, 8(sp)
784; RV64I-NEXT:    addi sp, sp, 16
785; RV64I-NEXT:    ret
786entry:
787  %conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict")
788  ret i32 %conv
789}
790
791define i32 @strict_fp32_to_si32(float %a) nounwind strictfp {
792; RV64I-LABEL: strict_fp32_to_si32:
793; RV64I:       # %bb.0: # %entry
794; RV64I-NEXT:    addi sp, sp, -16
795; RV64I-NEXT:    sd ra, 8(sp)
796; RV64I-NEXT:    call __fixsfsi
797; RV64I-NEXT:    ld ra, 8(sp)
798; RV64I-NEXT:    addi sp, sp, 16
799; RV64I-NEXT:    ret
800entry:
801  %conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict")
802  ret i32 %conv
803}
804
805define i32 @strict_fp64_to_ui32(double %a) nounwind strictfp {
806; RV64I-LABEL: strict_fp64_to_ui32:
807; RV64I:       # %bb.0: # %entry
808; RV64I-NEXT:    addi sp, sp, -16
809; RV64I-NEXT:    sd ra, 8(sp)
810; RV64I-NEXT:    call __fixunsdfsi
811; RV64I-NEXT:    ld ra, 8(sp)
812; RV64I-NEXT:    addi sp, sp, 16
813; RV64I-NEXT:    ret
814entry:
815  %conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %a, metadata !"fpexcept.strict")
816  ret i32 %conv
817}
818
819define i32 @struct_fp64_to_si32(double %a) nounwind strictfp {
820; RV64I-LABEL: struct_fp64_to_si32:
821; RV64I:       # %bb.0: # %entry
822; RV64I-NEXT:    addi sp, sp, -16
823; RV64I-NEXT:    sd ra, 8(sp)
824; RV64I-NEXT:    call __fixdfsi
825; RV64I-NEXT:    ld ra, 8(sp)
826; RV64I-NEXT:    addi sp, sp, 16
827; RV64I-NEXT:    ret
828entry:
829  %conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict")
830  ret i32 %conv
831}
832
833