1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV64IF
4
5; This file exhaustively checks float<->i32 conversions. In general,
6; fcvt.l[u].s can be selected instead of fcvt.w[u].s because poison is
7; generated for an fpto[s|u]i conversion if the result doesn't fit in the
8; target type.
9
10define i32 @aext_fptosi(float %a) nounwind {
11; RV64IF-LABEL: aext_fptosi:
12; RV64IF:       # %bb.0:
13; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
14; RV64IF-NEXT:    ret
15  %1 = fptosi float %a to i32
16  ret i32 %1
17}
18
19define signext i32 @sext_fptosi(float %a) nounwind {
20; RV64IF-LABEL: sext_fptosi:
21; RV64IF:       # %bb.0:
22; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
23; RV64IF-NEXT:    ret
24  %1 = fptosi float %a to i32
25  ret i32 %1
26}
27
28define zeroext i32 @zext_fptosi(float %a) nounwind {
29; RV64IF-LABEL: zext_fptosi:
30; RV64IF:       # %bb.0:
31; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
32; RV64IF-NEXT:    slli a0, a0, 32
33; RV64IF-NEXT:    srli a0, a0, 32
34; RV64IF-NEXT:    ret
35  %1 = fptosi float %a to i32
36  ret i32 %1
37}
38
39define i32 @aext_fptoui(float %a) nounwind {
40; RV64IF-LABEL: aext_fptoui:
41; RV64IF:       # %bb.0:
42; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
43; RV64IF-NEXT:    ret
44  %1 = fptoui float %a to i32
45  ret i32 %1
46}
47
48define signext i32 @sext_fptoui(float %a) nounwind {
49; RV64IF-LABEL: sext_fptoui:
50; RV64IF:       # %bb.0:
51; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
52; RV64IF-NEXT:    ret
53  %1 = fptoui float %a to i32
54  ret i32 %1
55}
56
57define zeroext i32 @zext_fptoui(float %a) nounwind {
58; RV64IF-LABEL: zext_fptoui:
59; RV64IF:       # %bb.0:
60; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
61; RV64IF-NEXT:    ret
62  %1 = fptoui float %a to i32
63  ret i32 %1
64}
65
66define i32 @bcvt_f32_to_aext_i32(float %a, float %b) nounwind {
67; RV64IF-LABEL: bcvt_f32_to_aext_i32:
68; RV64IF:       # %bb.0:
69; RV64IF-NEXT:    fadd.s ft0, fa0, fa1
70; RV64IF-NEXT:    fmv.x.w a0, ft0
71; RV64IF-NEXT:    ret
72  %1 = fadd float %a, %b
73  %2 = bitcast float %1 to i32
74  ret i32 %2
75}
76
77define signext i32 @bcvt_f32_to_sext_i32(float %a, float %b) nounwind {
78; RV64IF-LABEL: bcvt_f32_to_sext_i32:
79; RV64IF:       # %bb.0:
80; RV64IF-NEXT:    fadd.s ft0, fa0, fa1
81; RV64IF-NEXT:    fmv.x.w a0, ft0
82; RV64IF-NEXT:    ret
83  %1 = fadd float %a, %b
84  %2 = bitcast float %1 to i32
85  ret i32 %2
86}
87
88define zeroext i32 @bcvt_f32_to_zext_i32(float %a, float %b) nounwind {
89; RV64IF-LABEL: bcvt_f32_to_zext_i32:
90; RV64IF:       # %bb.0:
91; RV64IF-NEXT:    fadd.s ft0, fa0, fa1
92; RV64IF-NEXT:    fmv.x.w a0, ft0
93; RV64IF-NEXT:    slli a0, a0, 32
94; RV64IF-NEXT:    srli a0, a0, 32
95; RV64IF-NEXT:    ret
96  %1 = fadd float %a, %b
97  %2 = bitcast float %1 to i32
98  ret i32 %2
99}
100
101define float @bcvt_i64_to_f32_via_i32(i64 %a, i64 %b) nounwind {
102; RV64IF-LABEL: bcvt_i64_to_f32_via_i32:
103; RV64IF:       # %bb.0:
104; RV64IF-NEXT:    fmv.w.x ft0, a0
105; RV64IF-NEXT:    fmv.w.x ft1, a1
106; RV64IF-NEXT:    fadd.s fa0, ft0, ft1
107; RV64IF-NEXT:    ret
108  %1 = trunc i64 %a to i32
109  %2 = trunc i64 %b to i32
110  %3 = bitcast i32 %1 to float
111  %4 = bitcast i32 %2 to float
112  %5 = fadd float %3, %4
113  ret float %5
114}
115
116define float @uitofp_aext_i32_to_f32(i32 %a) nounwind {
117; RV64IF-LABEL: uitofp_aext_i32_to_f32:
118; RV64IF:       # %bb.0:
119; RV64IF-NEXT:    fcvt.s.wu fa0, a0
120; RV64IF-NEXT:    ret
121  %1 = uitofp i32 %a to float
122  ret float %1
123}
124
125define float @uitofp_sext_i32_to_f32(i32 signext %a) nounwind {
126; RV64IF-LABEL: uitofp_sext_i32_to_f32:
127; RV64IF:       # %bb.0:
128; RV64IF-NEXT:    fcvt.s.wu fa0, a0
129; RV64IF-NEXT:    ret
130  %1 = uitofp i32 %a to float
131  ret float %1
132}
133
134define float @uitofp_zext_i32_to_f32(i32 zeroext %a) nounwind {
135; RV64IF-LABEL: uitofp_zext_i32_to_f32:
136; RV64IF:       # %bb.0:
137; RV64IF-NEXT:    fcvt.s.wu fa0, a0
138; RV64IF-NEXT:    ret
139  %1 = uitofp i32 %a to float
140  ret float %1
141}
142
143define float @sitofp_aext_i32_to_f32(i32 %a) nounwind {
144; RV64IF-LABEL: sitofp_aext_i32_to_f32:
145; RV64IF:       # %bb.0:
146; RV64IF-NEXT:    fcvt.s.w fa0, a0
147; RV64IF-NEXT:    ret
148  %1 = sitofp i32 %a to float
149  ret float %1
150}
151
152define float @sitofp_sext_i32_to_f32(i32 signext %a) nounwind {
153; RV64IF-LABEL: sitofp_sext_i32_to_f32:
154; RV64IF:       # %bb.0:
155; RV64IF-NEXT:    fcvt.s.w fa0, a0
156; RV64IF-NEXT:    ret
157  %1 = sitofp i32 %a to float
158  ret float %1
159}
160
161define float @sitofp_zext_i32_to_f32(i32 zeroext %a) nounwind {
162; RV64IF-LABEL: sitofp_zext_i32_to_f32:
163; RV64IF:       # %bb.0:
164; RV64IF-NEXT:    fcvt.s.w fa0, a0
165; RV64IF-NEXT:    ret
166  %1 = sitofp i32 %a to float
167  ret float %1
168}
169