1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32I-FPELIM %s
4; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all < %s \
5; RUN:   | FileCheck -check-prefix=RV32I-WITHFP %s
6
7; TODO: the quality of the generated code is poor
8
9define void @test() nounwind {
10; RV32I-FPELIM-LABEL: test:
11; RV32I-FPELIM:       # %bb.0:
12; RV32I-FPELIM-NEXT:    lui a0, 74565
13; RV32I-FPELIM-NEXT:    addi a0, a0, 1664
14; RV32I-FPELIM-NEXT:    sub sp, sp, a0
15; RV32I-FPELIM-NEXT:    lui a0, 74565
16; RV32I-FPELIM-NEXT:    addi a0, a0, 1664
17; RV32I-FPELIM-NEXT:    add sp, sp, a0
18; RV32I-FPELIM-NEXT:    ret
19;
20; RV32I-WITHFP-LABEL: test:
21; RV32I-WITHFP:       # %bb.0:
22; RV32I-WITHFP-NEXT:    lui a0, 74565
23; RV32I-WITHFP-NEXT:    addi a0, a0, 1680
24; RV32I-WITHFP-NEXT:    sub sp, sp, a0
25; RV32I-WITHFP-NEXT:    lui a0, 74565
26; RV32I-WITHFP-NEXT:    addi a0, a0, 1676
27; RV32I-WITHFP-NEXT:    add a0, sp, a0
28; RV32I-WITHFP-NEXT:    sw ra, 0(a0)
29; RV32I-WITHFP-NEXT:    lui a0, 74565
30; RV32I-WITHFP-NEXT:    addi a0, a0, 1672
31; RV32I-WITHFP-NEXT:    add a0, sp, a0
32; RV32I-WITHFP-NEXT:    sw s0, 0(a0)
33; RV32I-WITHFP-NEXT:    lui a0, 74565
34; RV32I-WITHFP-NEXT:    addi a0, a0, 1680
35; RV32I-WITHFP-NEXT:    add s0, sp, a0
36; RV32I-WITHFP-NEXT:    lui a0, 74565
37; RV32I-WITHFP-NEXT:    addi a0, a0, 1672
38; RV32I-WITHFP-NEXT:    add a0, sp, a0
39; RV32I-WITHFP-NEXT:    lw s0, 0(a0)
40; RV32I-WITHFP-NEXT:    lui a0, 74565
41; RV32I-WITHFP-NEXT:    addi a0, a0, 1676
42; RV32I-WITHFP-NEXT:    add a0, sp, a0
43; RV32I-WITHFP-NEXT:    lw ra, 0(a0)
44; RV32I-WITHFP-NEXT:    lui a0, 74565
45; RV32I-WITHFP-NEXT:    addi a0, a0, 1680
46; RV32I-WITHFP-NEXT:    add sp, sp, a0
47; RV32I-WITHFP-NEXT:    ret
48  %tmp = alloca [ 305419896 x i8 ] , align 4
49  ret void
50}
51
52; This test case artificially produces register pressure which should force
53; use of the emergency spill slot.
54
55define void @test_emergency_spill_slot(i32 %a) nounwind {
56; RV32I-FPELIM-LABEL: test_emergency_spill_slot:
57; RV32I-FPELIM:       # %bb.0:
58; RV32I-FPELIM-NEXT:    lui a1, 98
59; RV32I-FPELIM-NEXT:    addi a1, a1, -1392
60; RV32I-FPELIM-NEXT:    sub sp, sp, a1
61; RV32I-FPELIM-NEXT:    lui a1, 98
62; RV32I-FPELIM-NEXT:    addi a1, a1, -1396
63; RV32I-FPELIM-NEXT:    add a1, sp, a1
64; RV32I-FPELIM-NEXT:    sw s0, 0(a1)
65; RV32I-FPELIM-NEXT:    lui a1, 98
66; RV32I-FPELIM-NEXT:    addi a1, a1, -1400
67; RV32I-FPELIM-NEXT:    add a1, sp, a1
68; RV32I-FPELIM-NEXT:    sw s1, 0(a1)
69; RV32I-FPELIM-NEXT:    lui a1, 78
70; RV32I-FPELIM-NEXT:    addi a1, a1, 512
71; RV32I-FPELIM-NEXT:    addi a2, sp, 8
72; RV32I-FPELIM-NEXT:    add a1, a2, a1
73; RV32I-FPELIM-NEXT:    #APP
74; RV32I-FPELIM-NEXT:    nop
75; RV32I-FPELIM-NEXT:    #NO_APP
76; RV32I-FPELIM-NEXT:    sw a0, 0(a1)
77; RV32I-FPELIM-NEXT:    #APP
78; RV32I-FPELIM-NEXT:    nop
79; RV32I-FPELIM-NEXT:    #NO_APP
80; RV32I-FPELIM-NEXT:    lui a0, 98
81; RV32I-FPELIM-NEXT:    addi a0, a0, -1400
82; RV32I-FPELIM-NEXT:    add a0, sp, a0
83; RV32I-FPELIM-NEXT:    lw s1, 0(a0)
84; RV32I-FPELIM-NEXT:    lui a0, 98
85; RV32I-FPELIM-NEXT:    addi a0, a0, -1396
86; RV32I-FPELIM-NEXT:    add a0, sp, a0
87; RV32I-FPELIM-NEXT:    lw s0, 0(a0)
88; RV32I-FPELIM-NEXT:    lui a0, 98
89; RV32I-FPELIM-NEXT:    addi a0, a0, -1392
90; RV32I-FPELIM-NEXT:    add sp, sp, a0
91; RV32I-FPELIM-NEXT:    ret
92;
93; RV32I-WITHFP-LABEL: test_emergency_spill_slot:
94; RV32I-WITHFP:       # %bb.0:
95; RV32I-WITHFP-NEXT:    lui a1, 98
96; RV32I-WITHFP-NEXT:    addi a1, a1, -1376
97; RV32I-WITHFP-NEXT:    sub sp, sp, a1
98; RV32I-WITHFP-NEXT:    lui a1, 98
99; RV32I-WITHFP-NEXT:    addi a1, a1, -1380
100; RV32I-WITHFP-NEXT:    add a1, sp, a1
101; RV32I-WITHFP-NEXT:    sw ra, 0(a1)
102; RV32I-WITHFP-NEXT:    lui a1, 98
103; RV32I-WITHFP-NEXT:    addi a1, a1, -1384
104; RV32I-WITHFP-NEXT:    add a1, sp, a1
105; RV32I-WITHFP-NEXT:    sw s0, 0(a1)
106; RV32I-WITHFP-NEXT:    lui a1, 98
107; RV32I-WITHFP-NEXT:    addi a1, a1, -1388
108; RV32I-WITHFP-NEXT:    add a1, sp, a1
109; RV32I-WITHFP-NEXT:    sw s1, 0(a1)
110; RV32I-WITHFP-NEXT:    lui a1, 98
111; RV32I-WITHFP-NEXT:    addi a1, a1, -1392
112; RV32I-WITHFP-NEXT:    add a1, sp, a1
113; RV32I-WITHFP-NEXT:    sw s2, 0(a1)
114; RV32I-WITHFP-NEXT:    lui a1, 98
115; RV32I-WITHFP-NEXT:    addi a1, a1, -1376
116; RV32I-WITHFP-NEXT:    add s0, sp, a1
117; RV32I-WITHFP-NEXT:    lui a1, 78
118; RV32I-WITHFP-NEXT:    addi a1, a1, 512
119; RV32I-WITHFP-NEXT:    lui a2, 1048478
120; RV32I-WITHFP-NEXT:    addi a2, a2, 1388
121; RV32I-WITHFP-NEXT:    add a2, s0, a2
122; RV32I-WITHFP-NEXT:    mv a2, a2
123; RV32I-WITHFP-NEXT:    add a1, a2, a1
124; RV32I-WITHFP-NEXT:    #APP
125; RV32I-WITHFP-NEXT:    nop
126; RV32I-WITHFP-NEXT:    #NO_APP
127; RV32I-WITHFP-NEXT:    sw a0, 0(a1)
128; RV32I-WITHFP-NEXT:    #APP
129; RV32I-WITHFP-NEXT:    nop
130; RV32I-WITHFP-NEXT:    #NO_APP
131; RV32I-WITHFP-NEXT:    lui a0, 98
132; RV32I-WITHFP-NEXT:    addi a0, a0, -1392
133; RV32I-WITHFP-NEXT:    add a0, sp, a0
134; RV32I-WITHFP-NEXT:    lw s2, 0(a0)
135; RV32I-WITHFP-NEXT:    lui a0, 98
136; RV32I-WITHFP-NEXT:    addi a0, a0, -1388
137; RV32I-WITHFP-NEXT:    add a0, sp, a0
138; RV32I-WITHFP-NEXT:    lw s1, 0(a0)
139; RV32I-WITHFP-NEXT:    lui a0, 98
140; RV32I-WITHFP-NEXT:    addi a0, a0, -1384
141; RV32I-WITHFP-NEXT:    add a0, sp, a0
142; RV32I-WITHFP-NEXT:    lw s0, 0(a0)
143; RV32I-WITHFP-NEXT:    lui a0, 98
144; RV32I-WITHFP-NEXT:    addi a0, a0, -1380
145; RV32I-WITHFP-NEXT:    add a0, sp, a0
146; RV32I-WITHFP-NEXT:    lw ra, 0(a0)
147; RV32I-WITHFP-NEXT:    lui a0, 98
148; RV32I-WITHFP-NEXT:    addi a0, a0, -1376
149; RV32I-WITHFP-NEXT:    add sp, sp, a0
150; RV32I-WITHFP-NEXT:    ret
151  %data = alloca [ 100000 x i32 ] , align 4
152  %ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %data, i32 0, i32 80000
153  %1 = tail call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "nop", "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r"()
154  %asmresult0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 0
155  %asmresult1 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 1
156  %asmresult2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 2
157  %asmresult3 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 3
158  %asmresult4 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 4
159  %asmresult5 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 5
160  %asmresult6 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 6
161  %asmresult7 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 7
162  %asmresult8 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 8
163  %asmresult9 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 9
164  %asmresult10 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 10
165  %asmresult11 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 11
166  %asmresult12 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 12
167  %asmresult13 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 13
168  %asmresult14 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 14
169  store volatile i32 %a, i32* %ptr
170  tail call void asm sideeffect "nop", "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r"(i32 %asmresult0, i32 %asmresult1, i32 %asmresult2, i32 %asmresult3, i32 %asmresult4, i32 %asmresult5, i32 %asmresult6, i32 %asmresult7, i32 %asmresult8, i32 %asmresult9, i32 %asmresult10, i32 %asmresult11, i32 %asmresult12, i32 %asmresult13, i32 %asmresult14)
171  ret void
172}
173