1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32I-FPELIM %s
4; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all < %s \
5; RUN:   | FileCheck -check-prefix=RV32I-WITHFP %s
6
7; TODO: the quality of the generated code is poor
8
9define void @test() {
10; RV32I-FPELIM-LABEL: test:
11; RV32I-FPELIM:       # %bb.0:
12; RV32I-FPELIM-NEXT:    lui a0, 74565
13; RV32I-FPELIM-NEXT:    addi a0, a0, 1664
14; RV32I-FPELIM-NEXT:    sub sp, sp, a0
15; RV32I-FPELIM-NEXT:    .cfi_def_cfa_offset 305419904
16; RV32I-FPELIM-NEXT:    lui a0, 74565
17; RV32I-FPELIM-NEXT:    addi a0, a0, 1664
18; RV32I-FPELIM-NEXT:    add sp, sp, a0
19; RV32I-FPELIM-NEXT:    .cfi_def_cfa_offset 0
20; RV32I-FPELIM-NEXT:    ret
21;
22; RV32I-WITHFP-LABEL: test:
23; RV32I-WITHFP:       # %bb.0:
24; RV32I-WITHFP-NEXT:    addi sp, sp, -2032
25; RV32I-WITHFP-NEXT:    .cfi_def_cfa_offset 2032
26; RV32I-WITHFP-NEXT:    sw ra, 2028(sp)
27; RV32I-WITHFP-NEXT:    sw s0, 2024(sp)
28; RV32I-WITHFP-NEXT:    .cfi_offset ra, -4
29; RV32I-WITHFP-NEXT:    .cfi_offset s0, -8
30; RV32I-WITHFP-NEXT:    addi s0, sp, 2032
31; RV32I-WITHFP-NEXT:    .cfi_def_cfa s0, 0
32; RV32I-WITHFP-NEXT:    lui a0, 74565
33; RV32I-WITHFP-NEXT:    addi a0, a0, -352
34; RV32I-WITHFP-NEXT:    sub sp, sp, a0
35; RV32I-WITHFP-NEXT:    .cfi_def_cfa_offset 305419920
36; RV32I-WITHFP-NEXT:    lui a0, 74565
37; RV32I-WITHFP-NEXT:    addi a0, a0, -352
38; RV32I-WITHFP-NEXT:    add sp, sp, a0
39; RV32I-WITHFP-NEXT:    .cfi_def_cfa_offset 2032
40; RV32I-WITHFP-NEXT:    lw s0, 2024(sp)
41; RV32I-WITHFP-NEXT:    .cfi_def_cfa sp, 305419920
42; RV32I-WITHFP-NEXT:    lw ra, 2028(sp)
43; RV32I-WITHFP-NEXT:    .cfi_restore ra
44; RV32I-WITHFP-NEXT:    .cfi_restore s0
45; RV32I-WITHFP-NEXT:    addi sp, sp, 2032
46; RV32I-WITHFP-NEXT:    .cfi_def_cfa_offset 0
47; RV32I-WITHFP-NEXT:    ret
48  %tmp = alloca [ 305419896 x i8 ] , align 4
49  ret void
50}
51
52; This test case artificially produces register pressure which should force
53; use of the emergency spill slot.
54
55define void @test_emergency_spill_slot(i32 %a) {
56; RV32I-FPELIM-LABEL: test_emergency_spill_slot:
57; RV32I-FPELIM:       # %bb.0:
58; RV32I-FPELIM-NEXT:    addi sp, sp, -2032
59; RV32I-FPELIM-NEXT:    .cfi_def_cfa_offset 2032
60; RV32I-FPELIM-NEXT:    sw s0, 2028(sp)
61; RV32I-FPELIM-NEXT:    sw s1, 2024(sp)
62; RV32I-FPELIM-NEXT:    .cfi_offset s0, -4
63; RV32I-FPELIM-NEXT:    .cfi_offset s1, -8
64; RV32I-FPELIM-NEXT:    lui a1, 97
65; RV32I-FPELIM-NEXT:    addi a1, a1, 672
66; RV32I-FPELIM-NEXT:    sub sp, sp, a1
67; RV32I-FPELIM-NEXT:    .cfi_def_cfa_offset 400016
68; RV32I-FPELIM-NEXT:    lui a1, 78
69; RV32I-FPELIM-NEXT:    addi a1, a1, 512
70; RV32I-FPELIM-NEXT:    addi a2, sp, 8
71; RV32I-FPELIM-NEXT:    add a1, a2, a1
72; RV32I-FPELIM-NEXT:    #APP
73; RV32I-FPELIM-NEXT:    nop
74; RV32I-FPELIM-NEXT:    #NO_APP
75; RV32I-FPELIM-NEXT:    sw a0, 0(a1)
76; RV32I-FPELIM-NEXT:    #APP
77; RV32I-FPELIM-NEXT:    nop
78; RV32I-FPELIM-NEXT:    #NO_APP
79; RV32I-FPELIM-NEXT:    lui a0, 97
80; RV32I-FPELIM-NEXT:    addi a0, a0, 672
81; RV32I-FPELIM-NEXT:    add sp, sp, a0
82; RV32I-FPELIM-NEXT:    .cfi_def_cfa_offset 2032
83; RV32I-FPELIM-NEXT:    lw s1, 2024(sp)
84; RV32I-FPELIM-NEXT:    lw s0, 2028(sp)
85; RV32I-FPELIM-NEXT:    .cfi_restore s0
86; RV32I-FPELIM-NEXT:    .cfi_restore s1
87; RV32I-FPELIM-NEXT:    addi sp, sp, 2032
88; RV32I-FPELIM-NEXT:    .cfi_def_cfa_offset 0
89; RV32I-FPELIM-NEXT:    ret
90;
91; RV32I-WITHFP-LABEL: test_emergency_spill_slot:
92; RV32I-WITHFP:       # %bb.0:
93; RV32I-WITHFP-NEXT:    addi sp, sp, -2032
94; RV32I-WITHFP-NEXT:    .cfi_def_cfa_offset 2032
95; RV32I-WITHFP-NEXT:    sw ra, 2028(sp)
96; RV32I-WITHFP-NEXT:    sw s0, 2024(sp)
97; RV32I-WITHFP-NEXT:    sw s1, 2020(sp)
98; RV32I-WITHFP-NEXT:    sw s2, 2016(sp)
99; RV32I-WITHFP-NEXT:    .cfi_offset ra, -4
100; RV32I-WITHFP-NEXT:    .cfi_offset s0, -8
101; RV32I-WITHFP-NEXT:    .cfi_offset s1, -12
102; RV32I-WITHFP-NEXT:    .cfi_offset s2, -16
103; RV32I-WITHFP-NEXT:    addi s0, sp, 2032
104; RV32I-WITHFP-NEXT:    .cfi_def_cfa s0, 0
105; RV32I-WITHFP-NEXT:    lui a1, 97
106; RV32I-WITHFP-NEXT:    addi a1, a1, 688
107; RV32I-WITHFP-NEXT:    sub sp, sp, a1
108; RV32I-WITHFP-NEXT:    .cfi_def_cfa_offset 400032
109; RV32I-WITHFP-NEXT:    lui a1, 78
110; RV32I-WITHFP-NEXT:    addi a1, a1, 512
111; RV32I-WITHFP-NEXT:    lui a2, 1048478
112; RV32I-WITHFP-NEXT:    addi a2, a2, 1388
113; RV32I-WITHFP-NEXT:    add a2, s0, a2
114; RV32I-WITHFP-NEXT:    mv a2, a2
115; RV32I-WITHFP-NEXT:    add a1, a2, a1
116; RV32I-WITHFP-NEXT:    #APP
117; RV32I-WITHFP-NEXT:    nop
118; RV32I-WITHFP-NEXT:    #NO_APP
119; RV32I-WITHFP-NEXT:    sw a0, 0(a1)
120; RV32I-WITHFP-NEXT:    #APP
121; RV32I-WITHFP-NEXT:    nop
122; RV32I-WITHFP-NEXT:    #NO_APP
123; RV32I-WITHFP-NEXT:    lui a0, 97
124; RV32I-WITHFP-NEXT:    addi a0, a0, 688
125; RV32I-WITHFP-NEXT:    add sp, sp, a0
126; RV32I-WITHFP-NEXT:    .cfi_def_cfa_offset 2032
127; RV32I-WITHFP-NEXT:    lw s2, 2016(sp)
128; RV32I-WITHFP-NEXT:    lw s1, 2020(sp)
129; RV32I-WITHFP-NEXT:    lw s0, 2024(sp)
130; RV32I-WITHFP-NEXT:    .cfi_def_cfa sp, 400032
131; RV32I-WITHFP-NEXT:    lw ra, 2028(sp)
132; RV32I-WITHFP-NEXT:    .cfi_restore ra
133; RV32I-WITHFP-NEXT:    .cfi_restore s0
134; RV32I-WITHFP-NEXT:    .cfi_restore s1
135; RV32I-WITHFP-NEXT:    .cfi_restore s2
136; RV32I-WITHFP-NEXT:    addi sp, sp, 2032
137; RV32I-WITHFP-NEXT:    .cfi_def_cfa_offset 0
138; RV32I-WITHFP-NEXT:    ret
139  %data = alloca [ 100000 x i32 ] , align 4
140  %ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %data, i32 0, i32 80000
141  %1 = tail call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "nop", "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r"()
142  %asmresult0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 0
143  %asmresult1 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 1
144  %asmresult2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 2
145  %asmresult3 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 3
146  %asmresult4 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 4
147  %asmresult5 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 5
148  %asmresult6 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 6
149  %asmresult7 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 7
150  %asmresult8 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 8
151  %asmresult9 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 9
152  %asmresult10 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 10
153  %asmresult11 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 11
154  %asmresult12 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 12
155  %asmresult13 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 13
156  %asmresult14 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 14
157  store volatile i32 %a, i32* %ptr
158  tail call void asm sideeffect "nop", "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r"(i32 %asmresult0, i32 %asmresult1, i32 %asmresult2, i32 %asmresult3, i32 %asmresult4, i32 %asmresult5, i32 %asmresult6, i32 %asmresult7, i32 %asmresult8, i32 %asmresult9, i32 %asmresult10, i32 %asmresult11, i32 %asmresult12, i32 %asmresult13, i32 %asmresult14)
159  ret void
160}
161