1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32I %s
4
5; TODO: the quality of the generated code is poor
6
7define void @test() nounwind {
8; RV32I-LABEL: test:
9; RV32I:       # %bb.0:
10; RV32I-NEXT:    lui a0, 74565
11; RV32I-NEXT:    addi a0, a0, 1680
12; RV32I-NEXT:    sub sp, sp, a0
13; RV32I-NEXT:    lui a0, 74565
14; RV32I-NEXT:    addi a0, a0, 1676
15; RV32I-NEXT:    add a0, sp, a0
16; RV32I-NEXT:    sw ra, 0(a0)
17; RV32I-NEXT:    lui a0, 74565
18; RV32I-NEXT:    addi a0, a0, 1672
19; RV32I-NEXT:    add a0, sp, a0
20; RV32I-NEXT:    sw s0, 0(a0)
21; RV32I-NEXT:    lui a0, 74565
22; RV32I-NEXT:    addi a0, a0, 1680
23; RV32I-NEXT:    add s0, sp, a0
24; RV32I-NEXT:    lui a0, 74565
25; RV32I-NEXT:    addi a0, a0, 1672
26; RV32I-NEXT:    add a0, sp, a0
27; RV32I-NEXT:    lw s0, 0(a0)
28; RV32I-NEXT:    lui a0, 74565
29; RV32I-NEXT:    addi a0, a0, 1676
30; RV32I-NEXT:    add a0, sp, a0
31; RV32I-NEXT:    lw ra, 0(a0)
32; RV32I-NEXT:    lui a0, 74565
33; RV32I-NEXT:    addi a0, a0, 1680
34; RV32I-NEXT:    add sp, sp, a0
35; RV32I-NEXT:    ret
36  %tmp = alloca [ 305419896 x i8 ] , align 4
37  ret void
38}
39
40; This test case artificially produces register pressure which should force
41; use of the emergency spill slot.
42
43define void @test_emergency_spill_slot(i32 %a) nounwind {
44; RV32I-LABEL: test_emergency_spill_slot:
45; RV32I:       # %bb.0:
46; RV32I-NEXT:    lui a1, 98
47; RV32I-NEXT:    addi a1, a1, -1376
48; RV32I-NEXT:    sub sp, sp, a1
49; RV32I-NEXT:    lui a1, 98
50; RV32I-NEXT:    addi a1, a1, -1380
51; RV32I-NEXT:    add a1, sp, a1
52; RV32I-NEXT:    sw ra, 0(a1)
53; RV32I-NEXT:    lui a1, 98
54; RV32I-NEXT:    addi a1, a1, -1384
55; RV32I-NEXT:    add a1, sp, a1
56; RV32I-NEXT:    sw s0, 0(a1)
57; RV32I-NEXT:    lui a1, 98
58; RV32I-NEXT:    addi a1, a1, -1388
59; RV32I-NEXT:    add a1, sp, a1
60; RV32I-NEXT:    sw s1, 0(a1)
61; RV32I-NEXT:    lui a1, 98
62; RV32I-NEXT:    addi a1, a1, -1392
63; RV32I-NEXT:    add a1, sp, a1
64; RV32I-NEXT:    sw s2, 0(a1)
65; RV32I-NEXT:    lui a1, 98
66; RV32I-NEXT:    addi a1, a1, -1376
67; RV32I-NEXT:    add s0, sp, a1
68; RV32I-NEXT:    lui a1, 78
69; RV32I-NEXT:    addi a1, a1, 512
70; RV32I-NEXT:    lui a2, 1048478
71; RV32I-NEXT:    addi a2, a2, 1388
72; RV32I-NEXT:    add a2, s0, a2
73; RV32I-NEXT:    mv a2, a2
74; RV32I-NEXT:    add a1, a2, a1
75; RV32I-NEXT:    #APP
76; RV32I-NEXT:    nop
77; RV32I-NEXT:    #NO_APP
78; RV32I-NEXT:    sw a0, 0(a1)
79; RV32I-NEXT:    #APP
80; RV32I-NEXT:    nop
81; RV32I-NEXT:    #NO_APP
82; RV32I-NEXT:    lui a0, 98
83; RV32I-NEXT:    addi a0, a0, -1392
84; RV32I-NEXT:    add a0, sp, a0
85; RV32I-NEXT:    lw s2, 0(a0)
86; RV32I-NEXT:    lui a0, 98
87; RV32I-NEXT:    addi a0, a0, -1388
88; RV32I-NEXT:    add a0, sp, a0
89; RV32I-NEXT:    lw s1, 0(a0)
90; RV32I-NEXT:    lui a0, 98
91; RV32I-NEXT:    addi a0, a0, -1384
92; RV32I-NEXT:    add a0, sp, a0
93; RV32I-NEXT:    lw s0, 0(a0)
94; RV32I-NEXT:    lui a0, 98
95; RV32I-NEXT:    addi a0, a0, -1380
96; RV32I-NEXT:    add a0, sp, a0
97; RV32I-NEXT:    lw ra, 0(a0)
98; RV32I-NEXT:    lui a0, 98
99; RV32I-NEXT:    addi a0, a0, -1376
100; RV32I-NEXT:    add sp, sp, a0
101; RV32I-NEXT:    ret
102  %data = alloca [ 100000 x i32 ] , align 4
103  %ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %data, i32 0, i32 80000
104  %1 = tail call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "nop", "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r"()
105  %asmresult0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 0
106  %asmresult1 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 1
107  %asmresult2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 2
108  %asmresult3 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 3
109  %asmresult4 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 4
110  %asmresult5 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 5
111  %asmresult6 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 6
112  %asmresult7 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 7
113  %asmresult8 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 8
114  %asmresult9 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 9
115  %asmresult10 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 10
116  %asmresult11 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 11
117  %asmresult12 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 12
118  %asmresult13 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 13
119  %asmresult14 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 14
120  store volatile i32 %a, i32* %ptr
121  tail call void asm sideeffect "nop", "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r"(i32 %asmresult0, i32 %asmresult1, i32 %asmresult2, i32 %asmresult3, i32 %asmresult4, i32 %asmresult5, i32 %asmresult6, i32 %asmresult7, i32 %asmresult8, i32 %asmresult9, i32 %asmresult10, i32 %asmresult11, i32 %asmresult12, i32 %asmresult13, i32 %asmresult14)
122  ret void
123}
124