1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32I %s
4
5@gi = external global i32
6
7define i32 @constraint_r(i32 %a) {
8; RV32I-LABEL: constraint_r:
9; RV32I:       # %bb.0:
10; RV32I-NEXT:    addi sp, sp, -16
11; RV32I-NEXT:    sw ra, 12(sp)
12; RV32I-NEXT:    sw s0, 8(sp)
13; RV32I-NEXT:    addi s0, sp, 16
14; RV32I-NEXT:    lui a1, %hi(gi)
15; RV32I-NEXT:    addi a1, a1, %lo(gi)
16; RV32I-NEXT:    lw a1, 0(a1)
17; RV32I-NEXT:    #APP
18; RV32I-NEXT:    add a0, a0, a1
19; RV32I-NEXT:    #NO_APP
20; RV32I-NEXT:    lw s0, 8(sp)
21; RV32I-NEXT:    lw ra, 12(sp)
22; RV32I-NEXT:    addi sp, sp, 16
23; RV32I-NEXT:    ret
24  %1 = load i32, i32* @gi
25  %2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1)
26  ret i32 %2
27}
28
29define i32 @constraint_i(i32 %a) {
30; RV32I-LABEL: constraint_i:
31; RV32I:       # %bb.0:
32; RV32I-NEXT:    addi sp, sp, -16
33; RV32I-NEXT:    sw ra, 12(sp)
34; RV32I-NEXT:    sw s0, 8(sp)
35; RV32I-NEXT:    addi s0, sp, 16
36; RV32I-NEXT:    #APP
37; RV32I-NEXT:    addi a0, a0, 113
38; RV32I-NEXT:    #NO_APP
39; RV32I-NEXT:    lw s0, 8(sp)
40; RV32I-NEXT:    lw ra, 12(sp)
41; RV32I-NEXT:    addi sp, sp, 16
42; RV32I-NEXT:    ret
43  %1 = load i32, i32* @gi
44  %2 = tail call i32 asm "addi $0, $1, $2", "=r,r,i"(i32 %a, i32 113)
45  ret i32 %2
46}
47
48define void @constraint_m(i32* %a) {
49; RV32I-LABEL: constraint_m:
50; RV32I:       # %bb.0:
51; RV32I-NEXT:    addi sp, sp, -16
52; RV32I-NEXT:    sw ra, 12(sp)
53; RV32I-NEXT:    sw s0, 8(sp)
54; RV32I-NEXT:    addi s0, sp, 16
55; RV32I-NEXT:    #APP
56; RV32I-NEXT:    #NO_APP
57; RV32I-NEXT:    lw s0, 8(sp)
58; RV32I-NEXT:    lw ra, 12(sp)
59; RV32I-NEXT:    addi sp, sp, 16
60; RV32I-NEXT:    ret
61  call void asm sideeffect "", "=*m"(i32* %a)
62  ret void
63}
64
65define i32 @constraint_m2(i32* %a) {
66; RV32I-LABEL: constraint_m2:
67; RV32I:       # %bb.0:
68; RV32I-NEXT:    addi sp, sp, -16
69; RV32I-NEXT:    sw ra, 12(sp)
70; RV32I-NEXT:    sw s0, 8(sp)
71; RV32I-NEXT:    addi s0, sp, 16
72; RV32I-NEXT:    #APP
73; RV32I-NEXT:    lw a0, 0(a0)
74; RV32I-NEXT:    #NO_APP
75; RV32I-NEXT:    lw s0, 8(sp)
76; RV32I-NEXT:    lw ra, 12(sp)
77; RV32I-NEXT:    addi sp, sp, 16
78; RV32I-NEXT:    ret
79  %1 = tail call i32 asm "lw $0, $1", "=r,*m"(i32* %a) nounwind
80  ret i32 %1
81}
82
83; TODO: expend tests for more complex constraints, out of range immediates etc
84