1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs < %s \
3; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IZFH %s
4; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs < %s \
5; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IZFH %s
6
7define signext i8 @test_floor_si8(half %x) {
8; RV32IZFH-LABEL: test_floor_si8:
9; RV32IZFH:       # %bb.0:
10; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rdn
11; RV32IZFH-NEXT:    ret
12;
13; RV64IZFH-LABEL: test_floor_si8:
14; RV64IZFH:       # %bb.0:
15; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rdn
16; RV64IZFH-NEXT:    ret
17  %a = call half @llvm.floor.f16(half %x)
18  %b = fptosi half %a to i8
19  ret i8 %b
20}
21
22define signext i16 @test_floor_si16(half %x) {
23; RV32IZFH-LABEL: test_floor_si16:
24; RV32IZFH:       # %bb.0:
25; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rdn
26; RV32IZFH-NEXT:    ret
27;
28; RV64IZFH-LABEL: test_floor_si16:
29; RV64IZFH:       # %bb.0:
30; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rdn
31; RV64IZFH-NEXT:    ret
32  %a = call half @llvm.floor.f16(half %x)
33  %b = fptosi half %a to i16
34  ret i16 %b
35}
36
37define signext i32 @test_floor_si32(half %x) {
38; RV32IZFH-LABEL: test_floor_si32:
39; RV32IZFH:       # %bb.0:
40; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rdn
41; RV32IZFH-NEXT:    ret
42;
43; RV64IZFH-LABEL: test_floor_si32:
44; RV64IZFH:       # %bb.0:
45; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rdn
46; RV64IZFH-NEXT:    ret
47  %a = call half @llvm.floor.f16(half %x)
48  %b = fptosi half %a to i32
49  ret i32 %b
50}
51
52define i64 @test_floor_si64(half %x) {
53; RV32IZFH-LABEL: test_floor_si64:
54; RV32IZFH:       # %bb.0:
55; RV32IZFH-NEXT:    addi sp, sp, -16
56; RV32IZFH-NEXT:    .cfi_def_cfa_offset 16
57; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
58; RV32IZFH-NEXT:    .cfi_offset ra, -4
59; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
60; RV32IZFH-NEXT:    call floorf@plt
61; RV32IZFH-NEXT:    fcvt.h.s fa0, fa0
62; RV32IZFH-NEXT:    call __fixhfdi@plt
63; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
64; RV32IZFH-NEXT:    addi sp, sp, 16
65; RV32IZFH-NEXT:    ret
66;
67; RV64IZFH-LABEL: test_floor_si64:
68; RV64IZFH:       # %bb.0:
69; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rdn
70; RV64IZFH-NEXT:    ret
71  %a = call half @llvm.floor.f16(half %x)
72  %b = fptosi half %a to i64
73  ret i64 %b
74}
75
76define zeroext i8 @test_floor_ui8(half %x) {
77; RV32IZFH-LABEL: test_floor_ui8:
78; RV32IZFH:       # %bb.0:
79; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rdn
80; RV32IZFH-NEXT:    ret
81;
82; RV64IZFH-LABEL: test_floor_ui8:
83; RV64IZFH:       # %bb.0:
84; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rdn
85; RV64IZFH-NEXT:    ret
86  %a = call half @llvm.floor.f16(half %x)
87  %b = fptoui half %a to i8
88  ret i8 %b
89}
90
91define zeroext i16 @test_floor_ui16(half %x) {
92; RV32IZFH-LABEL: test_floor_ui16:
93; RV32IZFH:       # %bb.0:
94; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rdn
95; RV32IZFH-NEXT:    ret
96;
97; RV64IZFH-LABEL: test_floor_ui16:
98; RV64IZFH:       # %bb.0:
99; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rdn
100; RV64IZFH-NEXT:    ret
101  %a = call half @llvm.floor.f16(half %x)
102  %b = fptoui half %a to i16
103  ret i16 %b
104}
105
106define signext i32 @test_floor_ui32(half %x) {
107; RV32IZFH-LABEL: test_floor_ui32:
108; RV32IZFH:       # %bb.0:
109; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rdn
110; RV32IZFH-NEXT:    ret
111;
112; RV64IZFH-LABEL: test_floor_ui32:
113; RV64IZFH:       # %bb.0:
114; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rdn
115; RV64IZFH-NEXT:    ret
116  %a = call half @llvm.floor.f16(half %x)
117  %b = fptoui half %a to i32
118  ret i32 %b
119}
120
121define i64 @test_floor_ui64(half %x) {
122; RV32IZFH-LABEL: test_floor_ui64:
123; RV32IZFH:       # %bb.0:
124; RV32IZFH-NEXT:    addi sp, sp, -16
125; RV32IZFH-NEXT:    .cfi_def_cfa_offset 16
126; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
127; RV32IZFH-NEXT:    .cfi_offset ra, -4
128; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
129; RV32IZFH-NEXT:    call floorf@plt
130; RV32IZFH-NEXT:    fcvt.h.s fa0, fa0
131; RV32IZFH-NEXT:    call __fixunshfdi@plt
132; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
133; RV32IZFH-NEXT:    addi sp, sp, 16
134; RV32IZFH-NEXT:    ret
135;
136; RV64IZFH-LABEL: test_floor_ui64:
137; RV64IZFH:       # %bb.0:
138; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rdn
139; RV64IZFH-NEXT:    ret
140  %a = call half @llvm.floor.f16(half %x)
141  %b = fptoui half %a to i64
142  ret i64 %b
143}
144
145define signext i8 @test_ceil_si8(half %x) {
146; RV32IZFH-LABEL: test_ceil_si8:
147; RV32IZFH:       # %bb.0:
148; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rup
149; RV32IZFH-NEXT:    ret
150;
151; RV64IZFH-LABEL: test_ceil_si8:
152; RV64IZFH:       # %bb.0:
153; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rup
154; RV64IZFH-NEXT:    ret
155  %a = call half @llvm.ceil.f16(half %x)
156  %b = fptosi half %a to i8
157  ret i8 %b
158}
159
160define signext i16 @test_ceil_si16(half %x) {
161; RV32IZFH-LABEL: test_ceil_si16:
162; RV32IZFH:       # %bb.0:
163; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rup
164; RV32IZFH-NEXT:    ret
165;
166; RV64IZFH-LABEL: test_ceil_si16:
167; RV64IZFH:       # %bb.0:
168; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rup
169; RV64IZFH-NEXT:    ret
170  %a = call half @llvm.ceil.f16(half %x)
171  %b = fptosi half %a to i16
172  ret i16 %b
173}
174
175define signext i32 @test_ceil_si32(half %x) {
176; RV32IZFH-LABEL: test_ceil_si32:
177; RV32IZFH:       # %bb.0:
178; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rup
179; RV32IZFH-NEXT:    ret
180;
181; RV64IZFH-LABEL: test_ceil_si32:
182; RV64IZFH:       # %bb.0:
183; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rup
184; RV64IZFH-NEXT:    ret
185  %a = call half @llvm.ceil.f16(half %x)
186  %b = fptosi half %a to i32
187  ret i32 %b
188}
189
190define i64 @test_ceil_si64(half %x) {
191; RV32IZFH-LABEL: test_ceil_si64:
192; RV32IZFH:       # %bb.0:
193; RV32IZFH-NEXT:    addi sp, sp, -16
194; RV32IZFH-NEXT:    .cfi_def_cfa_offset 16
195; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
196; RV32IZFH-NEXT:    .cfi_offset ra, -4
197; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
198; RV32IZFH-NEXT:    call ceilf@plt
199; RV32IZFH-NEXT:    fcvt.h.s fa0, fa0
200; RV32IZFH-NEXT:    call __fixhfdi@plt
201; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
202; RV32IZFH-NEXT:    addi sp, sp, 16
203; RV32IZFH-NEXT:    ret
204;
205; RV64IZFH-LABEL: test_ceil_si64:
206; RV64IZFH:       # %bb.0:
207; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rup
208; RV64IZFH-NEXT:    ret
209  %a = call half @llvm.ceil.f16(half %x)
210  %b = fptosi half %a to i64
211  ret i64 %b
212}
213
214define zeroext i8 @test_ceil_ui8(half %x) {
215; RV32IZFH-LABEL: test_ceil_ui8:
216; RV32IZFH:       # %bb.0:
217; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rup
218; RV32IZFH-NEXT:    ret
219;
220; RV64IZFH-LABEL: test_ceil_ui8:
221; RV64IZFH:       # %bb.0:
222; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rup
223; RV64IZFH-NEXT:    ret
224  %a = call half @llvm.ceil.f16(half %x)
225  %b = fptoui half %a to i8
226  ret i8 %b
227}
228
229define zeroext i16 @test_ceil_ui16(half %x) {
230; RV32IZFH-LABEL: test_ceil_ui16:
231; RV32IZFH:       # %bb.0:
232; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rup
233; RV32IZFH-NEXT:    ret
234;
235; RV64IZFH-LABEL: test_ceil_ui16:
236; RV64IZFH:       # %bb.0:
237; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rup
238; RV64IZFH-NEXT:    ret
239  %a = call half @llvm.ceil.f16(half %x)
240  %b = fptoui half %a to i16
241  ret i16 %b
242}
243
244define signext i32 @test_ceil_ui32(half %x) {
245; RV32IZFH-LABEL: test_ceil_ui32:
246; RV32IZFH:       # %bb.0:
247; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rup
248; RV32IZFH-NEXT:    ret
249;
250; RV64IZFH-LABEL: test_ceil_ui32:
251; RV64IZFH:       # %bb.0:
252; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rup
253; RV64IZFH-NEXT:    ret
254  %a = call half @llvm.ceil.f16(half %x)
255  %b = fptoui half %a to i32
256  ret i32 %b
257}
258
259define i64 @test_ceil_ui64(half %x) {
260; RV32IZFH-LABEL: test_ceil_ui64:
261; RV32IZFH:       # %bb.0:
262; RV32IZFH-NEXT:    addi sp, sp, -16
263; RV32IZFH-NEXT:    .cfi_def_cfa_offset 16
264; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
265; RV32IZFH-NEXT:    .cfi_offset ra, -4
266; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
267; RV32IZFH-NEXT:    call ceilf@plt
268; RV32IZFH-NEXT:    fcvt.h.s fa0, fa0
269; RV32IZFH-NEXT:    call __fixunshfdi@plt
270; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
271; RV32IZFH-NEXT:    addi sp, sp, 16
272; RV32IZFH-NEXT:    ret
273;
274; RV64IZFH-LABEL: test_ceil_ui64:
275; RV64IZFH:       # %bb.0:
276; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rup
277; RV64IZFH-NEXT:    ret
278  %a = call half @llvm.ceil.f16(half %x)
279  %b = fptoui half %a to i64
280  ret i64 %b
281}
282
283define signext i8 @test_trunc_si8(half %x) {
284; RV32IZFH-LABEL: test_trunc_si8:
285; RV32IZFH:       # %bb.0:
286; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
287; RV32IZFH-NEXT:    ret
288;
289; RV64IZFH-LABEL: test_trunc_si8:
290; RV64IZFH:       # %bb.0:
291; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
292; RV64IZFH-NEXT:    ret
293  %a = call half @llvm.trunc.f16(half %x)
294  %b = fptosi half %a to i8
295  ret i8 %b
296}
297
298define signext i16 @test_trunc_si16(half %x) {
299; RV32IZFH-LABEL: test_trunc_si16:
300; RV32IZFH:       # %bb.0:
301; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
302; RV32IZFH-NEXT:    ret
303;
304; RV64IZFH-LABEL: test_trunc_si16:
305; RV64IZFH:       # %bb.0:
306; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
307; RV64IZFH-NEXT:    ret
308  %a = call half @llvm.trunc.f16(half %x)
309  %b = fptosi half %a to i16
310  ret i16 %b
311}
312
313define signext i32 @test_trunc_si32(half %x) {
314; RV32IZFH-LABEL: test_trunc_si32:
315; RV32IZFH:       # %bb.0:
316; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
317; RV32IZFH-NEXT:    ret
318;
319; RV64IZFH-LABEL: test_trunc_si32:
320; RV64IZFH:       # %bb.0:
321; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
322; RV64IZFH-NEXT:    ret
323  %a = call half @llvm.trunc.f16(half %x)
324  %b = fptosi half %a to i32
325  ret i32 %b
326}
327
328define i64 @test_trunc_si64(half %x) {
329; RV32IZFH-LABEL: test_trunc_si64:
330; RV32IZFH:       # %bb.0:
331; RV32IZFH-NEXT:    addi sp, sp, -16
332; RV32IZFH-NEXT:    .cfi_def_cfa_offset 16
333; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
334; RV32IZFH-NEXT:    .cfi_offset ra, -4
335; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
336; RV32IZFH-NEXT:    call truncf@plt
337; RV32IZFH-NEXT:    fcvt.h.s fa0, fa0
338; RV32IZFH-NEXT:    call __fixhfdi@plt
339; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
340; RV32IZFH-NEXT:    addi sp, sp, 16
341; RV32IZFH-NEXT:    ret
342;
343; RV64IZFH-LABEL: test_trunc_si64:
344; RV64IZFH:       # %bb.0:
345; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
346; RV64IZFH-NEXT:    ret
347  %a = call half @llvm.trunc.f16(half %x)
348  %b = fptosi half %a to i64
349  ret i64 %b
350}
351
352define zeroext i8 @test_trunc_ui8(half %x) {
353; RV32IZFH-LABEL: test_trunc_ui8:
354; RV32IZFH:       # %bb.0:
355; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
356; RV32IZFH-NEXT:    ret
357;
358; RV64IZFH-LABEL: test_trunc_ui8:
359; RV64IZFH:       # %bb.0:
360; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
361; RV64IZFH-NEXT:    ret
362  %a = call half @llvm.trunc.f16(half %x)
363  %b = fptoui half %a to i8
364  ret i8 %b
365}
366
367define zeroext i16 @test_trunc_ui16(half %x) {
368; RV32IZFH-LABEL: test_trunc_ui16:
369; RV32IZFH:       # %bb.0:
370; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
371; RV32IZFH-NEXT:    ret
372;
373; RV64IZFH-LABEL: test_trunc_ui16:
374; RV64IZFH:       # %bb.0:
375; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
376; RV64IZFH-NEXT:    ret
377  %a = call half @llvm.trunc.f16(half %x)
378  %b = fptoui half %a to i16
379  ret i16 %b
380}
381
382define signext i32 @test_trunc_ui32(half %x) {
383; RV32IZFH-LABEL: test_trunc_ui32:
384; RV32IZFH:       # %bb.0:
385; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
386; RV32IZFH-NEXT:    ret
387;
388; RV64IZFH-LABEL: test_trunc_ui32:
389; RV64IZFH:       # %bb.0:
390; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
391; RV64IZFH-NEXT:    ret
392  %a = call half @llvm.trunc.f16(half %x)
393  %b = fptoui half %a to i32
394  ret i32 %b
395}
396
397define i64 @test_trunc_ui64(half %x) {
398; RV32IZFH-LABEL: test_trunc_ui64:
399; RV32IZFH:       # %bb.0:
400; RV32IZFH-NEXT:    addi sp, sp, -16
401; RV32IZFH-NEXT:    .cfi_def_cfa_offset 16
402; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
403; RV32IZFH-NEXT:    .cfi_offset ra, -4
404; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
405; RV32IZFH-NEXT:    call truncf@plt
406; RV32IZFH-NEXT:    fcvt.h.s fa0, fa0
407; RV32IZFH-NEXT:    call __fixunshfdi@plt
408; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
409; RV32IZFH-NEXT:    addi sp, sp, 16
410; RV32IZFH-NEXT:    ret
411;
412; RV64IZFH-LABEL: test_trunc_ui64:
413; RV64IZFH:       # %bb.0:
414; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
415; RV64IZFH-NEXT:    ret
416  %a = call half @llvm.trunc.f16(half %x)
417  %b = fptoui half %a to i64
418  ret i64 %b
419}
420
421define signext i8 @test_round_si8(half %x) {
422; RV32IZFH-LABEL: test_round_si8:
423; RV32IZFH:       # %bb.0:
424; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rmm
425; RV32IZFH-NEXT:    ret
426;
427; RV64IZFH-LABEL: test_round_si8:
428; RV64IZFH:       # %bb.0:
429; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rmm
430; RV64IZFH-NEXT:    ret
431  %a = call half @llvm.round.f16(half %x)
432  %b = fptosi half %a to i8
433  ret i8 %b
434}
435
436define signext i16 @test_round_si16(half %x) {
437; RV32IZFH-LABEL: test_round_si16:
438; RV32IZFH:       # %bb.0:
439; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rmm
440; RV32IZFH-NEXT:    ret
441;
442; RV64IZFH-LABEL: test_round_si16:
443; RV64IZFH:       # %bb.0:
444; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rmm
445; RV64IZFH-NEXT:    ret
446  %a = call half @llvm.round.f16(half %x)
447  %b = fptosi half %a to i16
448  ret i16 %b
449}
450
451define signext i32 @test_round_si32(half %x) {
452; RV32IZFH-LABEL: test_round_si32:
453; RV32IZFH:       # %bb.0:
454; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rmm
455; RV32IZFH-NEXT:    ret
456;
457; RV64IZFH-LABEL: test_round_si32:
458; RV64IZFH:       # %bb.0:
459; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rmm
460; RV64IZFH-NEXT:    ret
461  %a = call half @llvm.round.f16(half %x)
462  %b = fptosi half %a to i32
463  ret i32 %b
464}
465
466define i64 @test_round_si64(half %x) {
467; RV32IZFH-LABEL: test_round_si64:
468; RV32IZFH:       # %bb.0:
469; RV32IZFH-NEXT:    addi sp, sp, -16
470; RV32IZFH-NEXT:    .cfi_def_cfa_offset 16
471; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
472; RV32IZFH-NEXT:    .cfi_offset ra, -4
473; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
474; RV32IZFH-NEXT:    call roundf@plt
475; RV32IZFH-NEXT:    fcvt.h.s fa0, fa0
476; RV32IZFH-NEXT:    call __fixhfdi@plt
477; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
478; RV32IZFH-NEXT:    addi sp, sp, 16
479; RV32IZFH-NEXT:    ret
480;
481; RV64IZFH-LABEL: test_round_si64:
482; RV64IZFH:       # %bb.0:
483; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rmm
484; RV64IZFH-NEXT:    ret
485  %a = call half @llvm.round.f16(half %x)
486  %b = fptosi half %a to i64
487  ret i64 %b
488}
489
490define zeroext i8 @test_round_ui8(half %x) {
491; RV32IZFH-LABEL: test_round_ui8:
492; RV32IZFH:       # %bb.0:
493; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rmm
494; RV32IZFH-NEXT:    ret
495;
496; RV64IZFH-LABEL: test_round_ui8:
497; RV64IZFH:       # %bb.0:
498; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rmm
499; RV64IZFH-NEXT:    ret
500  %a = call half @llvm.round.f16(half %x)
501  %b = fptoui half %a to i8
502  ret i8 %b
503}
504
505define zeroext i16 @test_round_ui16(half %x) {
506; RV32IZFH-LABEL: test_round_ui16:
507; RV32IZFH:       # %bb.0:
508; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rmm
509; RV32IZFH-NEXT:    ret
510;
511; RV64IZFH-LABEL: test_round_ui16:
512; RV64IZFH:       # %bb.0:
513; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rmm
514; RV64IZFH-NEXT:    ret
515  %a = call half @llvm.round.f16(half %x)
516  %b = fptoui half %a to i16
517  ret i16 %b
518}
519
520define signext i32 @test_round_ui32(half %x) {
521; RV32IZFH-LABEL: test_round_ui32:
522; RV32IZFH:       # %bb.0:
523; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rmm
524; RV32IZFH-NEXT:    ret
525;
526; RV64IZFH-LABEL: test_round_ui32:
527; RV64IZFH:       # %bb.0:
528; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rmm
529; RV64IZFH-NEXT:    ret
530  %a = call half @llvm.round.f16(half %x)
531  %b = fptoui half %a to i32
532  ret i32 %b
533}
534
535define i64 @test_round_ui64(half %x) {
536; RV32IZFH-LABEL: test_round_ui64:
537; RV32IZFH:       # %bb.0:
538; RV32IZFH-NEXT:    addi sp, sp, -16
539; RV32IZFH-NEXT:    .cfi_def_cfa_offset 16
540; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
541; RV32IZFH-NEXT:    .cfi_offset ra, -4
542; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
543; RV32IZFH-NEXT:    call roundf@plt
544; RV32IZFH-NEXT:    fcvt.h.s fa0, fa0
545; RV32IZFH-NEXT:    call __fixunshfdi@plt
546; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
547; RV32IZFH-NEXT:    addi sp, sp, 16
548; RV32IZFH-NEXT:    ret
549;
550; RV64IZFH-LABEL: test_round_ui64:
551; RV64IZFH:       # %bb.0:
552; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rmm
553; RV64IZFH-NEXT:    ret
554  %a = call half @llvm.round.f16(half %x)
555  %b = fptoui half %a to i64
556  ret i64 %b
557}
558
559define signext i8 @test_roundeven_si8(half %x) {
560; RV32IZFH-LABEL: test_roundeven_si8:
561; RV32IZFH:       # %bb.0:
562; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rne
563; RV32IZFH-NEXT:    ret
564;
565; RV64IZFH-LABEL: test_roundeven_si8:
566; RV64IZFH:       # %bb.0:
567; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rne
568; RV64IZFH-NEXT:    ret
569  %a = call half @llvm.roundeven.f16(half %x)
570  %b = fptosi half %a to i8
571  ret i8 %b
572}
573
574define signext i16 @test_roundeven_si16(half %x) {
575; RV32IZFH-LABEL: test_roundeven_si16:
576; RV32IZFH:       # %bb.0:
577; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rne
578; RV32IZFH-NEXT:    ret
579;
580; RV64IZFH-LABEL: test_roundeven_si16:
581; RV64IZFH:       # %bb.0:
582; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rne
583; RV64IZFH-NEXT:    ret
584  %a = call half @llvm.roundeven.f16(half %x)
585  %b = fptosi half %a to i16
586  ret i16 %b
587}
588
589define signext i32 @test_roundeven_si32(half %x) {
590; RV32IZFH-LABEL: test_roundeven_si32:
591; RV32IZFH:       # %bb.0:
592; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rne
593; RV32IZFH-NEXT:    ret
594;
595; RV64IZFH-LABEL: test_roundeven_si32:
596; RV64IZFH:       # %bb.0:
597; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rne
598; RV64IZFH-NEXT:    ret
599  %a = call half @llvm.roundeven.f16(half %x)
600  %b = fptosi half %a to i32
601  ret i32 %b
602}
603
604define i64 @test_roundeven_si64(half %x) {
605; RV32IZFH-LABEL: test_roundeven_si64:
606; RV32IZFH:       # %bb.0:
607; RV32IZFH-NEXT:    addi sp, sp, -16
608; RV32IZFH-NEXT:    .cfi_def_cfa_offset 16
609; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
610; RV32IZFH-NEXT:    .cfi_offset ra, -4
611; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
612; RV32IZFH-NEXT:    call roundevenf@plt
613; RV32IZFH-NEXT:    fcvt.h.s fa0, fa0
614; RV32IZFH-NEXT:    call __fixhfdi@plt
615; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
616; RV32IZFH-NEXT:    addi sp, sp, 16
617; RV32IZFH-NEXT:    ret
618;
619; RV64IZFH-LABEL: test_roundeven_si64:
620; RV64IZFH:       # %bb.0:
621; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rne
622; RV64IZFH-NEXT:    ret
623  %a = call half @llvm.roundeven.f16(half %x)
624  %b = fptosi half %a to i64
625  ret i64 %b
626}
627
628define zeroext i8 @test_roundeven_ui8(half %x) {
629; RV32IZFH-LABEL: test_roundeven_ui8:
630; RV32IZFH:       # %bb.0:
631; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rne
632; RV32IZFH-NEXT:    ret
633;
634; RV64IZFH-LABEL: test_roundeven_ui8:
635; RV64IZFH:       # %bb.0:
636; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rne
637; RV64IZFH-NEXT:    ret
638  %a = call half @llvm.roundeven.f16(half %x)
639  %b = fptoui half %a to i8
640  ret i8 %b
641}
642
643define zeroext i16 @test_roundeven_ui16(half %x) {
644; RV32IZFH-LABEL: test_roundeven_ui16:
645; RV32IZFH:       # %bb.0:
646; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rne
647; RV32IZFH-NEXT:    ret
648;
649; RV64IZFH-LABEL: test_roundeven_ui16:
650; RV64IZFH:       # %bb.0:
651; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rne
652; RV64IZFH-NEXT:    ret
653  %a = call half @llvm.roundeven.f16(half %x)
654  %b = fptoui half %a to i16
655  ret i16 %b
656}
657
658define signext i32 @test_roundeven_ui32(half %x) {
659; RV32IZFH-LABEL: test_roundeven_ui32:
660; RV32IZFH:       # %bb.0:
661; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rne
662; RV32IZFH-NEXT:    ret
663;
664; RV64IZFH-LABEL: test_roundeven_ui32:
665; RV64IZFH:       # %bb.0:
666; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rne
667; RV64IZFH-NEXT:    ret
668  %a = call half @llvm.roundeven.f16(half %x)
669  %b = fptoui half %a to i32
670  ret i32 %b
671}
672
673define i64 @test_roundeven_ui64(half %x) {
674; RV32IZFH-LABEL: test_roundeven_ui64:
675; RV32IZFH:       # %bb.0:
676; RV32IZFH-NEXT:    addi sp, sp, -16
677; RV32IZFH-NEXT:    .cfi_def_cfa_offset 16
678; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
679; RV32IZFH-NEXT:    .cfi_offset ra, -4
680; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
681; RV32IZFH-NEXT:    call roundevenf@plt
682; RV32IZFH-NEXT:    fcvt.h.s fa0, fa0
683; RV32IZFH-NEXT:    call __fixunshfdi@plt
684; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
685; RV32IZFH-NEXT:    addi sp, sp, 16
686; RV32IZFH-NEXT:    ret
687;
688; RV64IZFH-LABEL: test_roundeven_ui64:
689; RV64IZFH:       # %bb.0:
690; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rne
691; RV64IZFH-NEXT:    ret
692  %a = call half @llvm.roundeven.f16(half %x)
693  %b = fptoui half %a to i64
694  ret i64 %b
695}
696
697declare half @llvm.floor.f16(half)
698declare half @llvm.ceil.f16(half)
699declare half @llvm.trunc.f16(half)
700declare half @llvm.round.f16(half)
701declare half @llvm.roundeven.f16(half)
702