1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
3; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
4; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
5; RUN:   -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
6
7define half @flh(half *%a) nounwind {
8; CHECKIZFH-LABEL: flh:
9; CHECKIZFH:       # %bb.0:
10; CHECKIZFH-NEXT:    flh ft0, 0(a0)
11; CHECKIZFH-NEXT:    flh ft1, 6(a0)
12; CHECKIZFH-NEXT:    fadd.h fa0, ft0, ft1
13; CHECKIZFH-NEXT:    ret
14  %1 = load half, half* %a
15  %2 = getelementptr half, half* %a, i32 3
16  %3 = load half, half* %2
17; Use both loaded values in an FP op to ensure an flh is used, even for the
18; soft half ABI
19  %4 = fadd half %1, %3
20  ret half %4
21}
22
23define dso_local void @fsh(half *%a, half %b, half %c) nounwind {
24; Use %b and %c in an FP op to ensure half precision floating point registers
25; are used, even for the soft half ABI
26; CHECKIZFH-LABEL: fsh:
27; CHECKIZFH:       # %bb.0:
28; CHECKIZFH-NEXT:    fadd.h ft0, fa0, fa1
29; CHECKIZFH-NEXT:    fsh ft0, 0(a0)
30; CHECKIZFH-NEXT:    fsh ft0, 16(a0)
31; CHECKIZFH-NEXT:    ret
32  %1 = fadd half %b, %c
33  store half %1, half* %a
34  %2 = getelementptr half, half* %a, i32 8
35  store half %1, half* %2
36  ret void
37}
38
39; Check load and store to a global
40@G = dso_local global half 0.0
41
42define half @flh_fsh_global(half %a, half %b) nounwind {
43; Use %a and %b in an FP op to ensure half precision floating point registers
44; are used, even for the soft half ABI
45; CHECKIZFH-LABEL: flh_fsh_global:
46; CHECKIZFH:       # %bb.0:
47; CHECKIZFH-NEXT:    fadd.h fa0, fa0, fa1
48; CHECKIZFH-NEXT:    lui a0, %hi(G)
49; CHECKIZFH-NEXT:    flh ft0, %lo(G)(a0)
50; CHECKIZFH-NEXT:    addi a1, a0, %lo(G)
51; CHECKIZFH-NEXT:    fsh fa0, %lo(G)(a0)
52; CHECKIZFH-NEXT:    flh ft0, 18(a1)
53; CHECKIZFH-NEXT:    fsh fa0, 18(a1)
54; CHECKIZFH-NEXT:    ret
55  %1 = fadd half %a, %b
56  %2 = load volatile half, half* @G
57  store half %1, half* @G
58  %3 = getelementptr half, half* @G, i32 9
59  %4 = load volatile half, half* %3
60  store half %1, half* %3
61  ret half %1
62}
63
64; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
65define half @flh_fsh_constant(half %a) nounwind {
66; RV32IZFH-LABEL: flh_fsh_constant:
67; RV32IZFH:       # %bb.0:
68; RV32IZFH-NEXT:    lui a0, 912092
69; RV32IZFH-NEXT:    flh ft0, -273(a0)
70; RV32IZFH-NEXT:    fadd.h fa0, fa0, ft0
71; RV32IZFH-NEXT:    fsh fa0, -273(a0)
72; RV32IZFH-NEXT:    ret
73;
74; RV64IZFH-LABEL: flh_fsh_constant:
75; RV64IZFH:       # %bb.0:
76; RV64IZFH-NEXT:    lui a0, 228023
77; RV64IZFH-NEXT:    slli a0, a0, 2
78; RV64IZFH-NEXT:    flh ft0, -273(a0)
79; RV64IZFH-NEXT:    fadd.h fa0, fa0, ft0
80; RV64IZFH-NEXT:    fsh fa0, -273(a0)
81; RV64IZFH-NEXT:    ret
82  %1 = inttoptr i32 3735928559 to half*
83  %2 = load volatile half, half* %1
84  %3 = fadd half %a, %2
85  store half %3, half* %1
86  ret half %3
87}
88
89declare void @notdead(i8*)
90
91define half @flh_stack(half %a) nounwind {
92; RV32IZFH-LABEL: flh_stack:
93; RV32IZFH:       # %bb.0:
94; RV32IZFH-NEXT:    addi sp, sp, -16
95; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
96; RV32IZFH-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
97; RV32IZFH-NEXT:    fmv.h fs0, fa0
98; RV32IZFH-NEXT:    addi a0, sp, 4
99; RV32IZFH-NEXT:    call notdead@plt
100; RV32IZFH-NEXT:    flh ft0, 4(sp)
101; RV32IZFH-NEXT:    fadd.h fa0, ft0, fs0
102; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
103; RV32IZFH-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
104; RV32IZFH-NEXT:    addi sp, sp, 16
105; RV32IZFH-NEXT:    ret
106;
107; RV64IZFH-LABEL: flh_stack:
108; RV64IZFH:       # %bb.0:
109; RV64IZFH-NEXT:    addi sp, sp, -16
110; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
111; RV64IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
112; RV64IZFH-NEXT:    fmv.h fs0, fa0
113; RV64IZFH-NEXT:    mv a0, sp
114; RV64IZFH-NEXT:    call notdead@plt
115; RV64IZFH-NEXT:    flh ft0, 0(sp)
116; RV64IZFH-NEXT:    fadd.h fa0, ft0, fs0
117; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
118; RV64IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
119; RV64IZFH-NEXT:    addi sp, sp, 16
120; RV64IZFH-NEXT:    ret
121  %1 = alloca half, align 4
122  %2 = bitcast half* %1 to i8*
123  call void @notdead(i8* %2)
124  %3 = load half, half* %1
125  %4 = fadd half %3, %a ; force load in to FPR16
126  ret half %4
127}
128
129define dso_local void @fsh_stack(half %a, half %b) nounwind {
130; RV32IZFH-LABEL: fsh_stack:
131; RV32IZFH:       # %bb.0:
132; RV32IZFH-NEXT:    addi sp, sp, -16
133; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
134; RV32IZFH-NEXT:    fadd.h ft0, fa0, fa1
135; RV32IZFH-NEXT:    fsh ft0, 8(sp)
136; RV32IZFH-NEXT:    addi a0, sp, 8
137; RV32IZFH-NEXT:    call notdead@plt
138; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
139; RV32IZFH-NEXT:    addi sp, sp, 16
140; RV32IZFH-NEXT:    ret
141;
142; RV64IZFH-LABEL: fsh_stack:
143; RV64IZFH:       # %bb.0:
144; RV64IZFH-NEXT:    addi sp, sp, -16
145; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
146; RV64IZFH-NEXT:    fadd.h ft0, fa0, fa1
147; RV64IZFH-NEXT:    fsh ft0, 4(sp)
148; RV64IZFH-NEXT:    addi a0, sp, 4
149; RV64IZFH-NEXT:    call notdead@plt
150; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
151; RV64IZFH-NEXT:    addi sp, sp, 16
152; RV64IZFH-NEXT:    ret
153  %1 = fadd half %a, %b ; force store from FPR16
154  %2 = alloca half, align 4
155  store half %1, half* %2
156  %3 = bitcast half* %2 to i8*
157  call void @notdead(i8* %3)
158  ret void
159}
160