1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
3; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
4; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
5; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
6
7; TODO: constant pool shouldn't be necessary for RV32IZfh and RV64IZfh
8define half @half_imm() nounwind {
9; RV32IZFH-LABEL: half_imm:
10; RV32IZFH:       # %bb.0:
11; RV32IZFH-NEXT:    lui a0, %hi(.LCPI0_0)
12; RV32IZFH-NEXT:    flh fa0, %lo(.LCPI0_0)(a0)
13; RV32IZFH-NEXT:    ret
14;
15; RV64IZFH-LABEL: half_imm:
16; RV64IZFH:       # %bb.0:
17; RV64IZFH-NEXT:    lui a0, %hi(.LCPI0_0)
18; RV64IZFH-NEXT:    flh fa0, %lo(.LCPI0_0)(a0)
19; RV64IZFH-NEXT:    ret
20  ret half 3.0
21}
22
23define half @half_imm_op(half %a) nounwind {
24; RV32IZFH-LABEL: half_imm_op:
25; RV32IZFH:       # %bb.0:
26; RV32IZFH-NEXT:    lui a0, %hi(.LCPI1_0)
27; RV32IZFH-NEXT:    flh ft0, %lo(.LCPI1_0)(a0)
28; RV32IZFH-NEXT:    fadd.h fa0, fa0, ft0
29; RV32IZFH-NEXT:    ret
30;
31; RV64IZFH-LABEL: half_imm_op:
32; RV64IZFH:       # %bb.0:
33; RV64IZFH-NEXT:    lui a0, %hi(.LCPI1_0)
34; RV64IZFH-NEXT:    flh ft0, %lo(.LCPI1_0)(a0)
35; RV64IZFH-NEXT:    fadd.h fa0, fa0, ft0
36; RV64IZFH-NEXT:    ret
37  %1 = fadd half %a, 1.0
38  ret half %1
39}
40