1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32I %s
4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV64I %s
6
7declare void @notdead(i8*)
8declare i8* @llvm.frameaddress(i32)
9declare i8* @llvm.returnaddress(i32)
10
11define i8* @test_frameaddress_0() nounwind {
12; RV32I-LABEL: test_frameaddress_0:
13; RV32I:       # %bb.0:
14; RV32I-NEXT:    addi sp, sp, -16
15; RV32I-NEXT:    sw ra, 12(sp)
16; RV32I-NEXT:    sw s0, 8(sp)
17; RV32I-NEXT:    addi s0, sp, 16
18; RV32I-NEXT:    mv a0, s0
19; RV32I-NEXT:    lw s0, 8(sp)
20; RV32I-NEXT:    lw ra, 12(sp)
21; RV32I-NEXT:    addi sp, sp, 16
22; RV32I-NEXT:    ret
23;
24; RV64I-LABEL: test_frameaddress_0:
25; RV64I:       # %bb.0:
26; RV64I-NEXT:    addi sp, sp, -16
27; RV64I-NEXT:    sd ra, 8(sp)
28; RV64I-NEXT:    sd s0, 0(sp)
29; RV64I-NEXT:    addi s0, sp, 16
30; RV64I-NEXT:    mv a0, s0
31; RV64I-NEXT:    ld s0, 0(sp)
32; RV64I-NEXT:    ld ra, 8(sp)
33; RV64I-NEXT:    addi sp, sp, 16
34; RV64I-NEXT:    ret
35  %1 = call i8* @llvm.frameaddress(i32 0)
36  ret i8* %1
37}
38
39define i8* @test_frameaddress_2() nounwind {
40; RV32I-LABEL: test_frameaddress_2:
41; RV32I:       # %bb.0:
42; RV32I-NEXT:    addi sp, sp, -16
43; RV32I-NEXT:    sw ra, 12(sp)
44; RV32I-NEXT:    sw s0, 8(sp)
45; RV32I-NEXT:    addi s0, sp, 16
46; RV32I-NEXT:    lw a0, -8(s0)
47; RV32I-NEXT:    lw a0, -8(a0)
48; RV32I-NEXT:    lw s0, 8(sp)
49; RV32I-NEXT:    lw ra, 12(sp)
50; RV32I-NEXT:    addi sp, sp, 16
51; RV32I-NEXT:    ret
52;
53; RV64I-LABEL: test_frameaddress_2:
54; RV64I:       # %bb.0:
55; RV64I-NEXT:    addi sp, sp, -16
56; RV64I-NEXT:    sd ra, 8(sp)
57; RV64I-NEXT:    sd s0, 0(sp)
58; RV64I-NEXT:    addi s0, sp, 16
59; RV64I-NEXT:    ld a0, -16(s0)
60; RV64I-NEXT:    ld a0, -16(a0)
61; RV64I-NEXT:    ld s0, 0(sp)
62; RV64I-NEXT:    ld ra, 8(sp)
63; RV64I-NEXT:    addi sp, sp, 16
64; RV64I-NEXT:    ret
65  %1 = call i8* @llvm.frameaddress(i32 2)
66  ret i8* %1
67}
68
69define i8* @test_frameaddress_3_alloca() nounwind {
70; RV32I-LABEL: test_frameaddress_3_alloca:
71; RV32I:       # %bb.0:
72; RV32I-NEXT:    addi sp, sp, -112
73; RV32I-NEXT:    sw ra, 108(sp)
74; RV32I-NEXT:    sw s0, 104(sp)
75; RV32I-NEXT:    addi s0, sp, 112
76; RV32I-NEXT:    addi a0, s0, -108
77; RV32I-NEXT:    call notdead
78; RV32I-NEXT:    lw a0, -8(s0)
79; RV32I-NEXT:    lw a0, -8(a0)
80; RV32I-NEXT:    lw a0, -8(a0)
81; RV32I-NEXT:    lw s0, 104(sp)
82; RV32I-NEXT:    lw ra, 108(sp)
83; RV32I-NEXT:    addi sp, sp, 112
84; RV32I-NEXT:    ret
85;
86; RV64I-LABEL: test_frameaddress_3_alloca:
87; RV64I:       # %bb.0:
88; RV64I-NEXT:    addi sp, sp, -128
89; RV64I-NEXT:    sd ra, 120(sp)
90; RV64I-NEXT:    sd s0, 112(sp)
91; RV64I-NEXT:    addi s0, sp, 128
92; RV64I-NEXT:    addi a0, s0, -116
93; RV64I-NEXT:    call notdead
94; RV64I-NEXT:    ld a0, -16(s0)
95; RV64I-NEXT:    ld a0, -16(a0)
96; RV64I-NEXT:    ld a0, -16(a0)
97; RV64I-NEXT:    ld s0, 112(sp)
98; RV64I-NEXT:    ld ra, 120(sp)
99; RV64I-NEXT:    addi sp, sp, 128
100; RV64I-NEXT:    ret
101  %1 = alloca [100 x i8]
102  %2 = bitcast [100 x i8]* %1 to i8*
103  call void @notdead(i8* %2)
104  %3 = call i8* @llvm.frameaddress(i32 3)
105  ret i8* %3
106}
107
108define i8* @test_returnaddress_0() nounwind {
109; RV32I-LABEL: test_returnaddress_0:
110; RV32I:       # %bb.0:
111; RV32I-NEXT:    mv a0, ra
112; RV32I-NEXT:    ret
113;
114; RV64I-LABEL: test_returnaddress_0:
115; RV64I:       # %bb.0:
116; RV64I-NEXT:    mv a0, ra
117; RV64I-NEXT:    ret
118  %1 = call i8* @llvm.returnaddress(i32 0)
119  ret i8* %1
120}
121
122define i8* @test_returnaddress_2() nounwind {
123; RV32I-LABEL: test_returnaddress_2:
124; RV32I:       # %bb.0:
125; RV32I-NEXT:    addi sp, sp, -16
126; RV32I-NEXT:    sw ra, 12(sp)
127; RV32I-NEXT:    sw s0, 8(sp)
128; RV32I-NEXT:    addi s0, sp, 16
129; RV32I-NEXT:    lw a0, -8(s0)
130; RV32I-NEXT:    lw a0, -8(a0)
131; RV32I-NEXT:    lw a0, -4(a0)
132; RV32I-NEXT:    lw s0, 8(sp)
133; RV32I-NEXT:    lw ra, 12(sp)
134; RV32I-NEXT:    addi sp, sp, 16
135; RV32I-NEXT:    ret
136;
137; RV64I-LABEL: test_returnaddress_2:
138; RV64I:       # %bb.0:
139; RV64I-NEXT:    addi sp, sp, -16
140; RV64I-NEXT:    sd ra, 8(sp)
141; RV64I-NEXT:    sd s0, 0(sp)
142; RV64I-NEXT:    addi s0, sp, 16
143; RV64I-NEXT:    ld a0, -16(s0)
144; RV64I-NEXT:    ld a0, -16(a0)
145; RV64I-NEXT:    ld a0, -8(a0)
146; RV64I-NEXT:    ld s0, 0(sp)
147; RV64I-NEXT:    ld ra, 8(sp)
148; RV64I-NEXT:    addi sp, sp, 16
149; RV64I-NEXT:    ret
150  %1 = call i8* @llvm.returnaddress(i32 2)
151  ret i8* %1
152}
153