1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f \
3; RUN:   -verify-machineinstrs -target-abi=ilp32f \
4; RUN:   | FileCheck -check-prefix=RV32IF %s
5; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
6; RUN:   -verify-machineinstrs -target-abi=ilp32f \
7; RUN:   | FileCheck -check-prefix=RV32IF %s
8; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f \
9; RUN:   -verify-machineinstrs -target-abi=lp64f \
10; RUN:   | FileCheck -check-prefix=RV64IF %s
11; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
12; RUN:   -verify-machineinstrs -target-abi=lp64d \
13; RUN:   | FileCheck -check-prefix=RV64IF %s
14; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
15; RUN:   -verify-machineinstrs | FileCheck -check-prefix=RV32I %s
16; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
17; RUN:   -verify-machineinstrs | FileCheck -check-prefix=RV64I %s
18
19declare float @llvm.sqrt.f32(float)
20
21define float @sqrt_f32(float %a) nounwind {
22; RV32IF-LABEL: sqrt_f32:
23; RV32IF:       # %bb.0:
24; RV32IF-NEXT:    fsqrt.s fa0, fa0
25; RV32IF-NEXT:    ret
26;
27; RV64IF-LABEL: sqrt_f32:
28; RV64IF:       # %bb.0:
29; RV64IF-NEXT:    fsqrt.s fa0, fa0
30; RV64IF-NEXT:    ret
31;
32; RV32I-LABEL: sqrt_f32:
33; RV32I:       # %bb.0:
34; RV32I-NEXT:    addi sp, sp, -16
35; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
36; RV32I-NEXT:    call sqrtf@plt
37; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
38; RV32I-NEXT:    addi sp, sp, 16
39; RV32I-NEXT:    ret
40;
41; RV64I-LABEL: sqrt_f32:
42; RV64I:       # %bb.0:
43; RV64I-NEXT:    addi sp, sp, -16
44; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
45; RV64I-NEXT:    call sqrtf@plt
46; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
47; RV64I-NEXT:    addi sp, sp, 16
48; RV64I-NEXT:    ret
49  %1 = call float @llvm.sqrt.f32(float %a)
50  ret float %1
51}
52
53declare float @llvm.powi.f32.i32(float, i32)
54
55define float @powi_f32(float %a, i32 %b) nounwind {
56; RV32IF-LABEL: powi_f32:
57; RV32IF:       # %bb.0:
58; RV32IF-NEXT:    addi sp, sp, -16
59; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
60; RV32IF-NEXT:    call __powisf2@plt
61; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
62; RV32IF-NEXT:    addi sp, sp, 16
63; RV32IF-NEXT:    ret
64;
65; RV64IF-LABEL: powi_f32:
66; RV64IF:       # %bb.0:
67; RV64IF-NEXT:    addi sp, sp, -16
68; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
69; RV64IF-NEXT:    sext.w a0, a0
70; RV64IF-NEXT:    call __powisf2@plt
71; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
72; RV64IF-NEXT:    addi sp, sp, 16
73; RV64IF-NEXT:    ret
74;
75; RV32I-LABEL: powi_f32:
76; RV32I:       # %bb.0:
77; RV32I-NEXT:    addi sp, sp, -16
78; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
79; RV32I-NEXT:    call __powisf2@plt
80; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
81; RV32I-NEXT:    addi sp, sp, 16
82; RV32I-NEXT:    ret
83;
84; RV64I-LABEL: powi_f32:
85; RV64I:       # %bb.0:
86; RV64I-NEXT:    addi sp, sp, -16
87; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
88; RV64I-NEXT:    sext.w a1, a1
89; RV64I-NEXT:    call __powisf2@plt
90; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
91; RV64I-NEXT:    addi sp, sp, 16
92; RV64I-NEXT:    ret
93  %1 = call float @llvm.powi.f32.i32(float %a, i32 %b)
94  ret float %1
95}
96
97declare float @llvm.sin.f32(float)
98
99define float @sin_f32(float %a) nounwind {
100; RV32IF-LABEL: sin_f32:
101; RV32IF:       # %bb.0:
102; RV32IF-NEXT:    addi sp, sp, -16
103; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
104; RV32IF-NEXT:    call sinf@plt
105; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
106; RV32IF-NEXT:    addi sp, sp, 16
107; RV32IF-NEXT:    ret
108;
109; RV64IF-LABEL: sin_f32:
110; RV64IF:       # %bb.0:
111; RV64IF-NEXT:    addi sp, sp, -16
112; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
113; RV64IF-NEXT:    call sinf@plt
114; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
115; RV64IF-NEXT:    addi sp, sp, 16
116; RV64IF-NEXT:    ret
117;
118; RV32I-LABEL: sin_f32:
119; RV32I:       # %bb.0:
120; RV32I-NEXT:    addi sp, sp, -16
121; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
122; RV32I-NEXT:    call sinf@plt
123; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
124; RV32I-NEXT:    addi sp, sp, 16
125; RV32I-NEXT:    ret
126;
127; RV64I-LABEL: sin_f32:
128; RV64I:       # %bb.0:
129; RV64I-NEXT:    addi sp, sp, -16
130; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
131; RV64I-NEXT:    call sinf@plt
132; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
133; RV64I-NEXT:    addi sp, sp, 16
134; RV64I-NEXT:    ret
135  %1 = call float @llvm.sin.f32(float %a)
136  ret float %1
137}
138
139declare float @llvm.cos.f32(float)
140
141define float @cos_f32(float %a) nounwind {
142; RV32IF-LABEL: cos_f32:
143; RV32IF:       # %bb.0:
144; RV32IF-NEXT:    addi sp, sp, -16
145; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
146; RV32IF-NEXT:    call cosf@plt
147; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
148; RV32IF-NEXT:    addi sp, sp, 16
149; RV32IF-NEXT:    ret
150;
151; RV64IF-LABEL: cos_f32:
152; RV64IF:       # %bb.0:
153; RV64IF-NEXT:    addi sp, sp, -16
154; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
155; RV64IF-NEXT:    call cosf@plt
156; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
157; RV64IF-NEXT:    addi sp, sp, 16
158; RV64IF-NEXT:    ret
159;
160; RV32I-LABEL: cos_f32:
161; RV32I:       # %bb.0:
162; RV32I-NEXT:    addi sp, sp, -16
163; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
164; RV32I-NEXT:    call cosf@plt
165; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
166; RV32I-NEXT:    addi sp, sp, 16
167; RV32I-NEXT:    ret
168;
169; RV64I-LABEL: cos_f32:
170; RV64I:       # %bb.0:
171; RV64I-NEXT:    addi sp, sp, -16
172; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
173; RV64I-NEXT:    call cosf@plt
174; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
175; RV64I-NEXT:    addi sp, sp, 16
176; RV64I-NEXT:    ret
177  %1 = call float @llvm.cos.f32(float %a)
178  ret float %1
179}
180
181; The sin+cos combination results in an FSINCOS SelectionDAG node.
182define float @sincos_f32(float %a) nounwind {
183; RV32IF-LABEL: sincos_f32:
184; RV32IF:       # %bb.0:
185; RV32IF-NEXT:    addi sp, sp, -16
186; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
187; RV32IF-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
188; RV32IF-NEXT:    fsw fs1, 4(sp) # 4-byte Folded Spill
189; RV32IF-NEXT:    fmv.s fs0, fa0
190; RV32IF-NEXT:    call sinf@plt
191; RV32IF-NEXT:    fmv.s fs1, fa0
192; RV32IF-NEXT:    fmv.s fa0, fs0
193; RV32IF-NEXT:    call cosf@plt
194; RV32IF-NEXT:    fadd.s fa0, fs1, fa0
195; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
196; RV32IF-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
197; RV32IF-NEXT:    flw fs1, 4(sp) # 4-byte Folded Reload
198; RV32IF-NEXT:    addi sp, sp, 16
199; RV32IF-NEXT:    ret
200;
201; RV32I-LABEL: sincos_f32:
202; RV32I:       # %bb.0:
203; RV32I-NEXT:    addi sp, sp, -16
204; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
205; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
206; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
207; RV32I-NEXT:    mv s0, a0
208; RV32I-NEXT:    call sinf@plt
209; RV32I-NEXT:    mv s1, a0
210; RV32I-NEXT:    mv a0, s0
211; RV32I-NEXT:    call cosf@plt
212; RV32I-NEXT:    mv a1, a0
213; RV32I-NEXT:    mv a0, s1
214; RV32I-NEXT:    call __addsf3@plt
215; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
216; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
217; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
218; RV32I-NEXT:    addi sp, sp, 16
219; RV32I-NEXT:    ret
220;
221; RV64I-LABEL: sincos_f32:
222; RV64I:       # %bb.0:
223; RV64I-NEXT:    addi sp, sp, -32
224; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
225; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
226; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
227; RV64I-NEXT:    mv s0, a0
228; RV64I-NEXT:    call sinf@plt
229; RV64I-NEXT:    mv s1, a0
230; RV64I-NEXT:    mv a0, s0
231; RV64I-NEXT:    call cosf@plt
232; RV64I-NEXT:    mv a1, a0
233; RV64I-NEXT:    mv a0, s1
234; RV64I-NEXT:    call __addsf3@plt
235; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
236; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
237; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
238; RV64I-NEXT:    addi sp, sp, 32
239; RV64I-NEXT:    ret
240  %1 = call float @llvm.sin.f32(float %a)
241  %2 = call float @llvm.cos.f32(float %a)
242  %3 = fadd float %1, %2
243  ret float %3
244}
245
246declare float @llvm.pow.f32(float, float)
247
248define float @pow_f32(float %a, float %b) nounwind {
249; RV32IF-LABEL: pow_f32:
250; RV32IF:       # %bb.0:
251; RV32IF-NEXT:    addi sp, sp, -16
252; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
253; RV32IF-NEXT:    call powf@plt
254; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
255; RV32IF-NEXT:    addi sp, sp, 16
256; RV32IF-NEXT:    ret
257;
258; RV64IF-LABEL: pow_f32:
259; RV64IF:       # %bb.0:
260; RV64IF-NEXT:    addi sp, sp, -16
261; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
262; RV64IF-NEXT:    call powf@plt
263; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
264; RV64IF-NEXT:    addi sp, sp, 16
265; RV64IF-NEXT:    ret
266;
267; RV32I-LABEL: pow_f32:
268; RV32I:       # %bb.0:
269; RV32I-NEXT:    addi sp, sp, -16
270; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
271; RV32I-NEXT:    call powf@plt
272; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
273; RV32I-NEXT:    addi sp, sp, 16
274; RV32I-NEXT:    ret
275;
276; RV64I-LABEL: pow_f32:
277; RV64I:       # %bb.0:
278; RV64I-NEXT:    addi sp, sp, -16
279; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
280; RV64I-NEXT:    call powf@plt
281; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
282; RV64I-NEXT:    addi sp, sp, 16
283; RV64I-NEXT:    ret
284  %1 = call float @llvm.pow.f32(float %a, float %b)
285  ret float %1
286}
287
288declare float @llvm.exp.f32(float)
289
290define float @exp_f32(float %a) nounwind {
291; RV32IF-LABEL: exp_f32:
292; RV32IF:       # %bb.0:
293; RV32IF-NEXT:    addi sp, sp, -16
294; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
295; RV32IF-NEXT:    call expf@plt
296; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
297; RV32IF-NEXT:    addi sp, sp, 16
298; RV32IF-NEXT:    ret
299;
300; RV64IF-LABEL: exp_f32:
301; RV64IF:       # %bb.0:
302; RV64IF-NEXT:    addi sp, sp, -16
303; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
304; RV64IF-NEXT:    call expf@plt
305; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
306; RV64IF-NEXT:    addi sp, sp, 16
307; RV64IF-NEXT:    ret
308;
309; RV32I-LABEL: exp_f32:
310; RV32I:       # %bb.0:
311; RV32I-NEXT:    addi sp, sp, -16
312; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
313; RV32I-NEXT:    call expf@plt
314; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
315; RV32I-NEXT:    addi sp, sp, 16
316; RV32I-NEXT:    ret
317;
318; RV64I-LABEL: exp_f32:
319; RV64I:       # %bb.0:
320; RV64I-NEXT:    addi sp, sp, -16
321; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
322; RV64I-NEXT:    call expf@plt
323; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
324; RV64I-NEXT:    addi sp, sp, 16
325; RV64I-NEXT:    ret
326  %1 = call float @llvm.exp.f32(float %a)
327  ret float %1
328}
329
330declare float @llvm.exp2.f32(float)
331
332define float @exp2_f32(float %a) nounwind {
333; RV32IF-LABEL: exp2_f32:
334; RV32IF:       # %bb.0:
335; RV32IF-NEXT:    addi sp, sp, -16
336; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
337; RV32IF-NEXT:    call exp2f@plt
338; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
339; RV32IF-NEXT:    addi sp, sp, 16
340; RV32IF-NEXT:    ret
341;
342; RV64IF-LABEL: exp2_f32:
343; RV64IF:       # %bb.0:
344; RV64IF-NEXT:    addi sp, sp, -16
345; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
346; RV64IF-NEXT:    call exp2f@plt
347; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
348; RV64IF-NEXT:    addi sp, sp, 16
349; RV64IF-NEXT:    ret
350;
351; RV32I-LABEL: exp2_f32:
352; RV32I:       # %bb.0:
353; RV32I-NEXT:    addi sp, sp, -16
354; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
355; RV32I-NEXT:    call exp2f@plt
356; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
357; RV32I-NEXT:    addi sp, sp, 16
358; RV32I-NEXT:    ret
359;
360; RV64I-LABEL: exp2_f32:
361; RV64I:       # %bb.0:
362; RV64I-NEXT:    addi sp, sp, -16
363; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
364; RV64I-NEXT:    call exp2f@plt
365; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
366; RV64I-NEXT:    addi sp, sp, 16
367; RV64I-NEXT:    ret
368  %1 = call float @llvm.exp2.f32(float %a)
369  ret float %1
370}
371
372declare float @llvm.log.f32(float)
373
374define float @log_f32(float %a) nounwind {
375; RV32IF-LABEL: log_f32:
376; RV32IF:       # %bb.0:
377; RV32IF-NEXT:    addi sp, sp, -16
378; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
379; RV32IF-NEXT:    call logf@plt
380; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
381; RV32IF-NEXT:    addi sp, sp, 16
382; RV32IF-NEXT:    ret
383;
384; RV64IF-LABEL: log_f32:
385; RV64IF:       # %bb.0:
386; RV64IF-NEXT:    addi sp, sp, -16
387; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
388; RV64IF-NEXT:    call logf@plt
389; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
390; RV64IF-NEXT:    addi sp, sp, 16
391; RV64IF-NEXT:    ret
392;
393; RV32I-LABEL: log_f32:
394; RV32I:       # %bb.0:
395; RV32I-NEXT:    addi sp, sp, -16
396; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
397; RV32I-NEXT:    call logf@plt
398; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
399; RV32I-NEXT:    addi sp, sp, 16
400; RV32I-NEXT:    ret
401;
402; RV64I-LABEL: log_f32:
403; RV64I:       # %bb.0:
404; RV64I-NEXT:    addi sp, sp, -16
405; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
406; RV64I-NEXT:    call logf@plt
407; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
408; RV64I-NEXT:    addi sp, sp, 16
409; RV64I-NEXT:    ret
410  %1 = call float @llvm.log.f32(float %a)
411  ret float %1
412}
413
414declare float @llvm.log10.f32(float)
415
416define float @log10_f32(float %a) nounwind {
417; RV32IF-LABEL: log10_f32:
418; RV32IF:       # %bb.0:
419; RV32IF-NEXT:    addi sp, sp, -16
420; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
421; RV32IF-NEXT:    call log10f@plt
422; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
423; RV32IF-NEXT:    addi sp, sp, 16
424; RV32IF-NEXT:    ret
425;
426; RV64IF-LABEL: log10_f32:
427; RV64IF:       # %bb.0:
428; RV64IF-NEXT:    addi sp, sp, -16
429; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
430; RV64IF-NEXT:    call log10f@plt
431; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
432; RV64IF-NEXT:    addi sp, sp, 16
433; RV64IF-NEXT:    ret
434;
435; RV32I-LABEL: log10_f32:
436; RV32I:       # %bb.0:
437; RV32I-NEXT:    addi sp, sp, -16
438; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
439; RV32I-NEXT:    call log10f@plt
440; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
441; RV32I-NEXT:    addi sp, sp, 16
442; RV32I-NEXT:    ret
443;
444; RV64I-LABEL: log10_f32:
445; RV64I:       # %bb.0:
446; RV64I-NEXT:    addi sp, sp, -16
447; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
448; RV64I-NEXT:    call log10f@plt
449; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
450; RV64I-NEXT:    addi sp, sp, 16
451; RV64I-NEXT:    ret
452  %1 = call float @llvm.log10.f32(float %a)
453  ret float %1
454}
455
456declare float @llvm.log2.f32(float)
457
458define float @log2_f32(float %a) nounwind {
459; RV32IF-LABEL: log2_f32:
460; RV32IF:       # %bb.0:
461; RV32IF-NEXT:    addi sp, sp, -16
462; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
463; RV32IF-NEXT:    call log2f@plt
464; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
465; RV32IF-NEXT:    addi sp, sp, 16
466; RV32IF-NEXT:    ret
467;
468; RV64IF-LABEL: log2_f32:
469; RV64IF:       # %bb.0:
470; RV64IF-NEXT:    addi sp, sp, -16
471; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
472; RV64IF-NEXT:    call log2f@plt
473; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
474; RV64IF-NEXT:    addi sp, sp, 16
475; RV64IF-NEXT:    ret
476;
477; RV32I-LABEL: log2_f32:
478; RV32I:       # %bb.0:
479; RV32I-NEXT:    addi sp, sp, -16
480; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
481; RV32I-NEXT:    call log2f@plt
482; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
483; RV32I-NEXT:    addi sp, sp, 16
484; RV32I-NEXT:    ret
485;
486; RV64I-LABEL: log2_f32:
487; RV64I:       # %bb.0:
488; RV64I-NEXT:    addi sp, sp, -16
489; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
490; RV64I-NEXT:    call log2f@plt
491; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
492; RV64I-NEXT:    addi sp, sp, 16
493; RV64I-NEXT:    ret
494  %1 = call float @llvm.log2.f32(float %a)
495  ret float %1
496}
497
498declare float @llvm.fma.f32(float, float, float)
499
500define float @fma_f32(float %a, float %b, float %c) nounwind {
501; RV32IF-LABEL: fma_f32:
502; RV32IF:       # %bb.0:
503; RV32IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
504; RV32IF-NEXT:    ret
505;
506; RV64IF-LABEL: fma_f32:
507; RV64IF:       # %bb.0:
508; RV64IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
509; RV64IF-NEXT:    ret
510;
511; RV32I-LABEL: fma_f32:
512; RV32I:       # %bb.0:
513; RV32I-NEXT:    addi sp, sp, -16
514; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
515; RV32I-NEXT:    call fmaf@plt
516; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
517; RV32I-NEXT:    addi sp, sp, 16
518; RV32I-NEXT:    ret
519;
520; RV64I-LABEL: fma_f32:
521; RV64I:       # %bb.0:
522; RV64I-NEXT:    addi sp, sp, -16
523; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
524; RV64I-NEXT:    call fmaf@plt
525; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
526; RV64I-NEXT:    addi sp, sp, 16
527; RV64I-NEXT:    ret
528  %1 = call float @llvm.fma.f32(float %a, float %b, float %c)
529  ret float %1
530}
531
532declare float @llvm.fmuladd.f32(float, float, float)
533
534define float @fmuladd_f32(float %a, float %b, float %c) nounwind {
535; RV32IF-LABEL: fmuladd_f32:
536; RV32IF:       # %bb.0:
537; RV32IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
538; RV32IF-NEXT:    ret
539;
540; RV64IF-LABEL: fmuladd_f32:
541; RV64IF:       # %bb.0:
542; RV64IF-NEXT:    fmadd.s fa0, fa0, fa1, fa2
543; RV64IF-NEXT:    ret
544;
545; RV32I-LABEL: fmuladd_f32:
546; RV32I:       # %bb.0:
547; RV32I-NEXT:    addi sp, sp, -16
548; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
549; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
550; RV32I-NEXT:    mv s0, a2
551; RV32I-NEXT:    call __mulsf3@plt
552; RV32I-NEXT:    mv a1, s0
553; RV32I-NEXT:    call __addsf3@plt
554; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
555; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
556; RV32I-NEXT:    addi sp, sp, 16
557; RV32I-NEXT:    ret
558;
559; RV64I-LABEL: fmuladd_f32:
560; RV64I:       # %bb.0:
561; RV64I-NEXT:    addi sp, sp, -16
562; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
563; RV64I-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
564; RV64I-NEXT:    mv s0, a2
565; RV64I-NEXT:    call __mulsf3@plt
566; RV64I-NEXT:    mv a1, s0
567; RV64I-NEXT:    call __addsf3@plt
568; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
569; RV64I-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
570; RV64I-NEXT:    addi sp, sp, 16
571; RV64I-NEXT:    ret
572  %1 = call float @llvm.fmuladd.f32(float %a, float %b, float %c)
573  ret float %1
574}
575
576declare float @llvm.fabs.f32(float)
577
578define float @fabs_f32(float %a) nounwind {
579; RV32IF-LABEL: fabs_f32:
580; RV32IF:       # %bb.0:
581; RV32IF-NEXT:    fabs.s fa0, fa0
582; RV32IF-NEXT:    ret
583;
584; RV64IF-LABEL: fabs_f32:
585; RV64IF:       # %bb.0:
586; RV64IF-NEXT:    fabs.s fa0, fa0
587; RV64IF-NEXT:    ret
588;
589; RV32I-LABEL: fabs_f32:
590; RV32I:       # %bb.0:
591; RV32I-NEXT:    slli a0, a0, 1
592; RV32I-NEXT:    srli a0, a0, 1
593; RV32I-NEXT:    ret
594;
595; RV64I-LABEL: fabs_f32:
596; RV64I:       # %bb.0:
597; RV64I-NEXT:    slli a0, a0, 33
598; RV64I-NEXT:    srli a0, a0, 33
599; RV64I-NEXT:    ret
600  %1 = call float @llvm.fabs.f32(float %a)
601  ret float %1
602}
603
604declare float @llvm.minnum.f32(float, float)
605
606define float @minnum_f32(float %a, float %b) nounwind {
607; RV32IF-LABEL: minnum_f32:
608; RV32IF:       # %bb.0:
609; RV32IF-NEXT:    fmin.s fa0, fa0, fa1
610; RV32IF-NEXT:    ret
611;
612; RV64IF-LABEL: minnum_f32:
613; RV64IF:       # %bb.0:
614; RV64IF-NEXT:    fmin.s fa0, fa0, fa1
615; RV64IF-NEXT:    ret
616;
617; RV32I-LABEL: minnum_f32:
618; RV32I:       # %bb.0:
619; RV32I-NEXT:    addi sp, sp, -16
620; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
621; RV32I-NEXT:    call fminf@plt
622; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
623; RV32I-NEXT:    addi sp, sp, 16
624; RV32I-NEXT:    ret
625;
626; RV64I-LABEL: minnum_f32:
627; RV64I:       # %bb.0:
628; RV64I-NEXT:    addi sp, sp, -16
629; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
630; RV64I-NEXT:    call fminf@plt
631; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
632; RV64I-NEXT:    addi sp, sp, 16
633; RV64I-NEXT:    ret
634  %1 = call float @llvm.minnum.f32(float %a, float %b)
635  ret float %1
636}
637
638declare float @llvm.maxnum.f32(float, float)
639
640define float @maxnum_f32(float %a, float %b) nounwind {
641; RV32IF-LABEL: maxnum_f32:
642; RV32IF:       # %bb.0:
643; RV32IF-NEXT:    fmax.s fa0, fa0, fa1
644; RV32IF-NEXT:    ret
645;
646; RV64IF-LABEL: maxnum_f32:
647; RV64IF:       # %bb.0:
648; RV64IF-NEXT:    fmax.s fa0, fa0, fa1
649; RV64IF-NEXT:    ret
650;
651; RV32I-LABEL: maxnum_f32:
652; RV32I:       # %bb.0:
653; RV32I-NEXT:    addi sp, sp, -16
654; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
655; RV32I-NEXT:    call fmaxf@plt
656; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
657; RV32I-NEXT:    addi sp, sp, 16
658; RV32I-NEXT:    ret
659;
660; RV64I-LABEL: maxnum_f32:
661; RV64I:       # %bb.0:
662; RV64I-NEXT:    addi sp, sp, -16
663; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
664; RV64I-NEXT:    call fmaxf@plt
665; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
666; RV64I-NEXT:    addi sp, sp, 16
667; RV64I-NEXT:    ret
668  %1 = call float @llvm.maxnum.f32(float %a, float %b)
669  ret float %1
670}
671
672; TODO: FMINNAN and FMAXNAN aren't handled in
673; SelectionDAGLegalize::ExpandNode.
674
675; declare float @llvm.minimum.f32(float, float)
676
677; define float @fminimum_f32(float %a, float %b) nounwind {
678;   %1 = call float @llvm.minimum.f32(float %a, float %b)
679;   ret float %1
680; }
681
682; declare float @llvm.maximum.f32(float, float)
683
684; define float @fmaximum_f32(float %a, float %b) nounwind {
685;   %1 = call float @llvm.maximum.f32(float %a, float %b)
686;   ret float %1
687; }
688
689declare float @llvm.copysign.f32(float, float)
690
691define float @copysign_f32(float %a, float %b) nounwind {
692; RV32IF-LABEL: copysign_f32:
693; RV32IF:       # %bb.0:
694; RV32IF-NEXT:    fsgnj.s fa0, fa0, fa1
695; RV32IF-NEXT:    ret
696;
697; RV64IF-LABEL: copysign_f32:
698; RV64IF:       # %bb.0:
699; RV64IF-NEXT:    fsgnj.s fa0, fa0, fa1
700; RV64IF-NEXT:    ret
701;
702; RV32I-LABEL: copysign_f32:
703; RV32I:       # %bb.0:
704; RV32I-NEXT:    lui a2, 524288
705; RV32I-NEXT:    and a1, a1, a2
706; RV32I-NEXT:    slli a0, a0, 1
707; RV32I-NEXT:    srli a0, a0, 1
708; RV32I-NEXT:    or a0, a0, a1
709; RV32I-NEXT:    ret
710;
711; RV64I-LABEL: copysign_f32:
712; RV64I:       # %bb.0:
713; RV64I-NEXT:    lui a2, 524288
714; RV64I-NEXT:    and a1, a1, a2
715; RV64I-NEXT:    slli a0, a0, 33
716; RV64I-NEXT:    srli a0, a0, 33
717; RV64I-NEXT:    or a0, a0, a1
718; RV64I-NEXT:    ret
719  %1 = call float @llvm.copysign.f32(float %a, float %b)
720  ret float %1
721}
722
723declare float @llvm.floor.f32(float)
724
725define float @floor_f32(float %a) nounwind {
726; RV32IF-LABEL: floor_f32:
727; RV32IF:       # %bb.0:
728; RV32IF-NEXT:    addi sp, sp, -16
729; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
730; RV32IF-NEXT:    call floorf@plt
731; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
732; RV32IF-NEXT:    addi sp, sp, 16
733; RV32IF-NEXT:    ret
734;
735; RV64IF-LABEL: floor_f32:
736; RV64IF:       # %bb.0:
737; RV64IF-NEXT:    addi sp, sp, -16
738; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
739; RV64IF-NEXT:    call floorf@plt
740; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
741; RV64IF-NEXT:    addi sp, sp, 16
742; RV64IF-NEXT:    ret
743;
744; RV32I-LABEL: floor_f32:
745; RV32I:       # %bb.0:
746; RV32I-NEXT:    addi sp, sp, -16
747; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
748; RV32I-NEXT:    call floorf@plt
749; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
750; RV32I-NEXT:    addi sp, sp, 16
751; RV32I-NEXT:    ret
752;
753; RV64I-LABEL: floor_f32:
754; RV64I:       # %bb.0:
755; RV64I-NEXT:    addi sp, sp, -16
756; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
757; RV64I-NEXT:    call floorf@plt
758; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
759; RV64I-NEXT:    addi sp, sp, 16
760; RV64I-NEXT:    ret
761  %1 = call float @llvm.floor.f32(float %a)
762  ret float %1
763}
764
765declare float @llvm.ceil.f32(float)
766
767define float @ceil_f32(float %a) nounwind {
768; RV32IF-LABEL: ceil_f32:
769; RV32IF:       # %bb.0:
770; RV32IF-NEXT:    addi sp, sp, -16
771; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
772; RV32IF-NEXT:    call ceilf@plt
773; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
774; RV32IF-NEXT:    addi sp, sp, 16
775; RV32IF-NEXT:    ret
776;
777; RV64IF-LABEL: ceil_f32:
778; RV64IF:       # %bb.0:
779; RV64IF-NEXT:    addi sp, sp, -16
780; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
781; RV64IF-NEXT:    call ceilf@plt
782; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
783; RV64IF-NEXT:    addi sp, sp, 16
784; RV64IF-NEXT:    ret
785;
786; RV32I-LABEL: ceil_f32:
787; RV32I:       # %bb.0:
788; RV32I-NEXT:    addi sp, sp, -16
789; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
790; RV32I-NEXT:    call ceilf@plt
791; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
792; RV32I-NEXT:    addi sp, sp, 16
793; RV32I-NEXT:    ret
794;
795; RV64I-LABEL: ceil_f32:
796; RV64I:       # %bb.0:
797; RV64I-NEXT:    addi sp, sp, -16
798; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
799; RV64I-NEXT:    call ceilf@plt
800; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
801; RV64I-NEXT:    addi sp, sp, 16
802; RV64I-NEXT:    ret
803  %1 = call float @llvm.ceil.f32(float %a)
804  ret float %1
805}
806
807declare float @llvm.trunc.f32(float)
808
809define float @trunc_f32(float %a) nounwind {
810; RV32IF-LABEL: trunc_f32:
811; RV32IF:       # %bb.0:
812; RV32IF-NEXT:    addi sp, sp, -16
813; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
814; RV32IF-NEXT:    call truncf@plt
815; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
816; RV32IF-NEXT:    addi sp, sp, 16
817; RV32IF-NEXT:    ret
818;
819; RV64IF-LABEL: trunc_f32:
820; RV64IF:       # %bb.0:
821; RV64IF-NEXT:    addi sp, sp, -16
822; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
823; RV64IF-NEXT:    call truncf@plt
824; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
825; RV64IF-NEXT:    addi sp, sp, 16
826; RV64IF-NEXT:    ret
827;
828; RV32I-LABEL: trunc_f32:
829; RV32I:       # %bb.0:
830; RV32I-NEXT:    addi sp, sp, -16
831; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
832; RV32I-NEXT:    call truncf@plt
833; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
834; RV32I-NEXT:    addi sp, sp, 16
835; RV32I-NEXT:    ret
836;
837; RV64I-LABEL: trunc_f32:
838; RV64I:       # %bb.0:
839; RV64I-NEXT:    addi sp, sp, -16
840; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
841; RV64I-NEXT:    call truncf@plt
842; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
843; RV64I-NEXT:    addi sp, sp, 16
844; RV64I-NEXT:    ret
845  %1 = call float @llvm.trunc.f32(float %a)
846  ret float %1
847}
848
849declare float @llvm.rint.f32(float)
850
851define float @rint_f32(float %a) nounwind {
852; RV32IF-LABEL: rint_f32:
853; RV32IF:       # %bb.0:
854; RV32IF-NEXT:    addi sp, sp, -16
855; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
856; RV32IF-NEXT:    call rintf@plt
857; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
858; RV32IF-NEXT:    addi sp, sp, 16
859; RV32IF-NEXT:    ret
860;
861; RV64IF-LABEL: rint_f32:
862; RV64IF:       # %bb.0:
863; RV64IF-NEXT:    addi sp, sp, -16
864; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
865; RV64IF-NEXT:    call rintf@plt
866; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
867; RV64IF-NEXT:    addi sp, sp, 16
868; RV64IF-NEXT:    ret
869;
870; RV32I-LABEL: rint_f32:
871; RV32I:       # %bb.0:
872; RV32I-NEXT:    addi sp, sp, -16
873; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
874; RV32I-NEXT:    call rintf@plt
875; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
876; RV32I-NEXT:    addi sp, sp, 16
877; RV32I-NEXT:    ret
878;
879; RV64I-LABEL: rint_f32:
880; RV64I:       # %bb.0:
881; RV64I-NEXT:    addi sp, sp, -16
882; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
883; RV64I-NEXT:    call rintf@plt
884; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
885; RV64I-NEXT:    addi sp, sp, 16
886; RV64I-NEXT:    ret
887  %1 = call float @llvm.rint.f32(float %a)
888  ret float %1
889}
890
891declare float @llvm.nearbyint.f32(float)
892
893define float @nearbyint_f32(float %a) nounwind {
894; RV32IF-LABEL: nearbyint_f32:
895; RV32IF:       # %bb.0:
896; RV32IF-NEXT:    addi sp, sp, -16
897; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
898; RV32IF-NEXT:    call nearbyintf@plt
899; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
900; RV32IF-NEXT:    addi sp, sp, 16
901; RV32IF-NEXT:    ret
902;
903; RV64IF-LABEL: nearbyint_f32:
904; RV64IF:       # %bb.0:
905; RV64IF-NEXT:    addi sp, sp, -16
906; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
907; RV64IF-NEXT:    call nearbyintf@plt
908; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
909; RV64IF-NEXT:    addi sp, sp, 16
910; RV64IF-NEXT:    ret
911;
912; RV32I-LABEL: nearbyint_f32:
913; RV32I:       # %bb.0:
914; RV32I-NEXT:    addi sp, sp, -16
915; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
916; RV32I-NEXT:    call nearbyintf@plt
917; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
918; RV32I-NEXT:    addi sp, sp, 16
919; RV32I-NEXT:    ret
920;
921; RV64I-LABEL: nearbyint_f32:
922; RV64I:       # %bb.0:
923; RV64I-NEXT:    addi sp, sp, -16
924; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
925; RV64I-NEXT:    call nearbyintf@plt
926; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
927; RV64I-NEXT:    addi sp, sp, 16
928; RV64I-NEXT:    ret
929  %1 = call float @llvm.nearbyint.f32(float %a)
930  ret float %1
931}
932
933declare float @llvm.round.f32(float)
934
935define float @round_f32(float %a) nounwind {
936; RV32IF-LABEL: round_f32:
937; RV32IF:       # %bb.0:
938; RV32IF-NEXT:    addi sp, sp, -16
939; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
940; RV32IF-NEXT:    call roundf@plt
941; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
942; RV32IF-NEXT:    addi sp, sp, 16
943; RV32IF-NEXT:    ret
944;
945; RV64IF-LABEL: round_f32:
946; RV64IF:       # %bb.0:
947; RV64IF-NEXT:    addi sp, sp, -16
948; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
949; RV64IF-NEXT:    call roundf@plt
950; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
951; RV64IF-NEXT:    addi sp, sp, 16
952; RV64IF-NEXT:    ret
953;
954; RV32I-LABEL: round_f32:
955; RV32I:       # %bb.0:
956; RV32I-NEXT:    addi sp, sp, -16
957; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
958; RV32I-NEXT:    call roundf@plt
959; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
960; RV32I-NEXT:    addi sp, sp, 16
961; RV32I-NEXT:    ret
962;
963; RV64I-LABEL: round_f32:
964; RV64I:       # %bb.0:
965; RV64I-NEXT:    addi sp, sp, -16
966; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
967; RV64I-NEXT:    call roundf@plt
968; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
969; RV64I-NEXT:    addi sp, sp, 16
970; RV64I-NEXT:    ret
971  %1 = call float @llvm.round.f32(float %a)
972  ret float %1
973}
974
975declare float @llvm.roundeven.f32(float)
976
977define float @roundeven_f32(float %a) nounwind {
978; RV32IF-LABEL: roundeven_f32:
979; RV32IF:       # %bb.0:
980; RV32IF-NEXT:    addi sp, sp, -16
981; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
982; RV32IF-NEXT:    call roundevenf@plt
983; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
984; RV32IF-NEXT:    addi sp, sp, 16
985; RV32IF-NEXT:    ret
986;
987; RV64IF-LABEL: roundeven_f32:
988; RV64IF:       # %bb.0:
989; RV64IF-NEXT:    addi sp, sp, -16
990; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
991; RV64IF-NEXT:    call roundevenf@plt
992; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
993; RV64IF-NEXT:    addi sp, sp, 16
994; RV64IF-NEXT:    ret
995;
996; RV32I-LABEL: roundeven_f32:
997; RV32I:       # %bb.0:
998; RV32I-NEXT:    addi sp, sp, -16
999; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1000; RV32I-NEXT:    call roundevenf@plt
1001; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1002; RV32I-NEXT:    addi sp, sp, 16
1003; RV32I-NEXT:    ret
1004;
1005; RV64I-LABEL: roundeven_f32:
1006; RV64I:       # %bb.0:
1007; RV64I-NEXT:    addi sp, sp, -16
1008; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1009; RV64I-NEXT:    call roundevenf@plt
1010; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1011; RV64I-NEXT:    addi sp, sp, 16
1012; RV64I-NEXT:    ret
1013  %1 = call float @llvm.roundeven.f32(float %a)
1014  ret float %1
1015}
1016
1017declare iXLen @llvm.lrint.iXLen.f32(float)
1018
1019define iXLen @lrint_f32(float %a) nounwind {
1020; RV32IF-LABEL: lrint_f32:
1021; RV32IF:       # %bb.0:
1022; RV32IF-NEXT:    fcvt.w.s a0, fa0
1023; RV32IF-NEXT:    ret
1024;
1025; RV64IF-LABEL: lrint_f32:
1026; RV64IF:       # %bb.0:
1027; RV64IF-NEXT:    fcvt.l.s a0, fa0
1028; RV64IF-NEXT:    ret
1029;
1030; RV32I-LABEL: lrint_f32:
1031; RV32I:       # %bb.0:
1032; RV32I-NEXT:    addi sp, sp, -16
1033; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1034; RV32I-NEXT:    call lrintf@plt
1035; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1036; RV32I-NEXT:    addi sp, sp, 16
1037; RV32I-NEXT:    ret
1038;
1039; RV64I-LABEL: lrint_f32:
1040; RV64I:       # %bb.0:
1041; RV64I-NEXT:    addi sp, sp, -16
1042; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1043; RV64I-NEXT:    call lrintf@plt
1044; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1045; RV64I-NEXT:    addi sp, sp, 16
1046; RV64I-NEXT:    ret
1047  %1 = call iXLen @llvm.lrint.iXLen.f32(float %a)
1048  ret iXLen %1
1049}
1050
1051declare iXLen @llvm.lround.iXLen.f32(float)
1052
1053define iXLen @lround_f32(float %a) nounwind {
1054; RV32IF-LABEL: lround_f32:
1055; RV32IF:       # %bb.0:
1056; RV32IF-NEXT:    fcvt.w.s a0, fa0, rmm
1057; RV32IF-NEXT:    ret
1058;
1059; RV64IF-LABEL: lround_f32:
1060; RV64IF:       # %bb.0:
1061; RV64IF-NEXT:    fcvt.l.s a0, fa0, rmm
1062; RV64IF-NEXT:    ret
1063;
1064; RV32I-LABEL: lround_f32:
1065; RV32I:       # %bb.0:
1066; RV32I-NEXT:    addi sp, sp, -16
1067; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1068; RV32I-NEXT:    call lroundf@plt
1069; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1070; RV32I-NEXT:    addi sp, sp, 16
1071; RV32I-NEXT:    ret
1072;
1073; RV64I-LABEL: lround_f32:
1074; RV64I:       # %bb.0:
1075; RV64I-NEXT:    addi sp, sp, -16
1076; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1077; RV64I-NEXT:    call lroundf@plt
1078; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1079; RV64I-NEXT:    addi sp, sp, 16
1080; RV64I-NEXT:    ret
1081  %1 = call iXLen @llvm.lround.iXLen.f32(float %a)
1082  ret iXLen %1
1083}
1084
1085declare i64 @llvm.llrint.i64.f32(float)
1086
1087define i64 @llrint_f32(float %a) nounwind {
1088; RV32IF-LABEL: llrint_f32:
1089; RV32IF:       # %bb.0:
1090; RV32IF-NEXT:    addi sp, sp, -16
1091; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1092; RV32IF-NEXT:    call llrintf@plt
1093; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1094; RV32IF-NEXT:    addi sp, sp, 16
1095; RV32IF-NEXT:    ret
1096;
1097; RV64IF-LABEL: llrint_f32:
1098; RV64IF:       # %bb.0:
1099; RV64IF-NEXT:    fcvt.l.s a0, fa0
1100; RV64IF-NEXT:    ret
1101;
1102; RV32I-LABEL: llrint_f32:
1103; RV32I:       # %bb.0:
1104; RV32I-NEXT:    addi sp, sp, -16
1105; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1106; RV32I-NEXT:    call llrintf@plt
1107; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1108; RV32I-NEXT:    addi sp, sp, 16
1109; RV32I-NEXT:    ret
1110;
1111; RV64I-LABEL: llrint_f32:
1112; RV64I:       # %bb.0:
1113; RV64I-NEXT:    addi sp, sp, -16
1114; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1115; RV64I-NEXT:    call llrintf@plt
1116; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1117; RV64I-NEXT:    addi sp, sp, 16
1118; RV64I-NEXT:    ret
1119  %1 = call i64 @llvm.llrint.i64.f32(float %a)
1120  ret i64 %1
1121}
1122
1123declare i64 @llvm.llround.i64.f32(float)
1124
1125define i64 @llround_f32(float %a) nounwind {
1126; RV32IF-LABEL: llround_f32:
1127; RV32IF:       # %bb.0:
1128; RV32IF-NEXT:    addi sp, sp, -16
1129; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1130; RV32IF-NEXT:    call llroundf@plt
1131; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1132; RV32IF-NEXT:    addi sp, sp, 16
1133; RV32IF-NEXT:    ret
1134;
1135; RV64IF-LABEL: llround_f32:
1136; RV64IF:       # %bb.0:
1137; RV64IF-NEXT:    fcvt.l.s a0, fa0, rmm
1138; RV64IF-NEXT:    ret
1139;
1140; RV32I-LABEL: llround_f32:
1141; RV32I:       # %bb.0:
1142; RV32I-NEXT:    addi sp, sp, -16
1143; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1144; RV32I-NEXT:    call llroundf@plt
1145; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1146; RV32I-NEXT:    addi sp, sp, 16
1147; RV32I-NEXT:    ret
1148;
1149; RV64I-LABEL: llround_f32:
1150; RV64I:       # %bb.0:
1151; RV64I-NEXT:    addi sp, sp, -16
1152; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1153; RV64I-NEXT:    call llroundf@plt
1154; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1155; RV64I-NEXT:    addi sp, sp, 16
1156; RV64I-NEXT:    ret
1157  %1 = call i64 @llvm.llround.i64.f32(float %a)
1158  ret i64 %1
1159}
1160