1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
3; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
4; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
5; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
6; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
7; RUN:   | FileCheck -check-prefix=RV32I %s
8; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
9; RUN:   | FileCheck -check-prefix=RV64I %s
10
11define i32 @fcvt_w_s(float %a) nounwind {
12; RV32IF-LABEL: fcvt_w_s:
13; RV32IF:       # %bb.0:
14; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
15; RV32IF-NEXT:    ret
16;
17; RV64IF-LABEL: fcvt_w_s:
18; RV64IF:       # %bb.0:
19; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
20; RV64IF-NEXT:    ret
21;
22; RV32I-LABEL: fcvt_w_s:
23; RV32I:       # %bb.0:
24; RV32I-NEXT:    addi sp, sp, -16
25; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
26; RV32I-NEXT:    call __fixsfsi@plt
27; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
28; RV32I-NEXT:    addi sp, sp, 16
29; RV32I-NEXT:    ret
30;
31; RV64I-LABEL: fcvt_w_s:
32; RV64I:       # %bb.0:
33; RV64I-NEXT:    addi sp, sp, -16
34; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
35; RV64I-NEXT:    call __fixsfsi@plt
36; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
37; RV64I-NEXT:    addi sp, sp, 16
38; RV64I-NEXT:    ret
39  %1 = fptosi float %a to i32
40  ret i32 %1
41}
42
43define i32 @fcvt_w_s_sat(float %a) nounwind {
44; RV32IF-LABEL: fcvt_w_s_sat:
45; RV32IF:       # %bb.0: # %start
46; RV32IF-NEXT:    feq.s a0, fa0, fa0
47; RV32IF-NEXT:    beqz a0, .LBB1_2
48; RV32IF-NEXT:  # %bb.1:
49; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
50; RV32IF-NEXT:  .LBB1_2: # %start
51; RV32IF-NEXT:    ret
52;
53; RV64IF-LABEL: fcvt_w_s_sat:
54; RV64IF:       # %bb.0: # %start
55; RV64IF-NEXT:    feq.s a0, fa0, fa0
56; RV64IF-NEXT:    beqz a0, .LBB1_2
57; RV64IF-NEXT:  # %bb.1:
58; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
59; RV64IF-NEXT:  .LBB1_2: # %start
60; RV64IF-NEXT:    ret
61;
62; RV32I-LABEL: fcvt_w_s_sat:
63; RV32I:       # %bb.0: # %start
64; RV32I-NEXT:    addi sp, sp, -32
65; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
66; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
67; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
68; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
69; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
70; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
71; RV32I-NEXT:    mv s0, a0
72; RV32I-NEXT:    lui a1, 847872
73; RV32I-NEXT:    call __gesf2@plt
74; RV32I-NEXT:    mv s2, a0
75; RV32I-NEXT:    mv a0, s0
76; RV32I-NEXT:    call __fixsfsi@plt
77; RV32I-NEXT:    li s1, 0
78; RV32I-NEXT:    lui s4, 524288
79; RV32I-NEXT:    lui s3, 524288
80; RV32I-NEXT:    bltz s2, .LBB1_2
81; RV32I-NEXT:  # %bb.1: # %start
82; RV32I-NEXT:    mv s3, a0
83; RV32I-NEXT:  .LBB1_2: # %start
84; RV32I-NEXT:    lui a0, 323584
85; RV32I-NEXT:    addi a1, a0, -1
86; RV32I-NEXT:    mv a0, s0
87; RV32I-NEXT:    call __gtsf2@plt
88; RV32I-NEXT:    bge s1, a0, .LBB1_4
89; RV32I-NEXT:  # %bb.3:
90; RV32I-NEXT:    addi s3, s4, -1
91; RV32I-NEXT:  .LBB1_4: # %start
92; RV32I-NEXT:    mv a0, s0
93; RV32I-NEXT:    mv a1, s0
94; RV32I-NEXT:    call __unordsf2@plt
95; RV32I-NEXT:    bne a0, s1, .LBB1_6
96; RV32I-NEXT:  # %bb.5: # %start
97; RV32I-NEXT:    mv s1, s3
98; RV32I-NEXT:  .LBB1_6: # %start
99; RV32I-NEXT:    mv a0, s1
100; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
101; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
102; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
103; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
104; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
105; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
106; RV32I-NEXT:    addi sp, sp, 32
107; RV32I-NEXT:    ret
108;
109; RV64I-LABEL: fcvt_w_s_sat:
110; RV64I:       # %bb.0: # %start
111; RV64I-NEXT:    addi sp, sp, -48
112; RV64I-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
113; RV64I-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
114; RV64I-NEXT:    sd s1, 24(sp) # 8-byte Folded Spill
115; RV64I-NEXT:    sd s2, 16(sp) # 8-byte Folded Spill
116; RV64I-NEXT:    sd s3, 8(sp) # 8-byte Folded Spill
117; RV64I-NEXT:    sd s4, 0(sp) # 8-byte Folded Spill
118; RV64I-NEXT:    mv s0, a0
119; RV64I-NEXT:    lui a1, 847872
120; RV64I-NEXT:    call __gesf2@plt
121; RV64I-NEXT:    mv s2, a0
122; RV64I-NEXT:    mv a0, s0
123; RV64I-NEXT:    call __fixsfdi@plt
124; RV64I-NEXT:    li s1, 0
125; RV64I-NEXT:    lui s4, 524288
126; RV64I-NEXT:    lui s3, 524288
127; RV64I-NEXT:    bltz s2, .LBB1_2
128; RV64I-NEXT:  # %bb.1: # %start
129; RV64I-NEXT:    mv s3, a0
130; RV64I-NEXT:  .LBB1_2: # %start
131; RV64I-NEXT:    lui a0, 323584
132; RV64I-NEXT:    addiw a1, a0, -1
133; RV64I-NEXT:    mv a0, s0
134; RV64I-NEXT:    call __gtsf2@plt
135; RV64I-NEXT:    bge s1, a0, .LBB1_4
136; RV64I-NEXT:  # %bb.3:
137; RV64I-NEXT:    addiw s3, s4, -1
138; RV64I-NEXT:  .LBB1_4: # %start
139; RV64I-NEXT:    mv a0, s0
140; RV64I-NEXT:    mv a1, s0
141; RV64I-NEXT:    call __unordsf2@plt
142; RV64I-NEXT:    bne a0, s1, .LBB1_6
143; RV64I-NEXT:  # %bb.5: # %start
144; RV64I-NEXT:    mv s1, s3
145; RV64I-NEXT:  .LBB1_6: # %start
146; RV64I-NEXT:    mv a0, s1
147; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
148; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
149; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
150; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
151; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
152; RV64I-NEXT:    ld s4, 0(sp) # 8-byte Folded Reload
153; RV64I-NEXT:    addi sp, sp, 48
154; RV64I-NEXT:    ret
155start:
156  %0 = tail call i32 @llvm.fptosi.sat.i32.f32(float %a)
157  ret i32 %0
158}
159declare i32 @llvm.fptosi.sat.i32.f32(float)
160
161define i32 @fcvt_wu_s(float %a) nounwind {
162; RV32IF-LABEL: fcvt_wu_s:
163; RV32IF:       # %bb.0:
164; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
165; RV32IF-NEXT:    ret
166;
167; RV64IF-LABEL: fcvt_wu_s:
168; RV64IF:       # %bb.0:
169; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
170; RV64IF-NEXT:    ret
171;
172; RV32I-LABEL: fcvt_wu_s:
173; RV32I:       # %bb.0:
174; RV32I-NEXT:    addi sp, sp, -16
175; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
176; RV32I-NEXT:    call __fixunssfsi@plt
177; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
178; RV32I-NEXT:    addi sp, sp, 16
179; RV32I-NEXT:    ret
180;
181; RV64I-LABEL: fcvt_wu_s:
182; RV64I:       # %bb.0:
183; RV64I-NEXT:    addi sp, sp, -16
184; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
185; RV64I-NEXT:    call __fixunssfsi@plt
186; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
187; RV64I-NEXT:    addi sp, sp, 16
188; RV64I-NEXT:    ret
189  %1 = fptoui float %a to i32
190  ret i32 %1
191}
192
193; Test where the fptoui has multiple uses, one of which causes a sext to be
194; inserted on RV64.
195define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) nounwind {
196; RV32IF-LABEL: fcvt_wu_s_multiple_use:
197; RV32IF:       # %bb.0:
198; RV32IF-NEXT:    fcvt.wu.s a1, fa0, rtz
199; RV32IF-NEXT:    li a0, 1
200; RV32IF-NEXT:    beqz a1, .LBB3_2
201; RV32IF-NEXT:  # %bb.1:
202; RV32IF-NEXT:    mv a0, a1
203; RV32IF-NEXT:  .LBB3_2:
204; RV32IF-NEXT:    ret
205;
206; RV64IF-LABEL: fcvt_wu_s_multiple_use:
207; RV64IF:       # %bb.0:
208; RV64IF-NEXT:    fcvt.wu.s a1, fa0, rtz
209; RV64IF-NEXT:    li a0, 1
210; RV64IF-NEXT:    beqz a1, .LBB3_2
211; RV64IF-NEXT:  # %bb.1:
212; RV64IF-NEXT:    mv a0, a1
213; RV64IF-NEXT:  .LBB3_2:
214; RV64IF-NEXT:    ret
215;
216; RV32I-LABEL: fcvt_wu_s_multiple_use:
217; RV32I:       # %bb.0:
218; RV32I-NEXT:    addi sp, sp, -16
219; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
220; RV32I-NEXT:    call __fixunssfsi@plt
221; RV32I-NEXT:    mv a1, a0
222; RV32I-NEXT:    li a0, 1
223; RV32I-NEXT:    beqz a1, .LBB3_2
224; RV32I-NEXT:  # %bb.1:
225; RV32I-NEXT:    mv a0, a1
226; RV32I-NEXT:  .LBB3_2:
227; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
228; RV32I-NEXT:    addi sp, sp, 16
229; RV32I-NEXT:    ret
230;
231; RV64I-LABEL: fcvt_wu_s_multiple_use:
232; RV64I:       # %bb.0:
233; RV64I-NEXT:    addi sp, sp, -16
234; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
235; RV64I-NEXT:    call __fixunssfsi@plt
236; RV64I-NEXT:    mv a1, a0
237; RV64I-NEXT:    li a0, 1
238; RV64I-NEXT:    beqz a1, .LBB3_2
239; RV64I-NEXT:  # %bb.1:
240; RV64I-NEXT:    mv a0, a1
241; RV64I-NEXT:  .LBB3_2:
242; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
243; RV64I-NEXT:    addi sp, sp, 16
244; RV64I-NEXT:    ret
245  %a = fptoui float %x to i32
246  %b = icmp eq i32 %a, 0
247  %c = select i1 %b, i32 1, i32 %a
248  ret i32 %c
249}
250
251define i32 @fcvt_wu_s_sat(float %a) nounwind {
252; RV32IF-LABEL: fcvt_wu_s_sat:
253; RV32IF:       # %bb.0: # %start
254; RV32IF-NEXT:    feq.s a0, fa0, fa0
255; RV32IF-NEXT:    beqz a0, .LBB4_2
256; RV32IF-NEXT:  # %bb.1:
257; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
258; RV32IF-NEXT:  .LBB4_2: # %start
259; RV32IF-NEXT:    ret
260;
261; RV64IF-LABEL: fcvt_wu_s_sat:
262; RV64IF:       # %bb.0: # %start
263; RV64IF-NEXT:    feq.s a0, fa0, fa0
264; RV64IF-NEXT:    beqz a0, .LBB4_2
265; RV64IF-NEXT:  # %bb.1:
266; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
267; RV64IF-NEXT:  .LBB4_2: # %start
268; RV64IF-NEXT:    ret
269;
270; RV32I-LABEL: fcvt_wu_s_sat:
271; RV32I:       # %bb.0: # %start
272; RV32I-NEXT:    addi sp, sp, -16
273; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
274; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
275; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
276; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
277; RV32I-NEXT:    mv s0, a0
278; RV32I-NEXT:    li a1, 0
279; RV32I-NEXT:    call __gesf2@plt
280; RV32I-NEXT:    mv s1, a0
281; RV32I-NEXT:    mv a0, s0
282; RV32I-NEXT:    call __fixunssfsi@plt
283; RV32I-NEXT:    li s2, 0
284; RV32I-NEXT:    bltz s1, .LBB4_2
285; RV32I-NEXT:  # %bb.1: # %start
286; RV32I-NEXT:    mv s2, a0
287; RV32I-NEXT:  .LBB4_2: # %start
288; RV32I-NEXT:    lui a0, 325632
289; RV32I-NEXT:    addi a1, a0, -1
290; RV32I-NEXT:    mv a0, s0
291; RV32I-NEXT:    call __gtsf2@plt
292; RV32I-NEXT:    mv a1, a0
293; RV32I-NEXT:    li a0, -1
294; RV32I-NEXT:    bgtz a1, .LBB4_4
295; RV32I-NEXT:  # %bb.3: # %start
296; RV32I-NEXT:    mv a0, s2
297; RV32I-NEXT:  .LBB4_4: # %start
298; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
299; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
300; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
301; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
302; RV32I-NEXT:    addi sp, sp, 16
303; RV32I-NEXT:    ret
304;
305; RV64I-LABEL: fcvt_wu_s_sat:
306; RV64I:       # %bb.0: # %start
307; RV64I-NEXT:    addi sp, sp, -32
308; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
309; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
310; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
311; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
312; RV64I-NEXT:    mv s0, a0
313; RV64I-NEXT:    li a1, 0
314; RV64I-NEXT:    call __gesf2@plt
315; RV64I-NEXT:    mv s2, a0
316; RV64I-NEXT:    mv a0, s0
317; RV64I-NEXT:    call __fixunssfdi@plt
318; RV64I-NEXT:    li s1, 0
319; RV64I-NEXT:    bltz s2, .LBB4_2
320; RV64I-NEXT:  # %bb.1: # %start
321; RV64I-NEXT:    mv s1, a0
322; RV64I-NEXT:  .LBB4_2: # %start
323; RV64I-NEXT:    lui a0, 325632
324; RV64I-NEXT:    addiw a1, a0, -1
325; RV64I-NEXT:    mv a0, s0
326; RV64I-NEXT:    call __gtsf2@plt
327; RV64I-NEXT:    blez a0, .LBB4_4
328; RV64I-NEXT:  # %bb.3:
329; RV64I-NEXT:    li a0, -1
330; RV64I-NEXT:    srli s1, a0, 32
331; RV64I-NEXT:  .LBB4_4: # %start
332; RV64I-NEXT:    mv a0, s1
333; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
334; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
335; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
336; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
337; RV64I-NEXT:    addi sp, sp, 32
338; RV64I-NEXT:    ret
339start:
340  %0 = tail call i32 @llvm.fptoui.sat.i32.f32(float %a)
341  ret i32 %0
342}
343declare i32 @llvm.fptoui.sat.i32.f32(float)
344
345define i32 @fmv_x_w(float %a, float %b) nounwind {
346; RV32IF-LABEL: fmv_x_w:
347; RV32IF:       # %bb.0:
348; RV32IF-NEXT:    fadd.s ft0, fa0, fa1
349; RV32IF-NEXT:    fmv.x.w a0, ft0
350; RV32IF-NEXT:    ret
351;
352; RV64IF-LABEL: fmv_x_w:
353; RV64IF:       # %bb.0:
354; RV64IF-NEXT:    fadd.s ft0, fa0, fa1
355; RV64IF-NEXT:    fmv.x.w a0, ft0
356; RV64IF-NEXT:    ret
357;
358; RV32I-LABEL: fmv_x_w:
359; RV32I:       # %bb.0:
360; RV32I-NEXT:    addi sp, sp, -16
361; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
362; RV32I-NEXT:    call __addsf3@plt
363; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
364; RV32I-NEXT:    addi sp, sp, 16
365; RV32I-NEXT:    ret
366;
367; RV64I-LABEL: fmv_x_w:
368; RV64I:       # %bb.0:
369; RV64I-NEXT:    addi sp, sp, -16
370; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
371; RV64I-NEXT:    call __addsf3@plt
372; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
373; RV64I-NEXT:    addi sp, sp, 16
374; RV64I-NEXT:    ret
375; Ensure fmv.x.w is generated even for a soft float calling convention
376  %1 = fadd float %a, %b
377  %2 = bitcast float %1 to i32
378  ret i32 %2
379}
380
381define float @fcvt_s_w(i32 %a) nounwind {
382; RV32IF-LABEL: fcvt_s_w:
383; RV32IF:       # %bb.0:
384; RV32IF-NEXT:    fcvt.s.w fa0, a0
385; RV32IF-NEXT:    ret
386;
387; RV64IF-LABEL: fcvt_s_w:
388; RV64IF:       # %bb.0:
389; RV64IF-NEXT:    fcvt.s.w fa0, a0
390; RV64IF-NEXT:    ret
391;
392; RV32I-LABEL: fcvt_s_w:
393; RV32I:       # %bb.0:
394; RV32I-NEXT:    addi sp, sp, -16
395; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
396; RV32I-NEXT:    call __floatsisf@plt
397; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
398; RV32I-NEXT:    addi sp, sp, 16
399; RV32I-NEXT:    ret
400;
401; RV64I-LABEL: fcvt_s_w:
402; RV64I:       # %bb.0:
403; RV64I-NEXT:    addi sp, sp, -16
404; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
405; RV64I-NEXT:    sext.w a0, a0
406; RV64I-NEXT:    call __floatsisf@plt
407; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
408; RV64I-NEXT:    addi sp, sp, 16
409; RV64I-NEXT:    ret
410  %1 = sitofp i32 %a to float
411  ret float %1
412}
413
414define float @fcvt_s_w_load(i32* %p) nounwind {
415; RV32IF-LABEL: fcvt_s_w_load:
416; RV32IF:       # %bb.0:
417; RV32IF-NEXT:    lw a0, 0(a0)
418; RV32IF-NEXT:    fcvt.s.w fa0, a0
419; RV32IF-NEXT:    ret
420;
421; RV64IF-LABEL: fcvt_s_w_load:
422; RV64IF:       # %bb.0:
423; RV64IF-NEXT:    lw a0, 0(a0)
424; RV64IF-NEXT:    fcvt.s.w fa0, a0
425; RV64IF-NEXT:    ret
426;
427; RV32I-LABEL: fcvt_s_w_load:
428; RV32I:       # %bb.0:
429; RV32I-NEXT:    addi sp, sp, -16
430; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
431; RV32I-NEXT:    lw a0, 0(a0)
432; RV32I-NEXT:    call __floatsisf@plt
433; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
434; RV32I-NEXT:    addi sp, sp, 16
435; RV32I-NEXT:    ret
436;
437; RV64I-LABEL: fcvt_s_w_load:
438; RV64I:       # %bb.0:
439; RV64I-NEXT:    addi sp, sp, -16
440; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
441; RV64I-NEXT:    lw a0, 0(a0)
442; RV64I-NEXT:    call __floatsisf@plt
443; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
444; RV64I-NEXT:    addi sp, sp, 16
445; RV64I-NEXT:    ret
446  %a = load i32, i32* %p
447  %1 = sitofp i32 %a to float
448  ret float %1
449}
450
451define float @fcvt_s_wu(i32 %a) nounwind {
452; RV32IF-LABEL: fcvt_s_wu:
453; RV32IF:       # %bb.0:
454; RV32IF-NEXT:    fcvt.s.wu fa0, a0
455; RV32IF-NEXT:    ret
456;
457; RV64IF-LABEL: fcvt_s_wu:
458; RV64IF:       # %bb.0:
459; RV64IF-NEXT:    fcvt.s.wu fa0, a0
460; RV64IF-NEXT:    ret
461;
462; RV32I-LABEL: fcvt_s_wu:
463; RV32I:       # %bb.0:
464; RV32I-NEXT:    addi sp, sp, -16
465; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
466; RV32I-NEXT:    call __floatunsisf@plt
467; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
468; RV32I-NEXT:    addi sp, sp, 16
469; RV32I-NEXT:    ret
470;
471; RV64I-LABEL: fcvt_s_wu:
472; RV64I:       # %bb.0:
473; RV64I-NEXT:    addi sp, sp, -16
474; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
475; RV64I-NEXT:    sext.w a0, a0
476; RV64I-NEXT:    call __floatunsisf@plt
477; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
478; RV64I-NEXT:    addi sp, sp, 16
479; RV64I-NEXT:    ret
480  %1 = uitofp i32 %a to float
481  ret float %1
482}
483
484define float @fcvt_s_wu_load(i32* %p) nounwind {
485; RV32IF-LABEL: fcvt_s_wu_load:
486; RV32IF:       # %bb.0:
487; RV32IF-NEXT:    lw a0, 0(a0)
488; RV32IF-NEXT:    fcvt.s.wu fa0, a0
489; RV32IF-NEXT:    ret
490;
491; RV64IF-LABEL: fcvt_s_wu_load:
492; RV64IF:       # %bb.0:
493; RV64IF-NEXT:    lwu a0, 0(a0)
494; RV64IF-NEXT:    fcvt.s.wu fa0, a0
495; RV64IF-NEXT:    ret
496;
497; RV32I-LABEL: fcvt_s_wu_load:
498; RV32I:       # %bb.0:
499; RV32I-NEXT:    addi sp, sp, -16
500; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
501; RV32I-NEXT:    lw a0, 0(a0)
502; RV32I-NEXT:    call __floatunsisf@plt
503; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
504; RV32I-NEXT:    addi sp, sp, 16
505; RV32I-NEXT:    ret
506;
507; RV64I-LABEL: fcvt_s_wu_load:
508; RV64I:       # %bb.0:
509; RV64I-NEXT:    addi sp, sp, -16
510; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
511; RV64I-NEXT:    lw a0, 0(a0)
512; RV64I-NEXT:    call __floatunsisf@plt
513; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
514; RV64I-NEXT:    addi sp, sp, 16
515; RV64I-NEXT:    ret
516  %a = load i32, i32* %p
517  %1 = uitofp i32 %a to float
518  ret float %1
519}
520
521define float @fmv_w_x(i32 %a, i32 %b) nounwind {
522; RV32IF-LABEL: fmv_w_x:
523; RV32IF:       # %bb.0:
524; RV32IF-NEXT:    fmv.w.x ft0, a0
525; RV32IF-NEXT:    fmv.w.x ft1, a1
526; RV32IF-NEXT:    fadd.s fa0, ft0, ft1
527; RV32IF-NEXT:    ret
528;
529; RV64IF-LABEL: fmv_w_x:
530; RV64IF:       # %bb.0:
531; RV64IF-NEXT:    fmv.w.x ft0, a0
532; RV64IF-NEXT:    fmv.w.x ft1, a1
533; RV64IF-NEXT:    fadd.s fa0, ft0, ft1
534; RV64IF-NEXT:    ret
535;
536; RV32I-LABEL: fmv_w_x:
537; RV32I:       # %bb.0:
538; RV32I-NEXT:    addi sp, sp, -16
539; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
540; RV32I-NEXT:    call __addsf3@plt
541; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
542; RV32I-NEXT:    addi sp, sp, 16
543; RV32I-NEXT:    ret
544;
545; RV64I-LABEL: fmv_w_x:
546; RV64I:       # %bb.0:
547; RV64I-NEXT:    addi sp, sp, -16
548; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
549; RV64I-NEXT:    call __addsf3@plt
550; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
551; RV64I-NEXT:    addi sp, sp, 16
552; RV64I-NEXT:    ret
553; Ensure fmv.w.x is generated even for a soft float calling convention
554  %1 = bitcast i32 %a to float
555  %2 = bitcast i32 %b to float
556  %3 = fadd float %1, %2
557  ret float %3
558}
559
560define i64 @fcvt_l_s(float %a) nounwind {
561; RV32IF-LABEL: fcvt_l_s:
562; RV32IF:       # %bb.0:
563; RV32IF-NEXT:    addi sp, sp, -16
564; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
565; RV32IF-NEXT:    call __fixsfdi@plt
566; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
567; RV32IF-NEXT:    addi sp, sp, 16
568; RV32IF-NEXT:    ret
569;
570; RV64IF-LABEL: fcvt_l_s:
571; RV64IF:       # %bb.0:
572; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
573; RV64IF-NEXT:    ret
574;
575; RV32I-LABEL: fcvt_l_s:
576; RV32I:       # %bb.0:
577; RV32I-NEXT:    addi sp, sp, -16
578; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
579; RV32I-NEXT:    call __fixsfdi@plt
580; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
581; RV32I-NEXT:    addi sp, sp, 16
582; RV32I-NEXT:    ret
583;
584; RV64I-LABEL: fcvt_l_s:
585; RV64I:       # %bb.0:
586; RV64I-NEXT:    addi sp, sp, -16
587; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
588; RV64I-NEXT:    call __fixsfdi@plt
589; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
590; RV64I-NEXT:    addi sp, sp, 16
591; RV64I-NEXT:    ret
592  %1 = fptosi float %a to i64
593  ret i64 %1
594}
595
596define i64 @fcvt_l_s_sat(float %a) nounwind {
597; RV32IF-LABEL: fcvt_l_s_sat:
598; RV32IF:       # %bb.0: # %start
599; RV32IF-NEXT:    addi sp, sp, -16
600; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
601; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
602; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
603; RV32IF-NEXT:    lui a0, %hi(.LCPI12_0)
604; RV32IF-NEXT:    flw ft0, %lo(.LCPI12_0)(a0)
605; RV32IF-NEXT:    fmv.s fs0, fa0
606; RV32IF-NEXT:    fle.s s0, ft0, fa0
607; RV32IF-NEXT:    call __fixsfdi@plt
608; RV32IF-NEXT:    mv a2, a0
609; RV32IF-NEXT:    bnez s0, .LBB12_2
610; RV32IF-NEXT:  # %bb.1: # %start
611; RV32IF-NEXT:    li a2, 0
612; RV32IF-NEXT:  .LBB12_2: # %start
613; RV32IF-NEXT:    lui a0, %hi(.LCPI12_1)
614; RV32IF-NEXT:    flw ft0, %lo(.LCPI12_1)(a0)
615; RV32IF-NEXT:    flt.s a3, ft0, fs0
616; RV32IF-NEXT:    li a0, -1
617; RV32IF-NEXT:    beqz a3, .LBB12_9
618; RV32IF-NEXT:  # %bb.3: # %start
619; RV32IF-NEXT:    feq.s a2, fs0, fs0
620; RV32IF-NEXT:    beqz a2, .LBB12_10
621; RV32IF-NEXT:  .LBB12_4: # %start
622; RV32IF-NEXT:    lui a4, 524288
623; RV32IF-NEXT:    beqz s0, .LBB12_11
624; RV32IF-NEXT:  .LBB12_5: # %start
625; RV32IF-NEXT:    bnez a3, .LBB12_12
626; RV32IF-NEXT:  .LBB12_6: # %start
627; RV32IF-NEXT:    bnez a2, .LBB12_8
628; RV32IF-NEXT:  .LBB12_7: # %start
629; RV32IF-NEXT:    li a1, 0
630; RV32IF-NEXT:  .LBB12_8: # %start
631; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
632; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
633; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
634; RV32IF-NEXT:    addi sp, sp, 16
635; RV32IF-NEXT:    ret
636; RV32IF-NEXT:  .LBB12_9: # %start
637; RV32IF-NEXT:    mv a0, a2
638; RV32IF-NEXT:    feq.s a2, fs0, fs0
639; RV32IF-NEXT:    bnez a2, .LBB12_4
640; RV32IF-NEXT:  .LBB12_10: # %start
641; RV32IF-NEXT:    li a0, 0
642; RV32IF-NEXT:    lui a4, 524288
643; RV32IF-NEXT:    bnez s0, .LBB12_5
644; RV32IF-NEXT:  .LBB12_11: # %start
645; RV32IF-NEXT:    lui a1, 524288
646; RV32IF-NEXT:    beqz a3, .LBB12_6
647; RV32IF-NEXT:  .LBB12_12:
648; RV32IF-NEXT:    addi a1, a4, -1
649; RV32IF-NEXT:    beqz a2, .LBB12_7
650; RV32IF-NEXT:    j .LBB12_8
651;
652; RV64IF-LABEL: fcvt_l_s_sat:
653; RV64IF:       # %bb.0: # %start
654; RV64IF-NEXT:    feq.s a0, fa0, fa0
655; RV64IF-NEXT:    beqz a0, .LBB12_2
656; RV64IF-NEXT:  # %bb.1:
657; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
658; RV64IF-NEXT:  .LBB12_2: # %start
659; RV64IF-NEXT:    ret
660;
661; RV32I-LABEL: fcvt_l_s_sat:
662; RV32I:       # %bb.0: # %start
663; RV32I-NEXT:    addi sp, sp, -32
664; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
665; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
666; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
667; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
668; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
669; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
670; RV32I-NEXT:    sw s5, 4(sp) # 4-byte Folded Spill
671; RV32I-NEXT:    sw s6, 0(sp) # 4-byte Folded Spill
672; RV32I-NEXT:    mv s0, a0
673; RV32I-NEXT:    lui a1, 913408
674; RV32I-NEXT:    call __gesf2@plt
675; RV32I-NEXT:    mv s3, a0
676; RV32I-NEXT:    mv a0, s0
677; RV32I-NEXT:    call __fixsfdi@plt
678; RV32I-NEXT:    mv s2, a1
679; RV32I-NEXT:    li s1, 0
680; RV32I-NEXT:    li s5, 0
681; RV32I-NEXT:    bltz s3, .LBB12_2
682; RV32I-NEXT:  # %bb.1: # %start
683; RV32I-NEXT:    mv s5, a0
684; RV32I-NEXT:  .LBB12_2: # %start
685; RV32I-NEXT:    lui a0, 389120
686; RV32I-NEXT:    addi s4, a0, -1
687; RV32I-NEXT:    mv a0, s0
688; RV32I-NEXT:    mv a1, s4
689; RV32I-NEXT:    call __gtsf2@plt
690; RV32I-NEXT:    li s6, -1
691; RV32I-NEXT:    blt s1, a0, .LBB12_4
692; RV32I-NEXT:  # %bb.3: # %start
693; RV32I-NEXT:    mv s6, s5
694; RV32I-NEXT:  .LBB12_4: # %start
695; RV32I-NEXT:    mv a0, s0
696; RV32I-NEXT:    mv a1, s0
697; RV32I-NEXT:    call __unordsf2@plt
698; RV32I-NEXT:    mv s3, s1
699; RV32I-NEXT:    bne a0, s1, .LBB12_6
700; RV32I-NEXT:  # %bb.5: # %start
701; RV32I-NEXT:    mv s3, s6
702; RV32I-NEXT:  .LBB12_6: # %start
703; RV32I-NEXT:    lui a1, 913408
704; RV32I-NEXT:    mv a0, s0
705; RV32I-NEXT:    call __gesf2@plt
706; RV32I-NEXT:    lui s6, 524288
707; RV32I-NEXT:    lui s5, 524288
708; RV32I-NEXT:    blt a0, s1, .LBB12_8
709; RV32I-NEXT:  # %bb.7: # %start
710; RV32I-NEXT:    mv s5, s2
711; RV32I-NEXT:  .LBB12_8: # %start
712; RV32I-NEXT:    mv a0, s0
713; RV32I-NEXT:    mv a1, s4
714; RV32I-NEXT:    call __gtsf2@plt
715; RV32I-NEXT:    bge s1, a0, .LBB12_10
716; RV32I-NEXT:  # %bb.9:
717; RV32I-NEXT:    addi s5, s6, -1
718; RV32I-NEXT:  .LBB12_10: # %start
719; RV32I-NEXT:    mv a0, s0
720; RV32I-NEXT:    mv a1, s0
721; RV32I-NEXT:    call __unordsf2@plt
722; RV32I-NEXT:    bne a0, s1, .LBB12_12
723; RV32I-NEXT:  # %bb.11: # %start
724; RV32I-NEXT:    mv s1, s5
725; RV32I-NEXT:  .LBB12_12: # %start
726; RV32I-NEXT:    mv a0, s3
727; RV32I-NEXT:    mv a1, s1
728; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
729; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
730; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
731; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
732; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
733; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
734; RV32I-NEXT:    lw s5, 4(sp) # 4-byte Folded Reload
735; RV32I-NEXT:    lw s6, 0(sp) # 4-byte Folded Reload
736; RV32I-NEXT:    addi sp, sp, 32
737; RV32I-NEXT:    ret
738;
739; RV64I-LABEL: fcvt_l_s_sat:
740; RV64I:       # %bb.0: # %start
741; RV64I-NEXT:    addi sp, sp, -48
742; RV64I-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
743; RV64I-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
744; RV64I-NEXT:    sd s1, 24(sp) # 8-byte Folded Spill
745; RV64I-NEXT:    sd s2, 16(sp) # 8-byte Folded Spill
746; RV64I-NEXT:    sd s3, 8(sp) # 8-byte Folded Spill
747; RV64I-NEXT:    sd s4, 0(sp) # 8-byte Folded Spill
748; RV64I-NEXT:    mv s0, a0
749; RV64I-NEXT:    lui a1, 913408
750; RV64I-NEXT:    call __gesf2@plt
751; RV64I-NEXT:    mv s3, a0
752; RV64I-NEXT:    mv a0, s0
753; RV64I-NEXT:    call __fixsfdi@plt
754; RV64I-NEXT:    li s1, 0
755; RV64I-NEXT:    li s4, -1
756; RV64I-NEXT:    bltz s3, .LBB12_2
757; RV64I-NEXT:  # %bb.1: # %start
758; RV64I-NEXT:    mv s2, a0
759; RV64I-NEXT:    j .LBB12_3
760; RV64I-NEXT:  .LBB12_2:
761; RV64I-NEXT:    slli s2, s4, 63
762; RV64I-NEXT:  .LBB12_3: # %start
763; RV64I-NEXT:    lui a0, 389120
764; RV64I-NEXT:    addiw a1, a0, -1
765; RV64I-NEXT:    mv a0, s0
766; RV64I-NEXT:    call __gtsf2@plt
767; RV64I-NEXT:    bge s1, a0, .LBB12_5
768; RV64I-NEXT:  # %bb.4:
769; RV64I-NEXT:    srli s2, s4, 1
770; RV64I-NEXT:  .LBB12_5: # %start
771; RV64I-NEXT:    mv a0, s0
772; RV64I-NEXT:    mv a1, s0
773; RV64I-NEXT:    call __unordsf2@plt
774; RV64I-NEXT:    bne a0, s1, .LBB12_7
775; RV64I-NEXT:  # %bb.6: # %start
776; RV64I-NEXT:    mv s1, s2
777; RV64I-NEXT:  .LBB12_7: # %start
778; RV64I-NEXT:    mv a0, s1
779; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
780; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
781; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
782; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
783; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
784; RV64I-NEXT:    ld s4, 0(sp) # 8-byte Folded Reload
785; RV64I-NEXT:    addi sp, sp, 48
786; RV64I-NEXT:    ret
787start:
788  %0 = tail call i64 @llvm.fptosi.sat.i64.f32(float %a)
789  ret i64 %0
790}
791declare i64 @llvm.fptosi.sat.i64.f32(float)
792
793define i64 @fcvt_lu_s(float %a) nounwind {
794; RV32IF-LABEL: fcvt_lu_s:
795; RV32IF:       # %bb.0:
796; RV32IF-NEXT:    addi sp, sp, -16
797; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
798; RV32IF-NEXT:    call __fixunssfdi@plt
799; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
800; RV32IF-NEXT:    addi sp, sp, 16
801; RV32IF-NEXT:    ret
802;
803; RV64IF-LABEL: fcvt_lu_s:
804; RV64IF:       # %bb.0:
805; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
806; RV64IF-NEXT:    ret
807;
808; RV32I-LABEL: fcvt_lu_s:
809; RV32I:       # %bb.0:
810; RV32I-NEXT:    addi sp, sp, -16
811; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
812; RV32I-NEXT:    call __fixunssfdi@plt
813; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
814; RV32I-NEXT:    addi sp, sp, 16
815; RV32I-NEXT:    ret
816;
817; RV64I-LABEL: fcvt_lu_s:
818; RV64I:       # %bb.0:
819; RV64I-NEXT:    addi sp, sp, -16
820; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
821; RV64I-NEXT:    call __fixunssfdi@plt
822; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
823; RV64I-NEXT:    addi sp, sp, 16
824; RV64I-NEXT:    ret
825  %1 = fptoui float %a to i64
826  ret i64 %1
827}
828
829define i64 @fcvt_lu_s_sat(float %a) nounwind {
830; RV32IF-LABEL: fcvt_lu_s_sat:
831; RV32IF:       # %bb.0: # %start
832; RV32IF-NEXT:    addi sp, sp, -16
833; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
834; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
835; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
836; RV32IF-NEXT:    fmv.s fs0, fa0
837; RV32IF-NEXT:    fmv.w.x ft0, zero
838; RV32IF-NEXT:    fle.s s0, ft0, fa0
839; RV32IF-NEXT:    call __fixunssfdi@plt
840; RV32IF-NEXT:    mv a3, a0
841; RV32IF-NEXT:    bnez s0, .LBB14_2
842; RV32IF-NEXT:  # %bb.1: # %start
843; RV32IF-NEXT:    li a3, 0
844; RV32IF-NEXT:  .LBB14_2: # %start
845; RV32IF-NEXT:    lui a0, %hi(.LCPI14_0)
846; RV32IF-NEXT:    flw ft0, %lo(.LCPI14_0)(a0)
847; RV32IF-NEXT:    flt.s a4, ft0, fs0
848; RV32IF-NEXT:    li a2, -1
849; RV32IF-NEXT:    li a0, -1
850; RV32IF-NEXT:    beqz a4, .LBB14_7
851; RV32IF-NEXT:  # %bb.3: # %start
852; RV32IF-NEXT:    beqz s0, .LBB14_8
853; RV32IF-NEXT:  .LBB14_4: # %start
854; RV32IF-NEXT:    bnez a4, .LBB14_6
855; RV32IF-NEXT:  .LBB14_5: # %start
856; RV32IF-NEXT:    mv a2, a1
857; RV32IF-NEXT:  .LBB14_6: # %start
858; RV32IF-NEXT:    mv a1, a2
859; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
860; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
861; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
862; RV32IF-NEXT:    addi sp, sp, 16
863; RV32IF-NEXT:    ret
864; RV32IF-NEXT:  .LBB14_7: # %start
865; RV32IF-NEXT:    mv a0, a3
866; RV32IF-NEXT:    bnez s0, .LBB14_4
867; RV32IF-NEXT:  .LBB14_8: # %start
868; RV32IF-NEXT:    li a1, 0
869; RV32IF-NEXT:    beqz a4, .LBB14_5
870; RV32IF-NEXT:    j .LBB14_6
871;
872; RV64IF-LABEL: fcvt_lu_s_sat:
873; RV64IF:       # %bb.0: # %start
874; RV64IF-NEXT:    feq.s a0, fa0, fa0
875; RV64IF-NEXT:    beqz a0, .LBB14_2
876; RV64IF-NEXT:  # %bb.1:
877; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
878; RV64IF-NEXT:  .LBB14_2: # %start
879; RV64IF-NEXT:    ret
880;
881; RV32I-LABEL: fcvt_lu_s_sat:
882; RV32I:       # %bb.0: # %start
883; RV32I-NEXT:    addi sp, sp, -32
884; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
885; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
886; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
887; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
888; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
889; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
890; RV32I-NEXT:    sw s5, 4(sp) # 4-byte Folded Spill
891; RV32I-NEXT:    mv s0, a0
892; RV32I-NEXT:    li a1, 0
893; RV32I-NEXT:    call __gesf2@plt
894; RV32I-NEXT:    mv s2, a0
895; RV32I-NEXT:    mv a0, s0
896; RV32I-NEXT:    call __fixunssfdi@plt
897; RV32I-NEXT:    mv s1, a1
898; RV32I-NEXT:    li s5, 0
899; RV32I-NEXT:    bltz s2, .LBB14_2
900; RV32I-NEXT:  # %bb.1: # %start
901; RV32I-NEXT:    mv s5, a0
902; RV32I-NEXT:  .LBB14_2: # %start
903; RV32I-NEXT:    lui a0, 391168
904; RV32I-NEXT:    addi s4, a0, -1
905; RV32I-NEXT:    mv a0, s0
906; RV32I-NEXT:    mv a1, s4
907; RV32I-NEXT:    call __gtsf2@plt
908; RV32I-NEXT:    li s2, -1
909; RV32I-NEXT:    li s3, -1
910; RV32I-NEXT:    bgtz a0, .LBB14_4
911; RV32I-NEXT:  # %bb.3: # %start
912; RV32I-NEXT:    mv s3, s5
913; RV32I-NEXT:  .LBB14_4: # %start
914; RV32I-NEXT:    mv a0, s0
915; RV32I-NEXT:    li a1, 0
916; RV32I-NEXT:    call __gesf2@plt
917; RV32I-NEXT:    li s5, 0
918; RV32I-NEXT:    bltz a0, .LBB14_6
919; RV32I-NEXT:  # %bb.5: # %start
920; RV32I-NEXT:    mv s5, s1
921; RV32I-NEXT:  .LBB14_6: # %start
922; RV32I-NEXT:    mv a0, s0
923; RV32I-NEXT:    mv a1, s4
924; RV32I-NEXT:    call __gtsf2@plt
925; RV32I-NEXT:    bgtz a0, .LBB14_8
926; RV32I-NEXT:  # %bb.7: # %start
927; RV32I-NEXT:    mv s2, s5
928; RV32I-NEXT:  .LBB14_8: # %start
929; RV32I-NEXT:    mv a0, s3
930; RV32I-NEXT:    mv a1, s2
931; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
932; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
933; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
934; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
935; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
936; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
937; RV32I-NEXT:    lw s5, 4(sp) # 4-byte Folded Reload
938; RV32I-NEXT:    addi sp, sp, 32
939; RV32I-NEXT:    ret
940;
941; RV64I-LABEL: fcvt_lu_s_sat:
942; RV64I:       # %bb.0: # %start
943; RV64I-NEXT:    addi sp, sp, -32
944; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
945; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
946; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
947; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
948; RV64I-NEXT:    mv s0, a0
949; RV64I-NEXT:    li a1, 0
950; RV64I-NEXT:    call __gesf2@plt
951; RV64I-NEXT:    mv s1, a0
952; RV64I-NEXT:    mv a0, s0
953; RV64I-NEXT:    call __fixunssfdi@plt
954; RV64I-NEXT:    li s2, 0
955; RV64I-NEXT:    bltz s1, .LBB14_2
956; RV64I-NEXT:  # %bb.1: # %start
957; RV64I-NEXT:    mv s2, a0
958; RV64I-NEXT:  .LBB14_2: # %start
959; RV64I-NEXT:    lui a0, 391168
960; RV64I-NEXT:    addiw a1, a0, -1
961; RV64I-NEXT:    mv a0, s0
962; RV64I-NEXT:    call __gtsf2@plt
963; RV64I-NEXT:    mv a1, a0
964; RV64I-NEXT:    li a0, -1
965; RV64I-NEXT:    bgtz a1, .LBB14_4
966; RV64I-NEXT:  # %bb.3: # %start
967; RV64I-NEXT:    mv a0, s2
968; RV64I-NEXT:  .LBB14_4: # %start
969; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
970; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
971; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
972; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
973; RV64I-NEXT:    addi sp, sp, 32
974; RV64I-NEXT:    ret
975start:
976  %0 = tail call i64 @llvm.fptoui.sat.i64.f32(float %a)
977  ret i64 %0
978}
979declare i64 @llvm.fptoui.sat.i64.f32(float)
980
981define float @fcvt_s_l(i64 %a) nounwind {
982; RV32IF-LABEL: fcvt_s_l:
983; RV32IF:       # %bb.0:
984; RV32IF-NEXT:    addi sp, sp, -16
985; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
986; RV32IF-NEXT:    call __floatdisf@plt
987; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
988; RV32IF-NEXT:    addi sp, sp, 16
989; RV32IF-NEXT:    ret
990;
991; RV64IF-LABEL: fcvt_s_l:
992; RV64IF:       # %bb.0:
993; RV64IF-NEXT:    fcvt.s.l fa0, a0
994; RV64IF-NEXT:    ret
995;
996; RV32I-LABEL: fcvt_s_l:
997; RV32I:       # %bb.0:
998; RV32I-NEXT:    addi sp, sp, -16
999; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1000; RV32I-NEXT:    call __floatdisf@plt
1001; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1002; RV32I-NEXT:    addi sp, sp, 16
1003; RV32I-NEXT:    ret
1004;
1005; RV64I-LABEL: fcvt_s_l:
1006; RV64I:       # %bb.0:
1007; RV64I-NEXT:    addi sp, sp, -16
1008; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1009; RV64I-NEXT:    call __floatdisf@plt
1010; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1011; RV64I-NEXT:    addi sp, sp, 16
1012; RV64I-NEXT:    ret
1013  %1 = sitofp i64 %a to float
1014  ret float %1
1015}
1016
1017define float @fcvt_s_lu(i64 %a) nounwind {
1018; RV32IF-LABEL: fcvt_s_lu:
1019; RV32IF:       # %bb.0:
1020; RV32IF-NEXT:    addi sp, sp, -16
1021; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1022; RV32IF-NEXT:    call __floatundisf@plt
1023; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1024; RV32IF-NEXT:    addi sp, sp, 16
1025; RV32IF-NEXT:    ret
1026;
1027; RV64IF-LABEL: fcvt_s_lu:
1028; RV64IF:       # %bb.0:
1029; RV64IF-NEXT:    fcvt.s.lu fa0, a0
1030; RV64IF-NEXT:    ret
1031;
1032; RV32I-LABEL: fcvt_s_lu:
1033; RV32I:       # %bb.0:
1034; RV32I-NEXT:    addi sp, sp, -16
1035; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1036; RV32I-NEXT:    call __floatundisf@plt
1037; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1038; RV32I-NEXT:    addi sp, sp, 16
1039; RV32I-NEXT:    ret
1040;
1041; RV64I-LABEL: fcvt_s_lu:
1042; RV64I:       # %bb.0:
1043; RV64I-NEXT:    addi sp, sp, -16
1044; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1045; RV64I-NEXT:    call __floatundisf@plt
1046; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1047; RV64I-NEXT:    addi sp, sp, 16
1048; RV64I-NEXT:    ret
1049  %1 = uitofp i64 %a to float
1050  ret float %1
1051}
1052
1053define float @fcvt_s_w_i8(i8 signext %a) nounwind {
1054; RV32IF-LABEL: fcvt_s_w_i8:
1055; RV32IF:       # %bb.0:
1056; RV32IF-NEXT:    fcvt.s.w fa0, a0
1057; RV32IF-NEXT:    ret
1058;
1059; RV64IF-LABEL: fcvt_s_w_i8:
1060; RV64IF:       # %bb.0:
1061; RV64IF-NEXT:    fcvt.s.w fa0, a0
1062; RV64IF-NEXT:    ret
1063;
1064; RV32I-LABEL: fcvt_s_w_i8:
1065; RV32I:       # %bb.0:
1066; RV32I-NEXT:    addi sp, sp, -16
1067; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1068; RV32I-NEXT:    call __floatsisf@plt
1069; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1070; RV32I-NEXT:    addi sp, sp, 16
1071; RV32I-NEXT:    ret
1072;
1073; RV64I-LABEL: fcvt_s_w_i8:
1074; RV64I:       # %bb.0:
1075; RV64I-NEXT:    addi sp, sp, -16
1076; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1077; RV64I-NEXT:    call __floatsisf@plt
1078; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1079; RV64I-NEXT:    addi sp, sp, 16
1080; RV64I-NEXT:    ret
1081  %1 = sitofp i8 %a to float
1082  ret float %1
1083}
1084
1085define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind {
1086; RV32IF-LABEL: fcvt_s_wu_i8:
1087; RV32IF:       # %bb.0:
1088; RV32IF-NEXT:    fcvt.s.wu fa0, a0
1089; RV32IF-NEXT:    ret
1090;
1091; RV64IF-LABEL: fcvt_s_wu_i8:
1092; RV64IF:       # %bb.0:
1093; RV64IF-NEXT:    fcvt.s.wu fa0, a0
1094; RV64IF-NEXT:    ret
1095;
1096; RV32I-LABEL: fcvt_s_wu_i8:
1097; RV32I:       # %bb.0:
1098; RV32I-NEXT:    addi sp, sp, -16
1099; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1100; RV32I-NEXT:    call __floatunsisf@plt
1101; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1102; RV32I-NEXT:    addi sp, sp, 16
1103; RV32I-NEXT:    ret
1104;
1105; RV64I-LABEL: fcvt_s_wu_i8:
1106; RV64I:       # %bb.0:
1107; RV64I-NEXT:    addi sp, sp, -16
1108; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1109; RV64I-NEXT:    call __floatunsisf@plt
1110; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1111; RV64I-NEXT:    addi sp, sp, 16
1112; RV64I-NEXT:    ret
1113  %1 = uitofp i8 %a to float
1114  ret float %1
1115}
1116
1117define float @fcvt_s_w_i16(i16 signext %a) nounwind {
1118; RV32IF-LABEL: fcvt_s_w_i16:
1119; RV32IF:       # %bb.0:
1120; RV32IF-NEXT:    fcvt.s.w fa0, a0
1121; RV32IF-NEXT:    ret
1122;
1123; RV64IF-LABEL: fcvt_s_w_i16:
1124; RV64IF:       # %bb.0:
1125; RV64IF-NEXT:    fcvt.s.w fa0, a0
1126; RV64IF-NEXT:    ret
1127;
1128; RV32I-LABEL: fcvt_s_w_i16:
1129; RV32I:       # %bb.0:
1130; RV32I-NEXT:    addi sp, sp, -16
1131; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1132; RV32I-NEXT:    call __floatsisf@plt
1133; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1134; RV32I-NEXT:    addi sp, sp, 16
1135; RV32I-NEXT:    ret
1136;
1137; RV64I-LABEL: fcvt_s_w_i16:
1138; RV64I:       # %bb.0:
1139; RV64I-NEXT:    addi sp, sp, -16
1140; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1141; RV64I-NEXT:    call __floatsisf@plt
1142; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1143; RV64I-NEXT:    addi sp, sp, 16
1144; RV64I-NEXT:    ret
1145  %1 = sitofp i16 %a to float
1146  ret float %1
1147}
1148
1149define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind {
1150; RV32IF-LABEL: fcvt_s_wu_i16:
1151; RV32IF:       # %bb.0:
1152; RV32IF-NEXT:    fcvt.s.wu fa0, a0
1153; RV32IF-NEXT:    ret
1154;
1155; RV64IF-LABEL: fcvt_s_wu_i16:
1156; RV64IF:       # %bb.0:
1157; RV64IF-NEXT:    fcvt.s.wu fa0, a0
1158; RV64IF-NEXT:    ret
1159;
1160; RV32I-LABEL: fcvt_s_wu_i16:
1161; RV32I:       # %bb.0:
1162; RV32I-NEXT:    addi sp, sp, -16
1163; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1164; RV32I-NEXT:    call __floatunsisf@plt
1165; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1166; RV32I-NEXT:    addi sp, sp, 16
1167; RV32I-NEXT:    ret
1168;
1169; RV64I-LABEL: fcvt_s_wu_i16:
1170; RV64I:       # %bb.0:
1171; RV64I-NEXT:    addi sp, sp, -16
1172; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1173; RV64I-NEXT:    call __floatunsisf@plt
1174; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1175; RV64I-NEXT:    addi sp, sp, 16
1176; RV64I-NEXT:    ret
1177  %1 = uitofp i16 %a to float
1178  ret float %1
1179}
1180
1181; Make sure we select W version of addi on RV64.
1182define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, float* %1) nounwind {
1183; RV32IF-LABEL: fcvt_s_w_demanded_bits:
1184; RV32IF:       # %bb.0:
1185; RV32IF-NEXT:    addi a0, a0, 1
1186; RV32IF-NEXT:    fcvt.s.w ft0, a0
1187; RV32IF-NEXT:    fsw ft0, 0(a1)
1188; RV32IF-NEXT:    ret
1189;
1190; RV64IF-LABEL: fcvt_s_w_demanded_bits:
1191; RV64IF:       # %bb.0:
1192; RV64IF-NEXT:    addiw a0, a0, 1
1193; RV64IF-NEXT:    fcvt.s.w ft0, a0
1194; RV64IF-NEXT:    fsw ft0, 0(a1)
1195; RV64IF-NEXT:    ret
1196;
1197; RV32I-LABEL: fcvt_s_w_demanded_bits:
1198; RV32I:       # %bb.0:
1199; RV32I-NEXT:    addi sp, sp, -16
1200; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1201; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
1202; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
1203; RV32I-NEXT:    mv s0, a1
1204; RV32I-NEXT:    addi s1, a0, 1
1205; RV32I-NEXT:    mv a0, s1
1206; RV32I-NEXT:    call __floatsisf@plt
1207; RV32I-NEXT:    sw a0, 0(s0)
1208; RV32I-NEXT:    mv a0, s1
1209; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1210; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
1211; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
1212; RV32I-NEXT:    addi sp, sp, 16
1213; RV32I-NEXT:    ret
1214;
1215; RV64I-LABEL: fcvt_s_w_demanded_bits:
1216; RV64I:       # %bb.0:
1217; RV64I-NEXT:    addi sp, sp, -32
1218; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
1219; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
1220; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
1221; RV64I-NEXT:    mv s0, a1
1222; RV64I-NEXT:    addiw s1, a0, 1
1223; RV64I-NEXT:    mv a0, s1
1224; RV64I-NEXT:    call __floatsisf@plt
1225; RV64I-NEXT:    sw a0, 0(s0)
1226; RV64I-NEXT:    mv a0, s1
1227; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
1228; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
1229; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
1230; RV64I-NEXT:    addi sp, sp, 32
1231; RV64I-NEXT:    ret
1232  %3 = add i32 %0, 1
1233  %4 = sitofp i32 %3 to float
1234  store float %4, float* %1, align 4
1235  ret i32 %3
1236}
1237
1238; Make sure we select W version of addi on RV64.
1239define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, float* %1) nounwind {
1240; RV32IF-LABEL: fcvt_s_wu_demanded_bits:
1241; RV32IF:       # %bb.0:
1242; RV32IF-NEXT:    addi a0, a0, 1
1243; RV32IF-NEXT:    fcvt.s.wu ft0, a0
1244; RV32IF-NEXT:    fsw ft0, 0(a1)
1245; RV32IF-NEXT:    ret
1246;
1247; RV64IF-LABEL: fcvt_s_wu_demanded_bits:
1248; RV64IF:       # %bb.0:
1249; RV64IF-NEXT:    addiw a0, a0, 1
1250; RV64IF-NEXT:    fcvt.s.wu ft0, a0
1251; RV64IF-NEXT:    fsw ft0, 0(a1)
1252; RV64IF-NEXT:    ret
1253;
1254; RV32I-LABEL: fcvt_s_wu_demanded_bits:
1255; RV32I:       # %bb.0:
1256; RV32I-NEXT:    addi sp, sp, -16
1257; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1258; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
1259; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
1260; RV32I-NEXT:    mv s0, a1
1261; RV32I-NEXT:    addi s1, a0, 1
1262; RV32I-NEXT:    mv a0, s1
1263; RV32I-NEXT:    call __floatunsisf@plt
1264; RV32I-NEXT:    sw a0, 0(s0)
1265; RV32I-NEXT:    mv a0, s1
1266; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1267; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
1268; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
1269; RV32I-NEXT:    addi sp, sp, 16
1270; RV32I-NEXT:    ret
1271;
1272; RV64I-LABEL: fcvt_s_wu_demanded_bits:
1273; RV64I:       # %bb.0:
1274; RV64I-NEXT:    addi sp, sp, -32
1275; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
1276; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
1277; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
1278; RV64I-NEXT:    mv s0, a1
1279; RV64I-NEXT:    addiw s1, a0, 1
1280; RV64I-NEXT:    mv a0, s1
1281; RV64I-NEXT:    call __floatunsisf@plt
1282; RV64I-NEXT:    sw a0, 0(s0)
1283; RV64I-NEXT:    mv a0, s1
1284; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
1285; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
1286; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
1287; RV64I-NEXT:    addi sp, sp, 32
1288; RV64I-NEXT:    ret
1289  %3 = add i32 %0, 1
1290  %4 = uitofp i32 %3 to float
1291  store float %4, float* %1, align 4
1292  ret i32 %3
1293}
1294
1295define signext i16 @fcvt_w_s_i16(float %a) nounwind {
1296; RV32IF-LABEL: fcvt_w_s_i16:
1297; RV32IF:       # %bb.0:
1298; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
1299; RV32IF-NEXT:    ret
1300;
1301; RV64IF-LABEL: fcvt_w_s_i16:
1302; RV64IF:       # %bb.0:
1303; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
1304; RV64IF-NEXT:    ret
1305;
1306; RV32I-LABEL: fcvt_w_s_i16:
1307; RV32I:       # %bb.0:
1308; RV32I-NEXT:    addi sp, sp, -16
1309; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1310; RV32I-NEXT:    call __fixsfsi@plt
1311; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1312; RV32I-NEXT:    addi sp, sp, 16
1313; RV32I-NEXT:    ret
1314;
1315; RV64I-LABEL: fcvt_w_s_i16:
1316; RV64I:       # %bb.0:
1317; RV64I-NEXT:    addi sp, sp, -16
1318; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1319; RV64I-NEXT:    call __fixsfdi@plt
1320; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1321; RV64I-NEXT:    addi sp, sp, 16
1322; RV64I-NEXT:    ret
1323  %1 = fptosi float %a to i16
1324  ret i16 %1
1325}
1326
1327define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
1328; RV32IF-LABEL: fcvt_w_s_sat_i16:
1329; RV32IF:       # %bb.0: # %start
1330; RV32IF-NEXT:    feq.s a0, fa0, fa0
1331; RV32IF-NEXT:    beqz a0, .LBB24_2
1332; RV32IF-NEXT:  # %bb.1:
1333; RV32IF-NEXT:    lui a0, %hi(.LCPI24_0)
1334; RV32IF-NEXT:    flw ft0, %lo(.LCPI24_0)(a0)
1335; RV32IF-NEXT:    lui a0, %hi(.LCPI24_1)
1336; RV32IF-NEXT:    flw ft1, %lo(.LCPI24_1)(a0)
1337; RV32IF-NEXT:    fmax.s ft0, fa0, ft0
1338; RV32IF-NEXT:    fmin.s ft0, ft0, ft1
1339; RV32IF-NEXT:    fcvt.w.s a0, ft0, rtz
1340; RV32IF-NEXT:  .LBB24_2: # %start
1341; RV32IF-NEXT:    ret
1342;
1343; RV64IF-LABEL: fcvt_w_s_sat_i16:
1344; RV64IF:       # %bb.0: # %start
1345; RV64IF-NEXT:    feq.s a0, fa0, fa0
1346; RV64IF-NEXT:    beqz a0, .LBB24_2
1347; RV64IF-NEXT:  # %bb.1:
1348; RV64IF-NEXT:    lui a0, %hi(.LCPI24_0)
1349; RV64IF-NEXT:    flw ft0, %lo(.LCPI24_0)(a0)
1350; RV64IF-NEXT:    lui a0, %hi(.LCPI24_1)
1351; RV64IF-NEXT:    flw ft1, %lo(.LCPI24_1)(a0)
1352; RV64IF-NEXT:    fmax.s ft0, fa0, ft0
1353; RV64IF-NEXT:    fmin.s ft0, ft0, ft1
1354; RV64IF-NEXT:    fcvt.l.s a0, ft0, rtz
1355; RV64IF-NEXT:  .LBB24_2: # %start
1356; RV64IF-NEXT:    ret
1357;
1358; RV32I-LABEL: fcvt_w_s_sat_i16:
1359; RV32I:       # %bb.0: # %start
1360; RV32I-NEXT:    addi sp, sp, -32
1361; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
1362; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
1363; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
1364; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
1365; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
1366; RV32I-NEXT:    mv s0, a0
1367; RV32I-NEXT:    lui a1, 815104
1368; RV32I-NEXT:    call __gesf2@plt
1369; RV32I-NEXT:    mv s1, a0
1370; RV32I-NEXT:    mv a0, s0
1371; RV32I-NEXT:    call __fixsfsi@plt
1372; RV32I-NEXT:    li s2, 0
1373; RV32I-NEXT:    lui s3, 1048568
1374; RV32I-NEXT:    bltz s1, .LBB24_2
1375; RV32I-NEXT:  # %bb.1: # %start
1376; RV32I-NEXT:    mv s3, a0
1377; RV32I-NEXT:  .LBB24_2: # %start
1378; RV32I-NEXT:    lui a0, 290816
1379; RV32I-NEXT:    addi a1, a0, -512
1380; RV32I-NEXT:    mv a0, s0
1381; RV32I-NEXT:    call __gtsf2@plt
1382; RV32I-NEXT:    bge s2, a0, .LBB24_4
1383; RV32I-NEXT:  # %bb.3:
1384; RV32I-NEXT:    lui a0, 8
1385; RV32I-NEXT:    addi s3, a0, -1
1386; RV32I-NEXT:  .LBB24_4: # %start
1387; RV32I-NEXT:    mv a0, s0
1388; RV32I-NEXT:    mv a1, s0
1389; RV32I-NEXT:    call __unordsf2@plt
1390; RV32I-NEXT:    bne a0, s2, .LBB24_6
1391; RV32I-NEXT:  # %bb.5: # %start
1392; RV32I-NEXT:    mv s2, s3
1393; RV32I-NEXT:  .LBB24_6: # %start
1394; RV32I-NEXT:    slli a0, s2, 16
1395; RV32I-NEXT:    srai a0, a0, 16
1396; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
1397; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
1398; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
1399; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
1400; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
1401; RV32I-NEXT:    addi sp, sp, 32
1402; RV32I-NEXT:    ret
1403;
1404; RV64I-LABEL: fcvt_w_s_sat_i16:
1405; RV64I:       # %bb.0: # %start
1406; RV64I-NEXT:    addi sp, sp, -48
1407; RV64I-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
1408; RV64I-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
1409; RV64I-NEXT:    sd s1, 24(sp) # 8-byte Folded Spill
1410; RV64I-NEXT:    sd s2, 16(sp) # 8-byte Folded Spill
1411; RV64I-NEXT:    sd s3, 8(sp) # 8-byte Folded Spill
1412; RV64I-NEXT:    mv s0, a0
1413; RV64I-NEXT:    lui a1, 815104
1414; RV64I-NEXT:    call __gesf2@plt
1415; RV64I-NEXT:    mv s1, a0
1416; RV64I-NEXT:    mv a0, s0
1417; RV64I-NEXT:    call __fixsfdi@plt
1418; RV64I-NEXT:    li s2, 0
1419; RV64I-NEXT:    lui s3, 1048568
1420; RV64I-NEXT:    bltz s1, .LBB24_2
1421; RV64I-NEXT:  # %bb.1: # %start
1422; RV64I-NEXT:    mv s3, a0
1423; RV64I-NEXT:  .LBB24_2: # %start
1424; RV64I-NEXT:    lui a0, 290816
1425; RV64I-NEXT:    addiw a1, a0, -512
1426; RV64I-NEXT:    mv a0, s0
1427; RV64I-NEXT:    call __gtsf2@plt
1428; RV64I-NEXT:    bge s2, a0, .LBB24_4
1429; RV64I-NEXT:  # %bb.3:
1430; RV64I-NEXT:    lui a0, 8
1431; RV64I-NEXT:    addiw s3, a0, -1
1432; RV64I-NEXT:  .LBB24_4: # %start
1433; RV64I-NEXT:    mv a0, s0
1434; RV64I-NEXT:    mv a1, s0
1435; RV64I-NEXT:    call __unordsf2@plt
1436; RV64I-NEXT:    bne a0, s2, .LBB24_6
1437; RV64I-NEXT:  # %bb.5: # %start
1438; RV64I-NEXT:    mv s2, s3
1439; RV64I-NEXT:  .LBB24_6: # %start
1440; RV64I-NEXT:    slli a0, s2, 48
1441; RV64I-NEXT:    srai a0, a0, 48
1442; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
1443; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
1444; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
1445; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
1446; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
1447; RV64I-NEXT:    addi sp, sp, 48
1448; RV64I-NEXT:    ret
1449start:
1450  %0 = tail call i16 @llvm.fptosi.sat.i16.f32(float %a)
1451  ret i16 %0
1452}
1453declare i16 @llvm.fptosi.sat.i16.f32(float)
1454
1455define zeroext i16 @fcvt_wu_s_i16(float %a) nounwind {
1456; RV32IF-LABEL: fcvt_wu_s_i16:
1457; RV32IF:       # %bb.0:
1458; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
1459; RV32IF-NEXT:    ret
1460;
1461; RV64IF-LABEL: fcvt_wu_s_i16:
1462; RV64IF:       # %bb.0:
1463; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
1464; RV64IF-NEXT:    ret
1465;
1466; RV32I-LABEL: fcvt_wu_s_i16:
1467; RV32I:       # %bb.0:
1468; RV32I-NEXT:    addi sp, sp, -16
1469; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1470; RV32I-NEXT:    call __fixunssfsi@plt
1471; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1472; RV32I-NEXT:    addi sp, sp, 16
1473; RV32I-NEXT:    ret
1474;
1475; RV64I-LABEL: fcvt_wu_s_i16:
1476; RV64I:       # %bb.0:
1477; RV64I-NEXT:    addi sp, sp, -16
1478; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1479; RV64I-NEXT:    call __fixunssfdi@plt
1480; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1481; RV64I-NEXT:    addi sp, sp, 16
1482; RV64I-NEXT:    ret
1483  %1 = fptoui float %a to i16
1484  ret i16 %1
1485}
1486
1487define zeroext i16 @fcvt_wu_s_sat_i16(float %a) nounwind {
1488; RV32IF-LABEL: fcvt_wu_s_sat_i16:
1489; RV32IF:       # %bb.0: # %start
1490; RV32IF-NEXT:    lui a0, %hi(.LCPI26_0)
1491; RV32IF-NEXT:    flw ft0, %lo(.LCPI26_0)(a0)
1492; RV32IF-NEXT:    fmv.w.x ft1, zero
1493; RV32IF-NEXT:    fmax.s ft1, fa0, ft1
1494; RV32IF-NEXT:    fmin.s ft0, ft1, ft0
1495; RV32IF-NEXT:    fcvt.wu.s a0, ft0, rtz
1496; RV32IF-NEXT:    ret
1497;
1498; RV64IF-LABEL: fcvt_wu_s_sat_i16:
1499; RV64IF:       # %bb.0: # %start
1500; RV64IF-NEXT:    lui a0, %hi(.LCPI26_0)
1501; RV64IF-NEXT:    flw ft0, %lo(.LCPI26_0)(a0)
1502; RV64IF-NEXT:    fmv.w.x ft1, zero
1503; RV64IF-NEXT:    fmax.s ft1, fa0, ft1
1504; RV64IF-NEXT:    fmin.s ft0, ft1, ft0
1505; RV64IF-NEXT:    fcvt.lu.s a0, ft0, rtz
1506; RV64IF-NEXT:    ret
1507;
1508; RV32I-LABEL: fcvt_wu_s_sat_i16:
1509; RV32I:       # %bb.0: # %start
1510; RV32I-NEXT:    addi sp, sp, -16
1511; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1512; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
1513; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
1514; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
1515; RV32I-NEXT:    mv s0, a0
1516; RV32I-NEXT:    li a1, 0
1517; RV32I-NEXT:    call __gesf2@plt
1518; RV32I-NEXT:    mv s1, a0
1519; RV32I-NEXT:    mv a0, s0
1520; RV32I-NEXT:    call __fixunssfsi@plt
1521; RV32I-NEXT:    li s2, 0
1522; RV32I-NEXT:    bltz s1, .LBB26_2
1523; RV32I-NEXT:  # %bb.1: # %start
1524; RV32I-NEXT:    mv s2, a0
1525; RV32I-NEXT:  .LBB26_2: # %start
1526; RV32I-NEXT:    lui a0, 292864
1527; RV32I-NEXT:    addi a1, a0, -256
1528; RV32I-NEXT:    mv a0, s0
1529; RV32I-NEXT:    call __gtsf2@plt
1530; RV32I-NEXT:    lui a1, 16
1531; RV32I-NEXT:    addi a1, a1, -1
1532; RV32I-NEXT:    mv a2, a1
1533; RV32I-NEXT:    bgtz a0, .LBB26_4
1534; RV32I-NEXT:  # %bb.3: # %start
1535; RV32I-NEXT:    mv a2, s2
1536; RV32I-NEXT:  .LBB26_4: # %start
1537; RV32I-NEXT:    and a0, a2, a1
1538; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1539; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
1540; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
1541; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
1542; RV32I-NEXT:    addi sp, sp, 16
1543; RV32I-NEXT:    ret
1544;
1545; RV64I-LABEL: fcvt_wu_s_sat_i16:
1546; RV64I:       # %bb.0: # %start
1547; RV64I-NEXT:    addi sp, sp, -32
1548; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
1549; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
1550; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
1551; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
1552; RV64I-NEXT:    mv s0, a0
1553; RV64I-NEXT:    li a1, 0
1554; RV64I-NEXT:    call __gesf2@plt
1555; RV64I-NEXT:    mv s1, a0
1556; RV64I-NEXT:    mv a0, s0
1557; RV64I-NEXT:    call __fixunssfdi@plt
1558; RV64I-NEXT:    li s2, 0
1559; RV64I-NEXT:    bltz s1, .LBB26_2
1560; RV64I-NEXT:  # %bb.1: # %start
1561; RV64I-NEXT:    mv s2, a0
1562; RV64I-NEXT:  .LBB26_2: # %start
1563; RV64I-NEXT:    lui a0, 292864
1564; RV64I-NEXT:    addiw a1, a0, -256
1565; RV64I-NEXT:    mv a0, s0
1566; RV64I-NEXT:    call __gtsf2@plt
1567; RV64I-NEXT:    lui a1, 16
1568; RV64I-NEXT:    addiw a1, a1, -1
1569; RV64I-NEXT:    mv a2, a1
1570; RV64I-NEXT:    bgtz a0, .LBB26_4
1571; RV64I-NEXT:  # %bb.3: # %start
1572; RV64I-NEXT:    mv a2, s2
1573; RV64I-NEXT:  .LBB26_4: # %start
1574; RV64I-NEXT:    and a0, a2, a1
1575; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
1576; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
1577; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
1578; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
1579; RV64I-NEXT:    addi sp, sp, 32
1580; RV64I-NEXT:    ret
1581start:
1582  %0 = tail call i16 @llvm.fptoui.sat.i16.f32(float %a)
1583  ret i16 %0
1584}
1585declare i16 @llvm.fptoui.sat.i16.f32(float)
1586
1587define signext i8 @fcvt_w_s_i8(float %a) nounwind {
1588; RV32IF-LABEL: fcvt_w_s_i8:
1589; RV32IF:       # %bb.0:
1590; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
1591; RV32IF-NEXT:    ret
1592;
1593; RV64IF-LABEL: fcvt_w_s_i8:
1594; RV64IF:       # %bb.0:
1595; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
1596; RV64IF-NEXT:    ret
1597;
1598; RV32I-LABEL: fcvt_w_s_i8:
1599; RV32I:       # %bb.0:
1600; RV32I-NEXT:    addi sp, sp, -16
1601; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1602; RV32I-NEXT:    call __fixsfsi@plt
1603; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1604; RV32I-NEXT:    addi sp, sp, 16
1605; RV32I-NEXT:    ret
1606;
1607; RV64I-LABEL: fcvt_w_s_i8:
1608; RV64I:       # %bb.0:
1609; RV64I-NEXT:    addi sp, sp, -16
1610; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1611; RV64I-NEXT:    call __fixsfdi@plt
1612; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1613; RV64I-NEXT:    addi sp, sp, 16
1614; RV64I-NEXT:    ret
1615  %1 = fptosi float %a to i8
1616  ret i8 %1
1617}
1618
1619define signext i8 @fcvt_w_s_sat_i8(float %a) nounwind {
1620; RV32IF-LABEL: fcvt_w_s_sat_i8:
1621; RV32IF:       # %bb.0: # %start
1622; RV32IF-NEXT:    feq.s a0, fa0, fa0
1623; RV32IF-NEXT:    beqz a0, .LBB28_2
1624; RV32IF-NEXT:  # %bb.1:
1625; RV32IF-NEXT:    lui a0, %hi(.LCPI28_0)
1626; RV32IF-NEXT:    flw ft0, %lo(.LCPI28_0)(a0)
1627; RV32IF-NEXT:    lui a0, %hi(.LCPI28_1)
1628; RV32IF-NEXT:    flw ft1, %lo(.LCPI28_1)(a0)
1629; RV32IF-NEXT:    fmax.s ft0, fa0, ft0
1630; RV32IF-NEXT:    fmin.s ft0, ft0, ft1
1631; RV32IF-NEXT:    fcvt.w.s a0, ft0, rtz
1632; RV32IF-NEXT:  .LBB28_2: # %start
1633; RV32IF-NEXT:    ret
1634;
1635; RV64IF-LABEL: fcvt_w_s_sat_i8:
1636; RV64IF:       # %bb.0: # %start
1637; RV64IF-NEXT:    feq.s a0, fa0, fa0
1638; RV64IF-NEXT:    beqz a0, .LBB28_2
1639; RV64IF-NEXT:  # %bb.1:
1640; RV64IF-NEXT:    lui a0, %hi(.LCPI28_0)
1641; RV64IF-NEXT:    flw ft0, %lo(.LCPI28_0)(a0)
1642; RV64IF-NEXT:    lui a0, %hi(.LCPI28_1)
1643; RV64IF-NEXT:    flw ft1, %lo(.LCPI28_1)(a0)
1644; RV64IF-NEXT:    fmax.s ft0, fa0, ft0
1645; RV64IF-NEXT:    fmin.s ft0, ft0, ft1
1646; RV64IF-NEXT:    fcvt.l.s a0, ft0, rtz
1647; RV64IF-NEXT:  .LBB28_2: # %start
1648; RV64IF-NEXT:    ret
1649;
1650; RV32I-LABEL: fcvt_w_s_sat_i8:
1651; RV32I:       # %bb.0: # %start
1652; RV32I-NEXT:    addi sp, sp, -32
1653; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
1654; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
1655; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
1656; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
1657; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
1658; RV32I-NEXT:    mv s0, a0
1659; RV32I-NEXT:    lui a1, 798720
1660; RV32I-NEXT:    call __gesf2@plt
1661; RV32I-NEXT:    mv s1, a0
1662; RV32I-NEXT:    mv a0, s0
1663; RV32I-NEXT:    call __fixsfsi@plt
1664; RV32I-NEXT:    li s2, 0
1665; RV32I-NEXT:    li s3, -128
1666; RV32I-NEXT:    bltz s1, .LBB28_2
1667; RV32I-NEXT:  # %bb.1: # %start
1668; RV32I-NEXT:    mv s3, a0
1669; RV32I-NEXT:  .LBB28_2: # %start
1670; RV32I-NEXT:    lui a1, 274400
1671; RV32I-NEXT:    mv a0, s0
1672; RV32I-NEXT:    call __gtsf2@plt
1673; RV32I-NEXT:    li s1, 127
1674; RV32I-NEXT:    blt s2, a0, .LBB28_4
1675; RV32I-NEXT:  # %bb.3: # %start
1676; RV32I-NEXT:    mv s1, s3
1677; RV32I-NEXT:  .LBB28_4: # %start
1678; RV32I-NEXT:    mv a0, s0
1679; RV32I-NEXT:    mv a1, s0
1680; RV32I-NEXT:    call __unordsf2@plt
1681; RV32I-NEXT:    bne a0, s2, .LBB28_6
1682; RV32I-NEXT:  # %bb.5: # %start
1683; RV32I-NEXT:    mv s2, s1
1684; RV32I-NEXT:  .LBB28_6: # %start
1685; RV32I-NEXT:    slli a0, s2, 24
1686; RV32I-NEXT:    srai a0, a0, 24
1687; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
1688; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
1689; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
1690; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
1691; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
1692; RV32I-NEXT:    addi sp, sp, 32
1693; RV32I-NEXT:    ret
1694;
1695; RV64I-LABEL: fcvt_w_s_sat_i8:
1696; RV64I:       # %bb.0: # %start
1697; RV64I-NEXT:    addi sp, sp, -48
1698; RV64I-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
1699; RV64I-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
1700; RV64I-NEXT:    sd s1, 24(sp) # 8-byte Folded Spill
1701; RV64I-NEXT:    sd s2, 16(sp) # 8-byte Folded Spill
1702; RV64I-NEXT:    sd s3, 8(sp) # 8-byte Folded Spill
1703; RV64I-NEXT:    mv s0, a0
1704; RV64I-NEXT:    lui a1, 798720
1705; RV64I-NEXT:    call __gesf2@plt
1706; RV64I-NEXT:    mv s1, a0
1707; RV64I-NEXT:    mv a0, s0
1708; RV64I-NEXT:    call __fixsfdi@plt
1709; RV64I-NEXT:    li s2, 0
1710; RV64I-NEXT:    li s3, -128
1711; RV64I-NEXT:    bltz s1, .LBB28_2
1712; RV64I-NEXT:  # %bb.1: # %start
1713; RV64I-NEXT:    mv s3, a0
1714; RV64I-NEXT:  .LBB28_2: # %start
1715; RV64I-NEXT:    lui a1, 274400
1716; RV64I-NEXT:    mv a0, s0
1717; RV64I-NEXT:    call __gtsf2@plt
1718; RV64I-NEXT:    li s1, 127
1719; RV64I-NEXT:    blt s2, a0, .LBB28_4
1720; RV64I-NEXT:  # %bb.3: # %start
1721; RV64I-NEXT:    mv s1, s3
1722; RV64I-NEXT:  .LBB28_4: # %start
1723; RV64I-NEXT:    mv a0, s0
1724; RV64I-NEXT:    mv a1, s0
1725; RV64I-NEXT:    call __unordsf2@plt
1726; RV64I-NEXT:    bne a0, s2, .LBB28_6
1727; RV64I-NEXT:  # %bb.5: # %start
1728; RV64I-NEXT:    mv s2, s1
1729; RV64I-NEXT:  .LBB28_6: # %start
1730; RV64I-NEXT:    slli a0, s2, 56
1731; RV64I-NEXT:    srai a0, a0, 56
1732; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
1733; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
1734; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
1735; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
1736; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
1737; RV64I-NEXT:    addi sp, sp, 48
1738; RV64I-NEXT:    ret
1739start:
1740  %0 = tail call i8 @llvm.fptosi.sat.i8.f32(float %a)
1741  ret i8 %0
1742}
1743declare i8 @llvm.fptosi.sat.i8.f32(float)
1744
1745define zeroext i8 @fcvt_wu_s_i8(float %a) nounwind {
1746; RV32IF-LABEL: fcvt_wu_s_i8:
1747; RV32IF:       # %bb.0:
1748; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
1749; RV32IF-NEXT:    ret
1750;
1751; RV64IF-LABEL: fcvt_wu_s_i8:
1752; RV64IF:       # %bb.0:
1753; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
1754; RV64IF-NEXT:    ret
1755;
1756; RV32I-LABEL: fcvt_wu_s_i8:
1757; RV32I:       # %bb.0:
1758; RV32I-NEXT:    addi sp, sp, -16
1759; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1760; RV32I-NEXT:    call __fixunssfsi@plt
1761; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1762; RV32I-NEXT:    addi sp, sp, 16
1763; RV32I-NEXT:    ret
1764;
1765; RV64I-LABEL: fcvt_wu_s_i8:
1766; RV64I:       # %bb.0:
1767; RV64I-NEXT:    addi sp, sp, -16
1768; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1769; RV64I-NEXT:    call __fixunssfdi@plt
1770; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1771; RV64I-NEXT:    addi sp, sp, 16
1772; RV64I-NEXT:    ret
1773  %1 = fptoui float %a to i8
1774  ret i8 %1
1775}
1776
1777define zeroext i8 @fcvt_wu_s_sat_i8(float %a) nounwind {
1778; RV32IF-LABEL: fcvt_wu_s_sat_i8:
1779; RV32IF:       # %bb.0: # %start
1780; RV32IF-NEXT:    lui a0, %hi(.LCPI30_0)
1781; RV32IF-NEXT:    flw ft0, %lo(.LCPI30_0)(a0)
1782; RV32IF-NEXT:    fmv.w.x ft1, zero
1783; RV32IF-NEXT:    fmax.s ft1, fa0, ft1
1784; RV32IF-NEXT:    fmin.s ft0, ft1, ft0
1785; RV32IF-NEXT:    fcvt.wu.s a0, ft0, rtz
1786; RV32IF-NEXT:    ret
1787;
1788; RV64IF-LABEL: fcvt_wu_s_sat_i8:
1789; RV64IF:       # %bb.0: # %start
1790; RV64IF-NEXT:    lui a0, %hi(.LCPI30_0)
1791; RV64IF-NEXT:    flw ft0, %lo(.LCPI30_0)(a0)
1792; RV64IF-NEXT:    fmv.w.x ft1, zero
1793; RV64IF-NEXT:    fmax.s ft1, fa0, ft1
1794; RV64IF-NEXT:    fmin.s ft0, ft1, ft0
1795; RV64IF-NEXT:    fcvt.lu.s a0, ft0, rtz
1796; RV64IF-NEXT:    ret
1797;
1798; RV32I-LABEL: fcvt_wu_s_sat_i8:
1799; RV32I:       # %bb.0: # %start
1800; RV32I-NEXT:    addi sp, sp, -16
1801; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1802; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
1803; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
1804; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
1805; RV32I-NEXT:    mv s0, a0
1806; RV32I-NEXT:    li a1, 0
1807; RV32I-NEXT:    call __gesf2@plt
1808; RV32I-NEXT:    mv s1, a0
1809; RV32I-NEXT:    mv a0, s0
1810; RV32I-NEXT:    call __fixunssfsi@plt
1811; RV32I-NEXT:    li s2, 0
1812; RV32I-NEXT:    bltz s1, .LBB30_2
1813; RV32I-NEXT:  # %bb.1: # %start
1814; RV32I-NEXT:    mv s2, a0
1815; RV32I-NEXT:  .LBB30_2: # %start
1816; RV32I-NEXT:    lui a1, 276464
1817; RV32I-NEXT:    mv a0, s0
1818; RV32I-NEXT:    call __gtsf2@plt
1819; RV32I-NEXT:    li a1, 255
1820; RV32I-NEXT:    bgtz a0, .LBB30_4
1821; RV32I-NEXT:  # %bb.3: # %start
1822; RV32I-NEXT:    mv a1, s2
1823; RV32I-NEXT:  .LBB30_4: # %start
1824; RV32I-NEXT:    andi a0, a1, 255
1825; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1826; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
1827; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
1828; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
1829; RV32I-NEXT:    addi sp, sp, 16
1830; RV32I-NEXT:    ret
1831;
1832; RV64I-LABEL: fcvt_wu_s_sat_i8:
1833; RV64I:       # %bb.0: # %start
1834; RV64I-NEXT:    addi sp, sp, -32
1835; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
1836; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
1837; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
1838; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
1839; RV64I-NEXT:    mv s0, a0
1840; RV64I-NEXT:    li a1, 0
1841; RV64I-NEXT:    call __gesf2@plt
1842; RV64I-NEXT:    mv s1, a0
1843; RV64I-NEXT:    mv a0, s0
1844; RV64I-NEXT:    call __fixunssfdi@plt
1845; RV64I-NEXT:    li s2, 0
1846; RV64I-NEXT:    bltz s1, .LBB30_2
1847; RV64I-NEXT:  # %bb.1: # %start
1848; RV64I-NEXT:    mv s2, a0
1849; RV64I-NEXT:  .LBB30_2: # %start
1850; RV64I-NEXT:    lui a1, 276464
1851; RV64I-NEXT:    mv a0, s0
1852; RV64I-NEXT:    call __gtsf2@plt
1853; RV64I-NEXT:    li a1, 255
1854; RV64I-NEXT:    bgtz a0, .LBB30_4
1855; RV64I-NEXT:  # %bb.3: # %start
1856; RV64I-NEXT:    mv a1, s2
1857; RV64I-NEXT:  .LBB30_4: # %start
1858; RV64I-NEXT:    andi a0, a1, 255
1859; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
1860; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
1861; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
1862; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
1863; RV64I-NEXT:    addi sp, sp, 32
1864; RV64I-NEXT:    ret
1865start:
1866  %0 = tail call i8 @llvm.fptoui.sat.i8.f32(float %a)
1867  ret i8 %0
1868}
1869declare i8 @llvm.fptoui.sat.i8.f32(float)
1870