1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
3; RUN:   -target-abi=ilp32d | FileCheck -check-prefix=RV32IFD %s
4; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
5; RUN:   -target-abi=lp64d | FileCheck -check-prefix=RV64IFD %s
6
7define signext i8 @test_floor_si8(double %x) {
8; RV32IFD-LABEL: test_floor_si8:
9; RV32IFD:       # %bb.0:
10; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rdn
11; RV32IFD-NEXT:    ret
12;
13; RV64IFD-LABEL: test_floor_si8:
14; RV64IFD:       # %bb.0:
15; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rdn
16; RV64IFD-NEXT:    ret
17  %a = call double @llvm.floor.f64(double %x)
18  %b = fptosi double %a to i8
19  ret i8 %b
20}
21
22define signext i16 @test_floor_si16(double %x) {
23; RV32IFD-LABEL: test_floor_si16:
24; RV32IFD:       # %bb.0:
25; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rdn
26; RV32IFD-NEXT:    ret
27;
28; RV64IFD-LABEL: test_floor_si16:
29; RV64IFD:       # %bb.0:
30; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rdn
31; RV64IFD-NEXT:    ret
32  %a = call double @llvm.floor.f64(double %x)
33  %b = fptosi double %a to i16
34  ret i16 %b
35}
36
37define signext i32 @test_floor_si32(double %x) {
38; RV32IFD-LABEL: test_floor_si32:
39; RV32IFD:       # %bb.0:
40; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rdn
41; RV32IFD-NEXT:    ret
42;
43; RV64IFD-LABEL: test_floor_si32:
44; RV64IFD:       # %bb.0:
45; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rdn
46; RV64IFD-NEXT:    ret
47  %a = call double @llvm.floor.f64(double %x)
48  %b = fptosi double %a to i32
49  ret i32 %b
50}
51
52define i64 @test_floor_si64(double %x) {
53; RV32IFD-LABEL: test_floor_si64:
54; RV32IFD:       # %bb.0:
55; RV32IFD-NEXT:    addi sp, sp, -16
56; RV32IFD-NEXT:    .cfi_def_cfa_offset 16
57; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
58; RV32IFD-NEXT:    .cfi_offset ra, -4
59; RV32IFD-NEXT:    call floor@plt
60; RV32IFD-NEXT:    call __fixdfdi@plt
61; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
62; RV32IFD-NEXT:    addi sp, sp, 16
63; RV32IFD-NEXT:    ret
64;
65; RV64IFD-LABEL: test_floor_si64:
66; RV64IFD:       # %bb.0:
67; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rdn
68; RV64IFD-NEXT:    ret
69  %a = call double @llvm.floor.f64(double %x)
70  %b = fptosi double %a to i64
71  ret i64 %b
72}
73
74define zeroext i8 @test_floor_ui8(double %x) {
75; RV32IFD-LABEL: test_floor_ui8:
76; RV32IFD:       # %bb.0:
77; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rdn
78; RV32IFD-NEXT:    ret
79;
80; RV64IFD-LABEL: test_floor_ui8:
81; RV64IFD:       # %bb.0:
82; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rdn
83; RV64IFD-NEXT:    ret
84  %a = call double @llvm.floor.f64(double %x)
85  %b = fptoui double %a to i8
86  ret i8 %b
87}
88
89define zeroext i16 @test_floor_ui16(double %x) {
90; RV32IFD-LABEL: test_floor_ui16:
91; RV32IFD:       # %bb.0:
92; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rdn
93; RV32IFD-NEXT:    ret
94;
95; RV64IFD-LABEL: test_floor_ui16:
96; RV64IFD:       # %bb.0:
97; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rdn
98; RV64IFD-NEXT:    ret
99  %a = call double @llvm.floor.f64(double %x)
100  %b = fptoui double %a to i16
101  ret i16 %b
102}
103
104define signext i32 @test_floor_ui32(double %x) {
105; RV32IFD-LABEL: test_floor_ui32:
106; RV32IFD:       # %bb.0:
107; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rdn
108; RV32IFD-NEXT:    ret
109;
110; RV64IFD-LABEL: test_floor_ui32:
111; RV64IFD:       # %bb.0:
112; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rdn
113; RV64IFD-NEXT:    ret
114  %a = call double @llvm.floor.f64(double %x)
115  %b = fptoui double %a to i32
116  ret i32 %b
117}
118
119define i64 @test_floor_ui64(double %x) {
120; RV32IFD-LABEL: test_floor_ui64:
121; RV32IFD:       # %bb.0:
122; RV32IFD-NEXT:    addi sp, sp, -16
123; RV32IFD-NEXT:    .cfi_def_cfa_offset 16
124; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
125; RV32IFD-NEXT:    .cfi_offset ra, -4
126; RV32IFD-NEXT:    call floor@plt
127; RV32IFD-NEXT:    call __fixunsdfdi@plt
128; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
129; RV32IFD-NEXT:    addi sp, sp, 16
130; RV32IFD-NEXT:    ret
131;
132; RV64IFD-LABEL: test_floor_ui64:
133; RV64IFD:       # %bb.0:
134; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rdn
135; RV64IFD-NEXT:    ret
136  %a = call double @llvm.floor.f64(double %x)
137  %b = fptoui double %a to i64
138  ret i64 %b
139}
140
141define signext i8 @test_ceil_si8(double %x) {
142; RV32IFD-LABEL: test_ceil_si8:
143; RV32IFD:       # %bb.0:
144; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rup
145; RV32IFD-NEXT:    ret
146;
147; RV64IFD-LABEL: test_ceil_si8:
148; RV64IFD:       # %bb.0:
149; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rup
150; RV64IFD-NEXT:    ret
151  %a = call double @llvm.ceil.f64(double %x)
152  %b = fptosi double %a to i8
153  ret i8 %b
154}
155
156define signext i16 @test_ceil_si16(double %x) {
157; RV32IFD-LABEL: test_ceil_si16:
158; RV32IFD:       # %bb.0:
159; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rup
160; RV32IFD-NEXT:    ret
161;
162; RV64IFD-LABEL: test_ceil_si16:
163; RV64IFD:       # %bb.0:
164; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rup
165; RV64IFD-NEXT:    ret
166  %a = call double @llvm.ceil.f64(double %x)
167  %b = fptosi double %a to i16
168  ret i16 %b
169}
170
171define signext i32 @test_ceil_si32(double %x) {
172; RV32IFD-LABEL: test_ceil_si32:
173; RV32IFD:       # %bb.0:
174; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rup
175; RV32IFD-NEXT:    ret
176;
177; RV64IFD-LABEL: test_ceil_si32:
178; RV64IFD:       # %bb.0:
179; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rup
180; RV64IFD-NEXT:    ret
181  %a = call double @llvm.ceil.f64(double %x)
182  %b = fptosi double %a to i32
183  ret i32 %b
184}
185
186define i64 @test_ceil_si64(double %x) {
187; RV32IFD-LABEL: test_ceil_si64:
188; RV32IFD:       # %bb.0:
189; RV32IFD-NEXT:    addi sp, sp, -16
190; RV32IFD-NEXT:    .cfi_def_cfa_offset 16
191; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
192; RV32IFD-NEXT:    .cfi_offset ra, -4
193; RV32IFD-NEXT:    call ceil@plt
194; RV32IFD-NEXT:    call __fixdfdi@plt
195; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
196; RV32IFD-NEXT:    addi sp, sp, 16
197; RV32IFD-NEXT:    ret
198;
199; RV64IFD-LABEL: test_ceil_si64:
200; RV64IFD:       # %bb.0:
201; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rup
202; RV64IFD-NEXT:    ret
203  %a = call double @llvm.ceil.f64(double %x)
204  %b = fptosi double %a to i64
205  ret i64 %b
206}
207
208define zeroext i8 @test_ceil_ui8(double %x) {
209; RV32IFD-LABEL: test_ceil_ui8:
210; RV32IFD:       # %bb.0:
211; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rup
212; RV32IFD-NEXT:    ret
213;
214; RV64IFD-LABEL: test_ceil_ui8:
215; RV64IFD:       # %bb.0:
216; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rup
217; RV64IFD-NEXT:    ret
218  %a = call double @llvm.ceil.f64(double %x)
219  %b = fptoui double %a to i8
220  ret i8 %b
221}
222
223define zeroext i16 @test_ceil_ui16(double %x) {
224; RV32IFD-LABEL: test_ceil_ui16:
225; RV32IFD:       # %bb.0:
226; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rup
227; RV32IFD-NEXT:    ret
228;
229; RV64IFD-LABEL: test_ceil_ui16:
230; RV64IFD:       # %bb.0:
231; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rup
232; RV64IFD-NEXT:    ret
233  %a = call double @llvm.ceil.f64(double %x)
234  %b = fptoui double %a to i16
235  ret i16 %b
236}
237
238define signext i32 @test_ceil_ui32(double %x) {
239; RV32IFD-LABEL: test_ceil_ui32:
240; RV32IFD:       # %bb.0:
241; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rup
242; RV32IFD-NEXT:    ret
243;
244; RV64IFD-LABEL: test_ceil_ui32:
245; RV64IFD:       # %bb.0:
246; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rup
247; RV64IFD-NEXT:    ret
248  %a = call double @llvm.ceil.f64(double %x)
249  %b = fptoui double %a to i32
250  ret i32 %b
251}
252
253define i64 @test_ceil_ui64(double %x) {
254; RV32IFD-LABEL: test_ceil_ui64:
255; RV32IFD:       # %bb.0:
256; RV32IFD-NEXT:    addi sp, sp, -16
257; RV32IFD-NEXT:    .cfi_def_cfa_offset 16
258; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
259; RV32IFD-NEXT:    .cfi_offset ra, -4
260; RV32IFD-NEXT:    call ceil@plt
261; RV32IFD-NEXT:    call __fixunsdfdi@plt
262; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
263; RV32IFD-NEXT:    addi sp, sp, 16
264; RV32IFD-NEXT:    ret
265;
266; RV64IFD-LABEL: test_ceil_ui64:
267; RV64IFD:       # %bb.0:
268; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rup
269; RV64IFD-NEXT:    ret
270  %a = call double @llvm.ceil.f64(double %x)
271  %b = fptoui double %a to i64
272  ret i64 %b
273}
274
275define signext i8 @test_trunc_si8(double %x) {
276; RV32IFD-LABEL: test_trunc_si8:
277; RV32IFD:       # %bb.0:
278; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rtz
279; RV32IFD-NEXT:    ret
280;
281; RV64IFD-LABEL: test_trunc_si8:
282; RV64IFD:       # %bb.0:
283; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rtz
284; RV64IFD-NEXT:    ret
285  %a = call double @llvm.trunc.f64(double %x)
286  %b = fptosi double %a to i8
287  ret i8 %b
288}
289
290define signext i16 @test_trunc_si16(double %x) {
291; RV32IFD-LABEL: test_trunc_si16:
292; RV32IFD:       # %bb.0:
293; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rtz
294; RV32IFD-NEXT:    ret
295;
296; RV64IFD-LABEL: test_trunc_si16:
297; RV64IFD:       # %bb.0:
298; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rtz
299; RV64IFD-NEXT:    ret
300  %a = call double @llvm.trunc.f64(double %x)
301  %b = fptosi double %a to i16
302  ret i16 %b
303}
304
305define signext i32 @test_trunc_si32(double %x) {
306; RV32IFD-LABEL: test_trunc_si32:
307; RV32IFD:       # %bb.0:
308; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rtz
309; RV32IFD-NEXT:    ret
310;
311; RV64IFD-LABEL: test_trunc_si32:
312; RV64IFD:       # %bb.0:
313; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rtz
314; RV64IFD-NEXT:    ret
315  %a = call double @llvm.trunc.f64(double %x)
316  %b = fptosi double %a to i32
317  ret i32 %b
318}
319
320define i64 @test_trunc_si64(double %x) {
321; RV32IFD-LABEL: test_trunc_si64:
322; RV32IFD:       # %bb.0:
323; RV32IFD-NEXT:    addi sp, sp, -16
324; RV32IFD-NEXT:    .cfi_def_cfa_offset 16
325; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
326; RV32IFD-NEXT:    .cfi_offset ra, -4
327; RV32IFD-NEXT:    call trunc@plt
328; RV32IFD-NEXT:    call __fixdfdi@plt
329; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
330; RV32IFD-NEXT:    addi sp, sp, 16
331; RV32IFD-NEXT:    ret
332;
333; RV64IFD-LABEL: test_trunc_si64:
334; RV64IFD:       # %bb.0:
335; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rtz
336; RV64IFD-NEXT:    ret
337  %a = call double @llvm.trunc.f64(double %x)
338  %b = fptosi double %a to i64
339  ret i64 %b
340}
341
342define zeroext i8 @test_trunc_ui8(double %x) {
343; RV32IFD-LABEL: test_trunc_ui8:
344; RV32IFD:       # %bb.0:
345; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
346; RV32IFD-NEXT:    ret
347;
348; RV64IFD-LABEL: test_trunc_ui8:
349; RV64IFD:       # %bb.0:
350; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rtz
351; RV64IFD-NEXT:    ret
352  %a = call double @llvm.trunc.f64(double %x)
353  %b = fptoui double %a to i8
354  ret i8 %b
355}
356
357define zeroext i16 @test_trunc_ui16(double %x) {
358; RV32IFD-LABEL: test_trunc_ui16:
359; RV32IFD:       # %bb.0:
360; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
361; RV32IFD-NEXT:    ret
362;
363; RV64IFD-LABEL: test_trunc_ui16:
364; RV64IFD:       # %bb.0:
365; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rtz
366; RV64IFD-NEXT:    ret
367  %a = call double @llvm.trunc.f64(double %x)
368  %b = fptoui double %a to i16
369  ret i16 %b
370}
371
372define signext i32 @test_trunc_ui32(double %x) {
373; RV32IFD-LABEL: test_trunc_ui32:
374; RV32IFD:       # %bb.0:
375; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
376; RV32IFD-NEXT:    ret
377;
378; RV64IFD-LABEL: test_trunc_ui32:
379; RV64IFD:       # %bb.0:
380; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
381; RV64IFD-NEXT:    ret
382  %a = call double @llvm.trunc.f64(double %x)
383  %b = fptoui double %a to i32
384  ret i32 %b
385}
386
387define i64 @test_trunc_ui64(double %x) {
388; RV32IFD-LABEL: test_trunc_ui64:
389; RV32IFD:       # %bb.0:
390; RV32IFD-NEXT:    addi sp, sp, -16
391; RV32IFD-NEXT:    .cfi_def_cfa_offset 16
392; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
393; RV32IFD-NEXT:    .cfi_offset ra, -4
394; RV32IFD-NEXT:    call trunc@plt
395; RV32IFD-NEXT:    call __fixunsdfdi@plt
396; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
397; RV32IFD-NEXT:    addi sp, sp, 16
398; RV32IFD-NEXT:    ret
399;
400; RV64IFD-LABEL: test_trunc_ui64:
401; RV64IFD:       # %bb.0:
402; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rtz
403; RV64IFD-NEXT:    ret
404  %a = call double @llvm.trunc.f64(double %x)
405  %b = fptoui double %a to i64
406  ret i64 %b
407}
408
409define signext i8 @test_round_si8(double %x) {
410; RV32IFD-LABEL: test_round_si8:
411; RV32IFD:       # %bb.0:
412; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rmm
413; RV32IFD-NEXT:    ret
414;
415; RV64IFD-LABEL: test_round_si8:
416; RV64IFD:       # %bb.0:
417; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rmm
418; RV64IFD-NEXT:    ret
419  %a = call double @llvm.round.f64(double %x)
420  %b = fptosi double %a to i8
421  ret i8 %b
422}
423
424define signext i16 @test_round_si16(double %x) {
425; RV32IFD-LABEL: test_round_si16:
426; RV32IFD:       # %bb.0:
427; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rmm
428; RV32IFD-NEXT:    ret
429;
430; RV64IFD-LABEL: test_round_si16:
431; RV64IFD:       # %bb.0:
432; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rmm
433; RV64IFD-NEXT:    ret
434  %a = call double @llvm.round.f64(double %x)
435  %b = fptosi double %a to i16
436  ret i16 %b
437}
438
439define signext i32 @test_round_si32(double %x) {
440; RV32IFD-LABEL: test_round_si32:
441; RV32IFD:       # %bb.0:
442; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rmm
443; RV32IFD-NEXT:    ret
444;
445; RV64IFD-LABEL: test_round_si32:
446; RV64IFD:       # %bb.0:
447; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rmm
448; RV64IFD-NEXT:    ret
449  %a = call double @llvm.round.f64(double %x)
450  %b = fptosi double %a to i32
451  ret i32 %b
452}
453
454define i64 @test_round_si64(double %x) {
455; RV32IFD-LABEL: test_round_si64:
456; RV32IFD:       # %bb.0:
457; RV32IFD-NEXT:    addi sp, sp, -16
458; RV32IFD-NEXT:    .cfi_def_cfa_offset 16
459; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
460; RV32IFD-NEXT:    .cfi_offset ra, -4
461; RV32IFD-NEXT:    call round@plt
462; RV32IFD-NEXT:    call __fixdfdi@plt
463; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
464; RV32IFD-NEXT:    addi sp, sp, 16
465; RV32IFD-NEXT:    ret
466;
467; RV64IFD-LABEL: test_round_si64:
468; RV64IFD:       # %bb.0:
469; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rmm
470; RV64IFD-NEXT:    ret
471  %a = call double @llvm.round.f64(double %x)
472  %b = fptosi double %a to i64
473  ret i64 %b
474}
475
476define zeroext i8 @test_round_ui8(double %x) {
477; RV32IFD-LABEL: test_round_ui8:
478; RV32IFD:       # %bb.0:
479; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rmm
480; RV32IFD-NEXT:    ret
481;
482; RV64IFD-LABEL: test_round_ui8:
483; RV64IFD:       # %bb.0:
484; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rmm
485; RV64IFD-NEXT:    ret
486  %a = call double @llvm.round.f64(double %x)
487  %b = fptoui double %a to i8
488  ret i8 %b
489}
490
491define zeroext i16 @test_round_ui16(double %x) {
492; RV32IFD-LABEL: test_round_ui16:
493; RV32IFD:       # %bb.0:
494; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rmm
495; RV32IFD-NEXT:    ret
496;
497; RV64IFD-LABEL: test_round_ui16:
498; RV64IFD:       # %bb.0:
499; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rmm
500; RV64IFD-NEXT:    ret
501  %a = call double @llvm.round.f64(double %x)
502  %b = fptoui double %a to i16
503  ret i16 %b
504}
505
506define signext i32 @test_round_ui32(double %x) {
507; RV32IFD-LABEL: test_round_ui32:
508; RV32IFD:       # %bb.0:
509; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rmm
510; RV32IFD-NEXT:    ret
511;
512; RV64IFD-LABEL: test_round_ui32:
513; RV64IFD:       # %bb.0:
514; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rmm
515; RV64IFD-NEXT:    ret
516  %a = call double @llvm.round.f64(double %x)
517  %b = fptoui double %a to i32
518  ret i32 %b
519}
520
521define i64 @test_round_ui64(double %x) {
522; RV32IFD-LABEL: test_round_ui64:
523; RV32IFD:       # %bb.0:
524; RV32IFD-NEXT:    addi sp, sp, -16
525; RV32IFD-NEXT:    .cfi_def_cfa_offset 16
526; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
527; RV32IFD-NEXT:    .cfi_offset ra, -4
528; RV32IFD-NEXT:    call round@plt
529; RV32IFD-NEXT:    call __fixunsdfdi@plt
530; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
531; RV32IFD-NEXT:    addi sp, sp, 16
532; RV32IFD-NEXT:    ret
533;
534; RV64IFD-LABEL: test_round_ui64:
535; RV64IFD:       # %bb.0:
536; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rmm
537; RV64IFD-NEXT:    ret
538  %a = call double @llvm.round.f64(double %x)
539  %b = fptoui double %a to i64
540  ret i64 %b
541}
542
543define signext i8 @test_roundeven_si8(double %x) {
544; RV32IFD-LABEL: test_roundeven_si8:
545; RV32IFD:       # %bb.0:
546; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rne
547; RV32IFD-NEXT:    ret
548;
549; RV64IFD-LABEL: test_roundeven_si8:
550; RV64IFD:       # %bb.0:
551; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rne
552; RV64IFD-NEXT:    ret
553  %a = call double @llvm.roundeven.f64(double %x)
554  %b = fptosi double %a to i8
555  ret i8 %b
556}
557
558define signext i16 @test_roundeven_si16(double %x) {
559; RV32IFD-LABEL: test_roundeven_si16:
560; RV32IFD:       # %bb.0:
561; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rne
562; RV32IFD-NEXT:    ret
563;
564; RV64IFD-LABEL: test_roundeven_si16:
565; RV64IFD:       # %bb.0:
566; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rne
567; RV64IFD-NEXT:    ret
568  %a = call double @llvm.roundeven.f64(double %x)
569  %b = fptosi double %a to i16
570  ret i16 %b
571}
572
573define signext i32 @test_roundeven_si32(double %x) {
574; RV32IFD-LABEL: test_roundeven_si32:
575; RV32IFD:       # %bb.0:
576; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rne
577; RV32IFD-NEXT:    ret
578;
579; RV64IFD-LABEL: test_roundeven_si32:
580; RV64IFD:       # %bb.0:
581; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rne
582; RV64IFD-NEXT:    ret
583  %a = call double @llvm.roundeven.f64(double %x)
584  %b = fptosi double %a to i32
585  ret i32 %b
586}
587
588define i64 @test_roundeven_si64(double %x) {
589; RV32IFD-LABEL: test_roundeven_si64:
590; RV32IFD:       # %bb.0:
591; RV32IFD-NEXT:    addi sp, sp, -16
592; RV32IFD-NEXT:    .cfi_def_cfa_offset 16
593; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
594; RV32IFD-NEXT:    .cfi_offset ra, -4
595; RV32IFD-NEXT:    call roundeven@plt
596; RV32IFD-NEXT:    call __fixdfdi@plt
597; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
598; RV32IFD-NEXT:    addi sp, sp, 16
599; RV32IFD-NEXT:    ret
600;
601; RV64IFD-LABEL: test_roundeven_si64:
602; RV64IFD:       # %bb.0:
603; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rne
604; RV64IFD-NEXT:    ret
605  %a = call double @llvm.roundeven.f64(double %x)
606  %b = fptosi double %a to i64
607  ret i64 %b
608}
609
610define zeroext i8 @test_roundeven_ui8(double %x) {
611; RV32IFD-LABEL: test_roundeven_ui8:
612; RV32IFD:       # %bb.0:
613; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rne
614; RV32IFD-NEXT:    ret
615;
616; RV64IFD-LABEL: test_roundeven_ui8:
617; RV64IFD:       # %bb.0:
618; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rne
619; RV64IFD-NEXT:    ret
620  %a = call double @llvm.roundeven.f64(double %x)
621  %b = fptoui double %a to i8
622  ret i8 %b
623}
624
625define zeroext i16 @test_roundeven_ui16(double %x) {
626; RV32IFD-LABEL: test_roundeven_ui16:
627; RV32IFD:       # %bb.0:
628; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rne
629; RV32IFD-NEXT:    ret
630;
631; RV64IFD-LABEL: test_roundeven_ui16:
632; RV64IFD:       # %bb.0:
633; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rne
634; RV64IFD-NEXT:    ret
635  %a = call double @llvm.roundeven.f64(double %x)
636  %b = fptoui double %a to i16
637  ret i16 %b
638}
639
640define signext i32 @test_roundeven_ui32(double %x) {
641; RV32IFD-LABEL: test_roundeven_ui32:
642; RV32IFD:       # %bb.0:
643; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rne
644; RV32IFD-NEXT:    ret
645;
646; RV64IFD-LABEL: test_roundeven_ui32:
647; RV64IFD:       # %bb.0:
648; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rne
649; RV64IFD-NEXT:    ret
650  %a = call double @llvm.roundeven.f64(double %x)
651  %b = fptoui double %a to i32
652  ret i32 %b
653}
654
655define i64 @test_roundeven_ui64(double %x) {
656; RV32IFD-LABEL: test_roundeven_ui64:
657; RV32IFD:       # %bb.0:
658; RV32IFD-NEXT:    addi sp, sp, -16
659; RV32IFD-NEXT:    .cfi_def_cfa_offset 16
660; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
661; RV32IFD-NEXT:    .cfi_offset ra, -4
662; RV32IFD-NEXT:    call roundeven@plt
663; RV32IFD-NEXT:    call __fixunsdfdi@plt
664; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
665; RV32IFD-NEXT:    addi sp, sp, 16
666; RV32IFD-NEXT:    ret
667;
668; RV64IFD-LABEL: test_roundeven_ui64:
669; RV64IFD:       # %bb.0:
670; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rne
671; RV64IFD-NEXT:    ret
672  %a = call double @llvm.roundeven.f64(double %x)
673  %b = fptoui double %a to i64
674  ret i64 %b
675}
676
677declare double @llvm.floor.f64(double)
678declare double @llvm.ceil.f64(double)
679declare double @llvm.trunc.f64(double)
680declare double @llvm.round.f64(double)
681declare double @llvm.roundeven.f64(double)
682