1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32IFD %s
4; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV64IFD %s
6; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
7; RUN:   | FileCheck -check-prefix=RV32I %s
8; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
9; RUN:   | FileCheck -check-prefix=RV64I %s
10
11define float @fcvt_s_d(double %a) nounwind {
12; RV32IFD-LABEL: fcvt_s_d:
13; RV32IFD:       # %bb.0:
14; RV32IFD-NEXT:    addi sp, sp, -16
15; RV32IFD-NEXT:    sw a0, 8(sp)
16; RV32IFD-NEXT:    sw a1, 12(sp)
17; RV32IFD-NEXT:    fld ft0, 8(sp)
18; RV32IFD-NEXT:    fcvt.s.d ft0, ft0
19; RV32IFD-NEXT:    fmv.x.w a0, ft0
20; RV32IFD-NEXT:    addi sp, sp, 16
21; RV32IFD-NEXT:    ret
22;
23; RV64IFD-LABEL: fcvt_s_d:
24; RV64IFD:       # %bb.0:
25; RV64IFD-NEXT:    fmv.d.x ft0, a0
26; RV64IFD-NEXT:    fcvt.s.d ft0, ft0
27; RV64IFD-NEXT:    fmv.x.w a0, ft0
28; RV64IFD-NEXT:    ret
29;
30; RV32I-LABEL: fcvt_s_d:
31; RV32I:       # %bb.0:
32; RV32I-NEXT:    addi sp, sp, -16
33; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
34; RV32I-NEXT:    call __truncdfsf2@plt
35; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
36; RV32I-NEXT:    addi sp, sp, 16
37; RV32I-NEXT:    ret
38;
39; RV64I-LABEL: fcvt_s_d:
40; RV64I:       # %bb.0:
41; RV64I-NEXT:    addi sp, sp, -16
42; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
43; RV64I-NEXT:    call __truncdfsf2@plt
44; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
45; RV64I-NEXT:    addi sp, sp, 16
46; RV64I-NEXT:    ret
47  %1 = fptrunc double %a to float
48  ret float %1
49}
50
51define double @fcvt_d_s(float %a) nounwind {
52; RV32IFD-LABEL: fcvt_d_s:
53; RV32IFD:       # %bb.0:
54; RV32IFD-NEXT:    addi sp, sp, -16
55; RV32IFD-NEXT:    fmv.w.x ft0, a0
56; RV32IFD-NEXT:    fcvt.d.s ft0, ft0
57; RV32IFD-NEXT:    fsd ft0, 8(sp)
58; RV32IFD-NEXT:    lw a0, 8(sp)
59; RV32IFD-NEXT:    lw a1, 12(sp)
60; RV32IFD-NEXT:    addi sp, sp, 16
61; RV32IFD-NEXT:    ret
62;
63; RV64IFD-LABEL: fcvt_d_s:
64; RV64IFD:       # %bb.0:
65; RV64IFD-NEXT:    fmv.w.x ft0, a0
66; RV64IFD-NEXT:    fcvt.d.s ft0, ft0
67; RV64IFD-NEXT:    fmv.x.d a0, ft0
68; RV64IFD-NEXT:    ret
69;
70; RV32I-LABEL: fcvt_d_s:
71; RV32I:       # %bb.0:
72; RV32I-NEXT:    addi sp, sp, -16
73; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
74; RV32I-NEXT:    call __extendsfdf2@plt
75; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
76; RV32I-NEXT:    addi sp, sp, 16
77; RV32I-NEXT:    ret
78;
79; RV64I-LABEL: fcvt_d_s:
80; RV64I:       # %bb.0:
81; RV64I-NEXT:    addi sp, sp, -16
82; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
83; RV64I-NEXT:    call __extendsfdf2@plt
84; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
85; RV64I-NEXT:    addi sp, sp, 16
86; RV64I-NEXT:    ret
87  %1 = fpext float %a to double
88  ret double %1
89}
90
91; For RV64D, fcvt.l.d is semantically equivalent to fcvt.w.d in this case
92; because fptosi will produce poison if the result doesn't fit into an i32.
93define i32 @fcvt_w_d(double %a) nounwind {
94; RV32IFD-LABEL: fcvt_w_d:
95; RV32IFD:       # %bb.0:
96; RV32IFD-NEXT:    addi sp, sp, -16
97; RV32IFD-NEXT:    sw a0, 8(sp)
98; RV32IFD-NEXT:    sw a1, 12(sp)
99; RV32IFD-NEXT:    fld ft0, 8(sp)
100; RV32IFD-NEXT:    fcvt.w.d a0, ft0, rtz
101; RV32IFD-NEXT:    addi sp, sp, 16
102; RV32IFD-NEXT:    ret
103;
104; RV64IFD-LABEL: fcvt_w_d:
105; RV64IFD:       # %bb.0:
106; RV64IFD-NEXT:    fmv.d.x ft0, a0
107; RV64IFD-NEXT:    fcvt.w.d a0, ft0, rtz
108; RV64IFD-NEXT:    ret
109;
110; RV32I-LABEL: fcvt_w_d:
111; RV32I:       # %bb.0:
112; RV32I-NEXT:    addi sp, sp, -16
113; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
114; RV32I-NEXT:    call __fixdfsi@plt
115; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
116; RV32I-NEXT:    addi sp, sp, 16
117; RV32I-NEXT:    ret
118;
119; RV64I-LABEL: fcvt_w_d:
120; RV64I:       # %bb.0:
121; RV64I-NEXT:    addi sp, sp, -16
122; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
123; RV64I-NEXT:    call __fixdfsi@plt
124; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
125; RV64I-NEXT:    addi sp, sp, 16
126; RV64I-NEXT:    ret
127  %1 = fptosi double %a to i32
128  ret i32 %1
129}
130
131define i32 @fcvt_w_d_sat(double %a) nounwind {
132; RV32IFD-LABEL: fcvt_w_d_sat:
133; RV32IFD:       # %bb.0: # %start
134; RV32IFD-NEXT:    addi sp, sp, -16
135; RV32IFD-NEXT:    sw a0, 8(sp)
136; RV32IFD-NEXT:    sw a1, 12(sp)
137; RV32IFD-NEXT:    fld ft0, 8(sp)
138; RV32IFD-NEXT:    feq.d a0, ft0, ft0
139; RV32IFD-NEXT:    bnez a0, .LBB3_2
140; RV32IFD-NEXT:  # %bb.1: # %start
141; RV32IFD-NEXT:    li a0, 0
142; RV32IFD-NEXT:    addi sp, sp, 16
143; RV32IFD-NEXT:    ret
144; RV32IFD-NEXT:  .LBB3_2:
145; RV32IFD-NEXT:    fcvt.w.d a0, ft0, rtz
146; RV32IFD-NEXT:    addi sp, sp, 16
147; RV32IFD-NEXT:    ret
148;
149; RV64IFD-LABEL: fcvt_w_d_sat:
150; RV64IFD:       # %bb.0: # %start
151; RV64IFD-NEXT:    fmv.d.x ft0, a0
152; RV64IFD-NEXT:    feq.d a0, ft0, ft0
153; RV64IFD-NEXT:    bnez a0, .LBB3_2
154; RV64IFD-NEXT:  # %bb.1: # %start
155; RV64IFD-NEXT:    li a0, 0
156; RV64IFD-NEXT:    ret
157; RV64IFD-NEXT:  .LBB3_2:
158; RV64IFD-NEXT:    fcvt.w.d a0, ft0, rtz
159; RV64IFD-NEXT:    ret
160;
161; RV32I-LABEL: fcvt_w_d_sat:
162; RV32I:       # %bb.0: # %start
163; RV32I-NEXT:    addi sp, sp, -32
164; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
165; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
166; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
167; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
168; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
169; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
170; RV32I-NEXT:    sw s5, 4(sp) # 4-byte Folded Spill
171; RV32I-NEXT:    mv s2, a1
172; RV32I-NEXT:    mv s1, a0
173; RV32I-NEXT:    lui a3, 794112
174; RV32I-NEXT:    li s0, 0
175; RV32I-NEXT:    li a2, 0
176; RV32I-NEXT:    call __gedf2@plt
177; RV32I-NEXT:    mv s3, a0
178; RV32I-NEXT:    mv a0, s1
179; RV32I-NEXT:    mv a1, s2
180; RV32I-NEXT:    call __fixdfsi@plt
181; RV32I-NEXT:    lui s5, 524288
182; RV32I-NEXT:    lui s4, 524288
183; RV32I-NEXT:    blt s3, s0, .LBB3_2
184; RV32I-NEXT:  # %bb.1: # %start
185; RV32I-NEXT:    mv s4, a0
186; RV32I-NEXT:  .LBB3_2: # %start
187; RV32I-NEXT:    lui a0, 269824
188; RV32I-NEXT:    addi a3, a0, -1
189; RV32I-NEXT:    lui a2, 1047552
190; RV32I-NEXT:    mv a0, s1
191; RV32I-NEXT:    mv a1, s2
192; RV32I-NEXT:    call __gtdf2@plt
193; RV32I-NEXT:    bge s0, a0, .LBB3_4
194; RV32I-NEXT:  # %bb.3:
195; RV32I-NEXT:    addi s4, s5, -1
196; RV32I-NEXT:  .LBB3_4: # %start
197; RV32I-NEXT:    mv a0, s1
198; RV32I-NEXT:    mv a1, s2
199; RV32I-NEXT:    mv a2, s1
200; RV32I-NEXT:    mv a3, s2
201; RV32I-NEXT:    call __unorddf2@plt
202; RV32I-NEXT:    bne a0, s0, .LBB3_6
203; RV32I-NEXT:  # %bb.5: # %start
204; RV32I-NEXT:    mv s0, s4
205; RV32I-NEXT:  .LBB3_6: # %start
206; RV32I-NEXT:    mv a0, s0
207; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
208; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
209; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
210; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
211; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
212; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
213; RV32I-NEXT:    lw s5, 4(sp) # 4-byte Folded Reload
214; RV32I-NEXT:    addi sp, sp, 32
215; RV32I-NEXT:    ret
216;
217; RV64I-LABEL: fcvt_w_d_sat:
218; RV64I:       # %bb.0: # %start
219; RV64I-NEXT:    addi sp, sp, -48
220; RV64I-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
221; RV64I-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
222; RV64I-NEXT:    sd s1, 24(sp) # 8-byte Folded Spill
223; RV64I-NEXT:    sd s2, 16(sp) # 8-byte Folded Spill
224; RV64I-NEXT:    sd s3, 8(sp) # 8-byte Folded Spill
225; RV64I-NEXT:    sd s4, 0(sp) # 8-byte Folded Spill
226; RV64I-NEXT:    mv s0, a0
227; RV64I-NEXT:    li a0, -497
228; RV64I-NEXT:    slli a1, a0, 53
229; RV64I-NEXT:    mv a0, s0
230; RV64I-NEXT:    call __gedf2@plt
231; RV64I-NEXT:    mv s2, a0
232; RV64I-NEXT:    mv a0, s0
233; RV64I-NEXT:    call __fixdfdi@plt
234; RV64I-NEXT:    li s1, 0
235; RV64I-NEXT:    lui s4, 524288
236; RV64I-NEXT:    lui s3, 524288
237; RV64I-NEXT:    bltz s2, .LBB3_2
238; RV64I-NEXT:  # %bb.1: # %start
239; RV64I-NEXT:    mv s3, a0
240; RV64I-NEXT:  .LBB3_2: # %start
241; RV64I-NEXT:    li a0, 527
242; RV64I-NEXT:    slli a0, a0, 31
243; RV64I-NEXT:    addi a0, a0, -1
244; RV64I-NEXT:    slli a1, a0, 22
245; RV64I-NEXT:    mv a0, s0
246; RV64I-NEXT:    call __gtdf2@plt
247; RV64I-NEXT:    bge s1, a0, .LBB3_4
248; RV64I-NEXT:  # %bb.3:
249; RV64I-NEXT:    addiw s3, s4, -1
250; RV64I-NEXT:  .LBB3_4: # %start
251; RV64I-NEXT:    mv a0, s0
252; RV64I-NEXT:    mv a1, s0
253; RV64I-NEXT:    call __unorddf2@plt
254; RV64I-NEXT:    bne a0, s1, .LBB3_6
255; RV64I-NEXT:  # %bb.5: # %start
256; RV64I-NEXT:    mv s1, s3
257; RV64I-NEXT:  .LBB3_6: # %start
258; RV64I-NEXT:    mv a0, s1
259; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
260; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
261; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
262; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
263; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
264; RV64I-NEXT:    ld s4, 0(sp) # 8-byte Folded Reload
265; RV64I-NEXT:    addi sp, sp, 48
266; RV64I-NEXT:    ret
267start:
268  %0 = tail call i32 @llvm.fptosi.sat.i32.f64(double %a)
269  ret i32 %0
270}
271declare i32 @llvm.fptosi.sat.i32.f64(double)
272
273; For RV64D, fcvt.lu.d is semantically equivalent to fcvt.wu.d in this case
274; because fptosi will produce poison if the result doesn't fit into an i32.
275define i32 @fcvt_wu_d(double %a) nounwind {
276; RV32IFD-LABEL: fcvt_wu_d:
277; RV32IFD:       # %bb.0:
278; RV32IFD-NEXT:    addi sp, sp, -16
279; RV32IFD-NEXT:    sw a0, 8(sp)
280; RV32IFD-NEXT:    sw a1, 12(sp)
281; RV32IFD-NEXT:    fld ft0, 8(sp)
282; RV32IFD-NEXT:    fcvt.wu.d a0, ft0, rtz
283; RV32IFD-NEXT:    addi sp, sp, 16
284; RV32IFD-NEXT:    ret
285;
286; RV64IFD-LABEL: fcvt_wu_d:
287; RV64IFD:       # %bb.0:
288; RV64IFD-NEXT:    fmv.d.x ft0, a0
289; RV64IFD-NEXT:    fcvt.wu.d a0, ft0, rtz
290; RV64IFD-NEXT:    ret
291;
292; RV32I-LABEL: fcvt_wu_d:
293; RV32I:       # %bb.0:
294; RV32I-NEXT:    addi sp, sp, -16
295; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
296; RV32I-NEXT:    call __fixunsdfsi@plt
297; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
298; RV32I-NEXT:    addi sp, sp, 16
299; RV32I-NEXT:    ret
300;
301; RV64I-LABEL: fcvt_wu_d:
302; RV64I:       # %bb.0:
303; RV64I-NEXT:    addi sp, sp, -16
304; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
305; RV64I-NEXT:    call __fixunsdfsi@plt
306; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
307; RV64I-NEXT:    addi sp, sp, 16
308; RV64I-NEXT:    ret
309  %1 = fptoui double %a to i32
310  ret i32 %1
311}
312
313; Test where the fptoui has multiple uses, one of which causes a sext to be
314; inserted on RV64.
315define i32 @fcvt_wu_d_multiple_use(double %x, i32* %y) {
316; RV32IFD-LABEL: fcvt_wu_d_multiple_use:
317; RV32IFD:       # %bb.0:
318; RV32IFD-NEXT:    addi sp, sp, -16
319; RV32IFD-NEXT:    .cfi_def_cfa_offset 16
320; RV32IFD-NEXT:    sw a0, 8(sp)
321; RV32IFD-NEXT:    sw a1, 12(sp)
322; RV32IFD-NEXT:    fld ft0, 8(sp)
323; RV32IFD-NEXT:    fcvt.wu.d a1, ft0, rtz
324; RV32IFD-NEXT:    li a0, 1
325; RV32IFD-NEXT:    beqz a1, .LBB5_2
326; RV32IFD-NEXT:  # %bb.1:
327; RV32IFD-NEXT:    mv a0, a1
328; RV32IFD-NEXT:  .LBB5_2:
329; RV32IFD-NEXT:    addi sp, sp, 16
330; RV32IFD-NEXT:    ret
331;
332; RV64IFD-LABEL: fcvt_wu_d_multiple_use:
333; RV64IFD:       # %bb.0:
334; RV64IFD-NEXT:    fmv.d.x ft0, a0
335; RV64IFD-NEXT:    fcvt.wu.d a1, ft0, rtz
336; RV64IFD-NEXT:    li a0, 1
337; RV64IFD-NEXT:    beqz a1, .LBB5_2
338; RV64IFD-NEXT:  # %bb.1:
339; RV64IFD-NEXT:    mv a0, a1
340; RV64IFD-NEXT:  .LBB5_2:
341; RV64IFD-NEXT:    ret
342;
343; RV32I-LABEL: fcvt_wu_d_multiple_use:
344; RV32I:       # %bb.0:
345; RV32I-NEXT:    addi sp, sp, -16
346; RV32I-NEXT:    .cfi_def_cfa_offset 16
347; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
348; RV32I-NEXT:    .cfi_offset ra, -4
349; RV32I-NEXT:    call __fixunsdfsi@plt
350; RV32I-NEXT:    mv a1, a0
351; RV32I-NEXT:    li a0, 1
352; RV32I-NEXT:    beqz a1, .LBB5_2
353; RV32I-NEXT:  # %bb.1:
354; RV32I-NEXT:    mv a0, a1
355; RV32I-NEXT:  .LBB5_2:
356; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
357; RV32I-NEXT:    addi sp, sp, 16
358; RV32I-NEXT:    ret
359;
360; RV64I-LABEL: fcvt_wu_d_multiple_use:
361; RV64I:       # %bb.0:
362; RV64I-NEXT:    addi sp, sp, -16
363; RV64I-NEXT:    .cfi_def_cfa_offset 16
364; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
365; RV64I-NEXT:    .cfi_offset ra, -8
366; RV64I-NEXT:    call __fixunsdfsi@plt
367; RV64I-NEXT:    mv a1, a0
368; RV64I-NEXT:    li a0, 1
369; RV64I-NEXT:    beqz a1, .LBB5_2
370; RV64I-NEXT:  # %bb.1:
371; RV64I-NEXT:    mv a0, a1
372; RV64I-NEXT:  .LBB5_2:
373; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
374; RV64I-NEXT:    addi sp, sp, 16
375; RV64I-NEXT:    ret
376  %a = fptoui double %x to i32
377  %b = icmp eq i32 %a, 0
378  %c = select i1 %b, i32 1, i32 %a
379  ret i32 %c
380}
381
382define i32 @fcvt_wu_d_sat(double %a) nounwind {
383; RV32IFD-LABEL: fcvt_wu_d_sat:
384; RV32IFD:       # %bb.0: # %start
385; RV32IFD-NEXT:    addi sp, sp, -16
386; RV32IFD-NEXT:    sw a0, 8(sp)
387; RV32IFD-NEXT:    sw a1, 12(sp)
388; RV32IFD-NEXT:    fld ft0, 8(sp)
389; RV32IFD-NEXT:    feq.d a0, ft0, ft0
390; RV32IFD-NEXT:    bnez a0, .LBB6_2
391; RV32IFD-NEXT:  # %bb.1: # %start
392; RV32IFD-NEXT:    li a0, 0
393; RV32IFD-NEXT:    addi sp, sp, 16
394; RV32IFD-NEXT:    ret
395; RV32IFD-NEXT:  .LBB6_2:
396; RV32IFD-NEXT:    fcvt.wu.d a0, ft0, rtz
397; RV32IFD-NEXT:    addi sp, sp, 16
398; RV32IFD-NEXT:    ret
399;
400; RV64IFD-LABEL: fcvt_wu_d_sat:
401; RV64IFD:       # %bb.0: # %start
402; RV64IFD-NEXT:    fmv.d.x ft0, a0
403; RV64IFD-NEXT:    feq.d a0, ft0, ft0
404; RV64IFD-NEXT:    bnez a0, .LBB6_2
405; RV64IFD-NEXT:  # %bb.1: # %start
406; RV64IFD-NEXT:    li a0, 0
407; RV64IFD-NEXT:    ret
408; RV64IFD-NEXT:  .LBB6_2:
409; RV64IFD-NEXT:    fcvt.wu.d a0, ft0, rtz
410; RV64IFD-NEXT:    ret
411;
412; RV32I-LABEL: fcvt_wu_d_sat:
413; RV32I:       # %bb.0: # %start
414; RV32I-NEXT:    addi sp, sp, -32
415; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
416; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
417; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
418; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
419; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
420; RV32I-NEXT:    mv s1, a1
421; RV32I-NEXT:    mv s0, a0
422; RV32I-NEXT:    lui a0, 270080
423; RV32I-NEXT:    addi a3, a0, -1
424; RV32I-NEXT:    lui a2, 1048064
425; RV32I-NEXT:    mv a0, s0
426; RV32I-NEXT:    call __gtdf2@plt
427; RV32I-NEXT:    mv s2, a0
428; RV32I-NEXT:    mv a0, s0
429; RV32I-NEXT:    mv a1, s1
430; RV32I-NEXT:    li a2, 0
431; RV32I-NEXT:    li a3, 0
432; RV32I-NEXT:    call __gedf2@plt
433; RV32I-NEXT:    mv s3, a0
434; RV32I-NEXT:    mv a0, s0
435; RV32I-NEXT:    mv a1, s1
436; RV32I-NEXT:    call __fixunsdfsi@plt
437; RV32I-NEXT:    li a1, 0
438; RV32I-NEXT:    bltz s3, .LBB6_2
439; RV32I-NEXT:  # %bb.1: # %start
440; RV32I-NEXT:    mv a1, a0
441; RV32I-NEXT:  .LBB6_2: # %start
442; RV32I-NEXT:    li a0, -1
443; RV32I-NEXT:    bgtz s2, .LBB6_4
444; RV32I-NEXT:  # %bb.3: # %start
445; RV32I-NEXT:    mv a0, a1
446; RV32I-NEXT:  .LBB6_4: # %start
447; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
448; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
449; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
450; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
451; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
452; RV32I-NEXT:    addi sp, sp, 32
453; RV32I-NEXT:    ret
454;
455; RV64I-LABEL: fcvt_wu_d_sat:
456; RV64I:       # %bb.0: # %start
457; RV64I-NEXT:    addi sp, sp, -32
458; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
459; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
460; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
461; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
462; RV64I-NEXT:    mv s0, a0
463; RV64I-NEXT:    li a1, 0
464; RV64I-NEXT:    call __gedf2@plt
465; RV64I-NEXT:    mv s2, a0
466; RV64I-NEXT:    mv a0, s0
467; RV64I-NEXT:    call __fixunsdfdi@plt
468; RV64I-NEXT:    li s1, 0
469; RV64I-NEXT:    bltz s2, .LBB6_2
470; RV64I-NEXT:  # %bb.1: # %start
471; RV64I-NEXT:    mv s1, a0
472; RV64I-NEXT:  .LBB6_2: # %start
473; RV64I-NEXT:    li a0, 1055
474; RV64I-NEXT:    slli a0, a0, 31
475; RV64I-NEXT:    addi a0, a0, -1
476; RV64I-NEXT:    slli a1, a0, 21
477; RV64I-NEXT:    mv a0, s0
478; RV64I-NEXT:    call __gtdf2@plt
479; RV64I-NEXT:    blez a0, .LBB6_4
480; RV64I-NEXT:  # %bb.3:
481; RV64I-NEXT:    li a0, -1
482; RV64I-NEXT:    srli s1, a0, 32
483; RV64I-NEXT:  .LBB6_4: # %start
484; RV64I-NEXT:    mv a0, s1
485; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
486; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
487; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
488; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
489; RV64I-NEXT:    addi sp, sp, 32
490; RV64I-NEXT:    ret
491start:
492  %0 = tail call i32 @llvm.fptoui.sat.i32.f64(double %a)
493  ret i32 %0
494}
495declare i32 @llvm.fptoui.sat.i32.f64(double)
496
497define double @fcvt_d_w(i32 %a) nounwind {
498; RV32IFD-LABEL: fcvt_d_w:
499; RV32IFD:       # %bb.0:
500; RV32IFD-NEXT:    addi sp, sp, -16
501; RV32IFD-NEXT:    fcvt.d.w ft0, a0
502; RV32IFD-NEXT:    fsd ft0, 8(sp)
503; RV32IFD-NEXT:    lw a0, 8(sp)
504; RV32IFD-NEXT:    lw a1, 12(sp)
505; RV32IFD-NEXT:    addi sp, sp, 16
506; RV32IFD-NEXT:    ret
507;
508; RV64IFD-LABEL: fcvt_d_w:
509; RV64IFD:       # %bb.0:
510; RV64IFD-NEXT:    fcvt.d.w ft0, a0
511; RV64IFD-NEXT:    fmv.x.d a0, ft0
512; RV64IFD-NEXT:    ret
513;
514; RV32I-LABEL: fcvt_d_w:
515; RV32I:       # %bb.0:
516; RV32I-NEXT:    addi sp, sp, -16
517; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
518; RV32I-NEXT:    call __floatsidf@plt
519; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
520; RV32I-NEXT:    addi sp, sp, 16
521; RV32I-NEXT:    ret
522;
523; RV64I-LABEL: fcvt_d_w:
524; RV64I:       # %bb.0:
525; RV64I-NEXT:    addi sp, sp, -16
526; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
527; RV64I-NEXT:    sext.w a0, a0
528; RV64I-NEXT:    call __floatsidf@plt
529; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
530; RV64I-NEXT:    addi sp, sp, 16
531; RV64I-NEXT:    ret
532  %1 = sitofp i32 %a to double
533  ret double %1
534}
535
536define double @fcvt_d_w_load(i32* %p) nounwind {
537; RV32IFD-LABEL: fcvt_d_w_load:
538; RV32IFD:       # %bb.0:
539; RV32IFD-NEXT:    addi sp, sp, -16
540; RV32IFD-NEXT:    lw a0, 0(a0)
541; RV32IFD-NEXT:    fcvt.d.w ft0, a0
542; RV32IFD-NEXT:    fsd ft0, 8(sp)
543; RV32IFD-NEXT:    lw a0, 8(sp)
544; RV32IFD-NEXT:    lw a1, 12(sp)
545; RV32IFD-NEXT:    addi sp, sp, 16
546; RV32IFD-NEXT:    ret
547;
548; RV64IFD-LABEL: fcvt_d_w_load:
549; RV64IFD:       # %bb.0:
550; RV64IFD-NEXT:    lw a0, 0(a0)
551; RV64IFD-NEXT:    fcvt.d.w ft0, a0
552; RV64IFD-NEXT:    fmv.x.d a0, ft0
553; RV64IFD-NEXT:    ret
554;
555; RV32I-LABEL: fcvt_d_w_load:
556; RV32I:       # %bb.0:
557; RV32I-NEXT:    addi sp, sp, -16
558; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
559; RV32I-NEXT:    lw a0, 0(a0)
560; RV32I-NEXT:    call __floatsidf@plt
561; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
562; RV32I-NEXT:    addi sp, sp, 16
563; RV32I-NEXT:    ret
564;
565; RV64I-LABEL: fcvt_d_w_load:
566; RV64I:       # %bb.0:
567; RV64I-NEXT:    addi sp, sp, -16
568; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
569; RV64I-NEXT:    lw a0, 0(a0)
570; RV64I-NEXT:    call __floatsidf@plt
571; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
572; RV64I-NEXT:    addi sp, sp, 16
573; RV64I-NEXT:    ret
574  %a = load i32, i32* %p
575  %1 = sitofp i32 %a to double
576  ret double %1
577}
578
579define double @fcvt_d_wu(i32 %a) nounwind {
580; RV32IFD-LABEL: fcvt_d_wu:
581; RV32IFD:       # %bb.0:
582; RV32IFD-NEXT:    addi sp, sp, -16
583; RV32IFD-NEXT:    fcvt.d.wu ft0, a0
584; RV32IFD-NEXT:    fsd ft0, 8(sp)
585; RV32IFD-NEXT:    lw a0, 8(sp)
586; RV32IFD-NEXT:    lw a1, 12(sp)
587; RV32IFD-NEXT:    addi sp, sp, 16
588; RV32IFD-NEXT:    ret
589;
590; RV64IFD-LABEL: fcvt_d_wu:
591; RV64IFD:       # %bb.0:
592; RV64IFD-NEXT:    fcvt.d.wu ft0, a0
593; RV64IFD-NEXT:    fmv.x.d a0, ft0
594; RV64IFD-NEXT:    ret
595;
596; RV32I-LABEL: fcvt_d_wu:
597; RV32I:       # %bb.0:
598; RV32I-NEXT:    addi sp, sp, -16
599; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
600; RV32I-NEXT:    call __floatunsidf@plt
601; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
602; RV32I-NEXT:    addi sp, sp, 16
603; RV32I-NEXT:    ret
604;
605; RV64I-LABEL: fcvt_d_wu:
606; RV64I:       # %bb.0:
607; RV64I-NEXT:    addi sp, sp, -16
608; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
609; RV64I-NEXT:    sext.w a0, a0
610; RV64I-NEXT:    call __floatunsidf@plt
611; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
612; RV64I-NEXT:    addi sp, sp, 16
613; RV64I-NEXT:    ret
614  %1 = uitofp i32 %a to double
615  ret double %1
616}
617
618define double @fcvt_d_wu_load(i32* %p) nounwind {
619; RV32IFD-LABEL: fcvt_d_wu_load:
620; RV32IFD:       # %bb.0:
621; RV32IFD-NEXT:    addi sp, sp, -16
622; RV32IFD-NEXT:    lw a0, 0(a0)
623; RV32IFD-NEXT:    fcvt.d.wu ft0, a0
624; RV32IFD-NEXT:    fsd ft0, 8(sp)
625; RV32IFD-NEXT:    lw a0, 8(sp)
626; RV32IFD-NEXT:    lw a1, 12(sp)
627; RV32IFD-NEXT:    addi sp, sp, 16
628; RV32IFD-NEXT:    ret
629;
630; RV64IFD-LABEL: fcvt_d_wu_load:
631; RV64IFD:       # %bb.0:
632; RV64IFD-NEXT:    lwu a0, 0(a0)
633; RV64IFD-NEXT:    fcvt.d.wu ft0, a0
634; RV64IFD-NEXT:    fmv.x.d a0, ft0
635; RV64IFD-NEXT:    ret
636;
637; RV32I-LABEL: fcvt_d_wu_load:
638; RV32I:       # %bb.0:
639; RV32I-NEXT:    addi sp, sp, -16
640; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
641; RV32I-NEXT:    lw a0, 0(a0)
642; RV32I-NEXT:    call __floatunsidf@plt
643; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
644; RV32I-NEXT:    addi sp, sp, 16
645; RV32I-NEXT:    ret
646;
647; RV64I-LABEL: fcvt_d_wu_load:
648; RV64I:       # %bb.0:
649; RV64I-NEXT:    addi sp, sp, -16
650; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
651; RV64I-NEXT:    lw a0, 0(a0)
652; RV64I-NEXT:    call __floatunsidf@plt
653; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
654; RV64I-NEXT:    addi sp, sp, 16
655; RV64I-NEXT:    ret
656  %a = load i32, i32* %p
657  %1 = uitofp i32 %a to double
658  ret double %1
659}
660
661define i64 @fcvt_l_d(double %a) nounwind {
662; RV32IFD-LABEL: fcvt_l_d:
663; RV32IFD:       # %bb.0:
664; RV32IFD-NEXT:    addi sp, sp, -16
665; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
666; RV32IFD-NEXT:    call __fixdfdi@plt
667; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
668; RV32IFD-NEXT:    addi sp, sp, 16
669; RV32IFD-NEXT:    ret
670;
671; RV64IFD-LABEL: fcvt_l_d:
672; RV64IFD:       # %bb.0:
673; RV64IFD-NEXT:    fmv.d.x ft0, a0
674; RV64IFD-NEXT:    fcvt.l.d a0, ft0, rtz
675; RV64IFD-NEXT:    ret
676;
677; RV32I-LABEL: fcvt_l_d:
678; RV32I:       # %bb.0:
679; RV32I-NEXT:    addi sp, sp, -16
680; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
681; RV32I-NEXT:    call __fixdfdi@plt
682; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
683; RV32I-NEXT:    addi sp, sp, 16
684; RV32I-NEXT:    ret
685;
686; RV64I-LABEL: fcvt_l_d:
687; RV64I:       # %bb.0:
688; RV64I-NEXT:    addi sp, sp, -16
689; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
690; RV64I-NEXT:    call __fixdfdi@plt
691; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
692; RV64I-NEXT:    addi sp, sp, 16
693; RV64I-NEXT:    ret
694  %1 = fptosi double %a to i64
695  ret i64 %1
696}
697
698define i64 @fcvt_l_d_sat(double %a) nounwind {
699; RV32IFD-LABEL: fcvt_l_d_sat:
700; RV32IFD:       # %bb.0: # %start
701; RV32IFD-NEXT:    addi sp, sp, -32
702; RV32IFD-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
703; RV32IFD-NEXT:    sw a0, 16(sp)
704; RV32IFD-NEXT:    sw a1, 20(sp)
705; RV32IFD-NEXT:    fld ft0, 16(sp)
706; RV32IFD-NEXT:    fsd ft0, 8(sp) # 8-byte Folded Spill
707; RV32IFD-NEXT:    call __fixdfdi@plt
708; RV32IFD-NEXT:    fld ft1, 8(sp) # 8-byte Folded Reload
709; RV32IFD-NEXT:    lui a2, %hi(.LCPI12_0)
710; RV32IFD-NEXT:    fld ft0, %lo(.LCPI12_0)(a2)
711; RV32IFD-NEXT:    fle.d a3, ft0, ft1
712; RV32IFD-NEXT:    mv a2, a0
713; RV32IFD-NEXT:    bnez a3, .LBB12_2
714; RV32IFD-NEXT:  # %bb.1: # %start
715; RV32IFD-NEXT:    li a2, 0
716; RV32IFD-NEXT:  .LBB12_2: # %start
717; RV32IFD-NEXT:    lui a0, %hi(.LCPI12_1)
718; RV32IFD-NEXT:    fld ft0, %lo(.LCPI12_1)(a0)
719; RV32IFD-NEXT:    flt.d a4, ft0, ft1
720; RV32IFD-NEXT:    li a0, -1
721; RV32IFD-NEXT:    beqz a4, .LBB12_9
722; RV32IFD-NEXT:  # %bb.3: # %start
723; RV32IFD-NEXT:    feq.d a2, ft1, ft1
724; RV32IFD-NEXT:    beqz a2, .LBB12_10
725; RV32IFD-NEXT:  .LBB12_4: # %start
726; RV32IFD-NEXT:    lui a5, 524288
727; RV32IFD-NEXT:    beqz a3, .LBB12_11
728; RV32IFD-NEXT:  .LBB12_5: # %start
729; RV32IFD-NEXT:    bnez a4, .LBB12_12
730; RV32IFD-NEXT:  .LBB12_6: # %start
731; RV32IFD-NEXT:    bnez a2, .LBB12_8
732; RV32IFD-NEXT:  .LBB12_7: # %start
733; RV32IFD-NEXT:    li a1, 0
734; RV32IFD-NEXT:  .LBB12_8: # %start
735; RV32IFD-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
736; RV32IFD-NEXT:    addi sp, sp, 32
737; RV32IFD-NEXT:    ret
738; RV32IFD-NEXT:  .LBB12_9: # %start
739; RV32IFD-NEXT:    mv a0, a2
740; RV32IFD-NEXT:    feq.d a2, ft1, ft1
741; RV32IFD-NEXT:    bnez a2, .LBB12_4
742; RV32IFD-NEXT:  .LBB12_10: # %start
743; RV32IFD-NEXT:    li a0, 0
744; RV32IFD-NEXT:    lui a5, 524288
745; RV32IFD-NEXT:    bnez a3, .LBB12_5
746; RV32IFD-NEXT:  .LBB12_11: # %start
747; RV32IFD-NEXT:    lui a1, 524288
748; RV32IFD-NEXT:    beqz a4, .LBB12_6
749; RV32IFD-NEXT:  .LBB12_12:
750; RV32IFD-NEXT:    addi a1, a5, -1
751; RV32IFD-NEXT:    beqz a2, .LBB12_7
752; RV32IFD-NEXT:    j .LBB12_8
753;
754; RV64IFD-LABEL: fcvt_l_d_sat:
755; RV64IFD:       # %bb.0: # %start
756; RV64IFD-NEXT:    fmv.d.x ft0, a0
757; RV64IFD-NEXT:    feq.d a0, ft0, ft0
758; RV64IFD-NEXT:    bnez a0, .LBB12_2
759; RV64IFD-NEXT:  # %bb.1: # %start
760; RV64IFD-NEXT:    li a0, 0
761; RV64IFD-NEXT:    ret
762; RV64IFD-NEXT:  .LBB12_2:
763; RV64IFD-NEXT:    fcvt.l.d a0, ft0, rtz
764; RV64IFD-NEXT:    ret
765;
766; RV32I-LABEL: fcvt_l_d_sat:
767; RV32I:       # %bb.0: # %start
768; RV32I-NEXT:    addi sp, sp, -48
769; RV32I-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
770; RV32I-NEXT:    sw s0, 40(sp) # 4-byte Folded Spill
771; RV32I-NEXT:    sw s1, 36(sp) # 4-byte Folded Spill
772; RV32I-NEXT:    sw s2, 32(sp) # 4-byte Folded Spill
773; RV32I-NEXT:    sw s3, 28(sp) # 4-byte Folded Spill
774; RV32I-NEXT:    sw s4, 24(sp) # 4-byte Folded Spill
775; RV32I-NEXT:    sw s5, 20(sp) # 4-byte Folded Spill
776; RV32I-NEXT:    sw s6, 16(sp) # 4-byte Folded Spill
777; RV32I-NEXT:    sw s7, 12(sp) # 4-byte Folded Spill
778; RV32I-NEXT:    mv s2, a1
779; RV32I-NEXT:    mv s1, a0
780; RV32I-NEXT:    lui a0, 278016
781; RV32I-NEXT:    addi s3, a0, -1
782; RV32I-NEXT:    li a2, -1
783; RV32I-NEXT:    mv a0, s1
784; RV32I-NEXT:    mv a3, s3
785; RV32I-NEXT:    call __gtdf2@plt
786; RV32I-NEXT:    mv s4, a0
787; RV32I-NEXT:    lui a3, 802304
788; RV32I-NEXT:    li s0, 0
789; RV32I-NEXT:    mv a0, s1
790; RV32I-NEXT:    mv a1, s2
791; RV32I-NEXT:    li a2, 0
792; RV32I-NEXT:    call __gedf2@plt
793; RV32I-NEXT:    mv s6, a0
794; RV32I-NEXT:    mv a0, s1
795; RV32I-NEXT:    mv a1, s2
796; RV32I-NEXT:    call __fixdfdi@plt
797; RV32I-NEXT:    mv s5, a1
798; RV32I-NEXT:    mv a1, s0
799; RV32I-NEXT:    blt s6, s0, .LBB12_2
800; RV32I-NEXT:  # %bb.1: # %start
801; RV32I-NEXT:    mv a1, a0
802; RV32I-NEXT:  .LBB12_2: # %start
803; RV32I-NEXT:    li s6, -1
804; RV32I-NEXT:    blt s0, s4, .LBB12_4
805; RV32I-NEXT:  # %bb.3: # %start
806; RV32I-NEXT:    mv s6, a1
807; RV32I-NEXT:  .LBB12_4: # %start
808; RV32I-NEXT:    mv a0, s1
809; RV32I-NEXT:    mv a1, s2
810; RV32I-NEXT:    mv a2, s1
811; RV32I-NEXT:    mv a3, s2
812; RV32I-NEXT:    call __unorddf2@plt
813; RV32I-NEXT:    mv s4, s0
814; RV32I-NEXT:    bne a0, s0, .LBB12_6
815; RV32I-NEXT:  # %bb.5: # %start
816; RV32I-NEXT:    mv s4, s6
817; RV32I-NEXT:  .LBB12_6: # %start
818; RV32I-NEXT:    lui a3, 802304
819; RV32I-NEXT:    mv a0, s1
820; RV32I-NEXT:    mv a1, s2
821; RV32I-NEXT:    mv a2, s0
822; RV32I-NEXT:    call __gedf2@plt
823; RV32I-NEXT:    lui s7, 524288
824; RV32I-NEXT:    lui s6, 524288
825; RV32I-NEXT:    blt a0, s0, .LBB12_8
826; RV32I-NEXT:  # %bb.7: # %start
827; RV32I-NEXT:    mv s6, s5
828; RV32I-NEXT:  .LBB12_8: # %start
829; RV32I-NEXT:    li a2, -1
830; RV32I-NEXT:    mv a0, s1
831; RV32I-NEXT:    mv a1, s2
832; RV32I-NEXT:    mv a3, s3
833; RV32I-NEXT:    call __gtdf2@plt
834; RV32I-NEXT:    bge s0, a0, .LBB12_10
835; RV32I-NEXT:  # %bb.9:
836; RV32I-NEXT:    addi s6, s7, -1
837; RV32I-NEXT:  .LBB12_10: # %start
838; RV32I-NEXT:    mv a0, s1
839; RV32I-NEXT:    mv a1, s2
840; RV32I-NEXT:    mv a2, s1
841; RV32I-NEXT:    mv a3, s2
842; RV32I-NEXT:    call __unorddf2@plt
843; RV32I-NEXT:    bne a0, s0, .LBB12_12
844; RV32I-NEXT:  # %bb.11: # %start
845; RV32I-NEXT:    mv s0, s6
846; RV32I-NEXT:  .LBB12_12: # %start
847; RV32I-NEXT:    mv a0, s4
848; RV32I-NEXT:    mv a1, s0
849; RV32I-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
850; RV32I-NEXT:    lw s0, 40(sp) # 4-byte Folded Reload
851; RV32I-NEXT:    lw s1, 36(sp) # 4-byte Folded Reload
852; RV32I-NEXT:    lw s2, 32(sp) # 4-byte Folded Reload
853; RV32I-NEXT:    lw s3, 28(sp) # 4-byte Folded Reload
854; RV32I-NEXT:    lw s4, 24(sp) # 4-byte Folded Reload
855; RV32I-NEXT:    lw s5, 20(sp) # 4-byte Folded Reload
856; RV32I-NEXT:    lw s6, 16(sp) # 4-byte Folded Reload
857; RV32I-NEXT:    lw s7, 12(sp) # 4-byte Folded Reload
858; RV32I-NEXT:    addi sp, sp, 48
859; RV32I-NEXT:    ret
860;
861; RV64I-LABEL: fcvt_l_d_sat:
862; RV64I:       # %bb.0: # %start
863; RV64I-NEXT:    addi sp, sp, -48
864; RV64I-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
865; RV64I-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
866; RV64I-NEXT:    sd s1, 24(sp) # 8-byte Folded Spill
867; RV64I-NEXT:    sd s2, 16(sp) # 8-byte Folded Spill
868; RV64I-NEXT:    sd s3, 8(sp) # 8-byte Folded Spill
869; RV64I-NEXT:    sd s4, 0(sp) # 8-byte Folded Spill
870; RV64I-NEXT:    mv s0, a0
871; RV64I-NEXT:    li a0, -481
872; RV64I-NEXT:    slli a1, a0, 53
873; RV64I-NEXT:    mv a0, s0
874; RV64I-NEXT:    call __gedf2@plt
875; RV64I-NEXT:    mv s3, a0
876; RV64I-NEXT:    mv a0, s0
877; RV64I-NEXT:    call __fixdfdi@plt
878; RV64I-NEXT:    li s1, 0
879; RV64I-NEXT:    li s4, -1
880; RV64I-NEXT:    bltz s3, .LBB12_2
881; RV64I-NEXT:  # %bb.1: # %start
882; RV64I-NEXT:    mv s2, a0
883; RV64I-NEXT:    j .LBB12_3
884; RV64I-NEXT:  .LBB12_2:
885; RV64I-NEXT:    slli s2, s4, 63
886; RV64I-NEXT:  .LBB12_3: # %start
887; RV64I-NEXT:    li a0, 543
888; RV64I-NEXT:    slli a0, a0, 53
889; RV64I-NEXT:    addi a1, a0, -1
890; RV64I-NEXT:    mv a0, s0
891; RV64I-NEXT:    call __gtdf2@plt
892; RV64I-NEXT:    bge s1, a0, .LBB12_5
893; RV64I-NEXT:  # %bb.4:
894; RV64I-NEXT:    srli s2, s4, 1
895; RV64I-NEXT:  .LBB12_5: # %start
896; RV64I-NEXT:    mv a0, s0
897; RV64I-NEXT:    mv a1, s0
898; RV64I-NEXT:    call __unorddf2@plt
899; RV64I-NEXT:    bne a0, s1, .LBB12_7
900; RV64I-NEXT:  # %bb.6: # %start
901; RV64I-NEXT:    mv s1, s2
902; RV64I-NEXT:  .LBB12_7: # %start
903; RV64I-NEXT:    mv a0, s1
904; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
905; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
906; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
907; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
908; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
909; RV64I-NEXT:    ld s4, 0(sp) # 8-byte Folded Reload
910; RV64I-NEXT:    addi sp, sp, 48
911; RV64I-NEXT:    ret
912start:
913  %0 = tail call i64 @llvm.fptosi.sat.i64.f64(double %a)
914  ret i64 %0
915}
916declare i64 @llvm.fptosi.sat.i64.f64(double)
917
918define i64 @fcvt_lu_d(double %a) nounwind {
919; RV32IFD-LABEL: fcvt_lu_d:
920; RV32IFD:       # %bb.0:
921; RV32IFD-NEXT:    addi sp, sp, -16
922; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
923; RV32IFD-NEXT:    call __fixunsdfdi@plt
924; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
925; RV32IFD-NEXT:    addi sp, sp, 16
926; RV32IFD-NEXT:    ret
927;
928; RV64IFD-LABEL: fcvt_lu_d:
929; RV64IFD:       # %bb.0:
930; RV64IFD-NEXT:    fmv.d.x ft0, a0
931; RV64IFD-NEXT:    fcvt.lu.d a0, ft0, rtz
932; RV64IFD-NEXT:    ret
933;
934; RV32I-LABEL: fcvt_lu_d:
935; RV32I:       # %bb.0:
936; RV32I-NEXT:    addi sp, sp, -16
937; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
938; RV32I-NEXT:    call __fixunsdfdi@plt
939; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
940; RV32I-NEXT:    addi sp, sp, 16
941; RV32I-NEXT:    ret
942;
943; RV64I-LABEL: fcvt_lu_d:
944; RV64I:       # %bb.0:
945; RV64I-NEXT:    addi sp, sp, -16
946; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
947; RV64I-NEXT:    call __fixunsdfdi@plt
948; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
949; RV64I-NEXT:    addi sp, sp, 16
950; RV64I-NEXT:    ret
951  %1 = fptoui double %a to i64
952  ret i64 %1
953}
954
955define i64 @fcvt_lu_d_sat(double %a) nounwind {
956; RV32IFD-LABEL: fcvt_lu_d_sat:
957; RV32IFD:       # %bb.0: # %start
958; RV32IFD-NEXT:    addi sp, sp, -32
959; RV32IFD-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
960; RV32IFD-NEXT:    sw a0, 16(sp)
961; RV32IFD-NEXT:    sw a1, 20(sp)
962; RV32IFD-NEXT:    fld ft0, 16(sp)
963; RV32IFD-NEXT:    fsd ft0, 8(sp) # 8-byte Folded Spill
964; RV32IFD-NEXT:    call __fixunsdfdi@plt
965; RV32IFD-NEXT:    fld ft1, 8(sp) # 8-byte Folded Reload
966; RV32IFD-NEXT:    fcvt.d.w ft0, zero
967; RV32IFD-NEXT:    fle.d a4, ft0, ft1
968; RV32IFD-NEXT:    mv a3, a0
969; RV32IFD-NEXT:    bnez a4, .LBB14_2
970; RV32IFD-NEXT:  # %bb.1: # %start
971; RV32IFD-NEXT:    li a3, 0
972; RV32IFD-NEXT:  .LBB14_2: # %start
973; RV32IFD-NEXT:    lui a0, %hi(.LCPI14_0)
974; RV32IFD-NEXT:    fld ft0, %lo(.LCPI14_0)(a0)
975; RV32IFD-NEXT:    flt.d a5, ft0, ft1
976; RV32IFD-NEXT:    li a2, -1
977; RV32IFD-NEXT:    li a0, -1
978; RV32IFD-NEXT:    beqz a5, .LBB14_7
979; RV32IFD-NEXT:  # %bb.3: # %start
980; RV32IFD-NEXT:    beqz a4, .LBB14_8
981; RV32IFD-NEXT:  .LBB14_4: # %start
982; RV32IFD-NEXT:    bnez a5, .LBB14_6
983; RV32IFD-NEXT:  .LBB14_5: # %start
984; RV32IFD-NEXT:    mv a2, a1
985; RV32IFD-NEXT:  .LBB14_6: # %start
986; RV32IFD-NEXT:    mv a1, a2
987; RV32IFD-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
988; RV32IFD-NEXT:    addi sp, sp, 32
989; RV32IFD-NEXT:    ret
990; RV32IFD-NEXT:  .LBB14_7: # %start
991; RV32IFD-NEXT:    mv a0, a3
992; RV32IFD-NEXT:    bnez a4, .LBB14_4
993; RV32IFD-NEXT:  .LBB14_8: # %start
994; RV32IFD-NEXT:    li a1, 0
995; RV32IFD-NEXT:    beqz a5, .LBB14_5
996; RV32IFD-NEXT:    j .LBB14_6
997;
998; RV64IFD-LABEL: fcvt_lu_d_sat:
999; RV64IFD:       # %bb.0: # %start
1000; RV64IFD-NEXT:    fmv.d.x ft0, a0
1001; RV64IFD-NEXT:    feq.d a0, ft0, ft0
1002; RV64IFD-NEXT:    bnez a0, .LBB14_2
1003; RV64IFD-NEXT:  # %bb.1: # %start
1004; RV64IFD-NEXT:    li a0, 0
1005; RV64IFD-NEXT:    ret
1006; RV64IFD-NEXT:  .LBB14_2:
1007; RV64IFD-NEXT:    fcvt.lu.d a0, ft0, rtz
1008; RV64IFD-NEXT:    ret
1009;
1010; RV32I-LABEL: fcvt_lu_d_sat:
1011; RV32I:       # %bb.0: # %start
1012; RV32I-NEXT:    addi sp, sp, -32
1013; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
1014; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
1015; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
1016; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
1017; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
1018; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
1019; RV32I-NEXT:    sw s5, 4(sp) # 4-byte Folded Spill
1020; RV32I-NEXT:    sw s6, 0(sp) # 4-byte Folded Spill
1021; RV32I-NEXT:    mv s1, a1
1022; RV32I-NEXT:    mv s0, a0
1023; RV32I-NEXT:    lui a0, 278272
1024; RV32I-NEXT:    addi s3, a0, -1
1025; RV32I-NEXT:    li a2, -1
1026; RV32I-NEXT:    li s2, -1
1027; RV32I-NEXT:    mv a0, s0
1028; RV32I-NEXT:    mv a3, s3
1029; RV32I-NEXT:    call __gtdf2@plt
1030; RV32I-NEXT:    mv s6, a0
1031; RV32I-NEXT:    mv a0, s0
1032; RV32I-NEXT:    mv a1, s1
1033; RV32I-NEXT:    li a2, 0
1034; RV32I-NEXT:    li a3, 0
1035; RV32I-NEXT:    call __gedf2@plt
1036; RV32I-NEXT:    mv s4, a0
1037; RV32I-NEXT:    mv a0, s0
1038; RV32I-NEXT:    mv a1, s1
1039; RV32I-NEXT:    call __fixunsdfdi@plt
1040; RV32I-NEXT:    mv s5, a1
1041; RV32I-NEXT:    li a1, 0
1042; RV32I-NEXT:    bltz s4, .LBB14_2
1043; RV32I-NEXT:  # %bb.1: # %start
1044; RV32I-NEXT:    mv a1, a0
1045; RV32I-NEXT:  .LBB14_2: # %start
1046; RV32I-NEXT:    li s4, -1
1047; RV32I-NEXT:    bgtz s6, .LBB14_4
1048; RV32I-NEXT:  # %bb.3: # %start
1049; RV32I-NEXT:    mv s4, a1
1050; RV32I-NEXT:  .LBB14_4: # %start
1051; RV32I-NEXT:    li a2, -1
1052; RV32I-NEXT:    mv a0, s0
1053; RV32I-NEXT:    mv a1, s1
1054; RV32I-NEXT:    mv a3, s3
1055; RV32I-NEXT:    call __gtdf2@plt
1056; RV32I-NEXT:    mv s3, a0
1057; RV32I-NEXT:    mv a0, s0
1058; RV32I-NEXT:    mv a1, s1
1059; RV32I-NEXT:    li a2, 0
1060; RV32I-NEXT:    li a3, 0
1061; RV32I-NEXT:    call __gedf2@plt
1062; RV32I-NEXT:    li a1, 0
1063; RV32I-NEXT:    bltz a0, .LBB14_6
1064; RV32I-NEXT:  # %bb.5: # %start
1065; RV32I-NEXT:    mv a1, s5
1066; RV32I-NEXT:  .LBB14_6: # %start
1067; RV32I-NEXT:    bgtz s3, .LBB14_8
1068; RV32I-NEXT:  # %bb.7: # %start
1069; RV32I-NEXT:    mv s2, a1
1070; RV32I-NEXT:  .LBB14_8: # %start
1071; RV32I-NEXT:    mv a0, s4
1072; RV32I-NEXT:    mv a1, s2
1073; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
1074; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
1075; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
1076; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
1077; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
1078; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
1079; RV32I-NEXT:    lw s5, 4(sp) # 4-byte Folded Reload
1080; RV32I-NEXT:    lw s6, 0(sp) # 4-byte Folded Reload
1081; RV32I-NEXT:    addi sp, sp, 32
1082; RV32I-NEXT:    ret
1083;
1084; RV64I-LABEL: fcvt_lu_d_sat:
1085; RV64I:       # %bb.0: # %start
1086; RV64I-NEXT:    addi sp, sp, -32
1087; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
1088; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
1089; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
1090; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
1091; RV64I-NEXT:    mv s0, a0
1092; RV64I-NEXT:    li a1, 0
1093; RV64I-NEXT:    call __gedf2@plt
1094; RV64I-NEXT:    mv s1, a0
1095; RV64I-NEXT:    mv a0, s0
1096; RV64I-NEXT:    call __fixunsdfdi@plt
1097; RV64I-NEXT:    li s2, 0
1098; RV64I-NEXT:    bltz s1, .LBB14_2
1099; RV64I-NEXT:  # %bb.1: # %start
1100; RV64I-NEXT:    mv s2, a0
1101; RV64I-NEXT:  .LBB14_2: # %start
1102; RV64I-NEXT:    li a0, 1087
1103; RV64I-NEXT:    slli a0, a0, 52
1104; RV64I-NEXT:    addi a1, a0, -1
1105; RV64I-NEXT:    mv a0, s0
1106; RV64I-NEXT:    call __gtdf2@plt
1107; RV64I-NEXT:    mv a1, a0
1108; RV64I-NEXT:    li a0, -1
1109; RV64I-NEXT:    bgtz a1, .LBB14_4
1110; RV64I-NEXT:  # %bb.3: # %start
1111; RV64I-NEXT:    mv a0, s2
1112; RV64I-NEXT:  .LBB14_4: # %start
1113; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
1114; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
1115; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
1116; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
1117; RV64I-NEXT:    addi sp, sp, 32
1118; RV64I-NEXT:    ret
1119start:
1120  %0 = tail call i64 @llvm.fptoui.sat.i64.f64(double %a)
1121  ret i64 %0
1122}
1123declare i64 @llvm.fptoui.sat.i64.f64(double)
1124
1125define i64 @fmv_x_d(double %a, double %b) nounwind {
1126; RV32IFD-LABEL: fmv_x_d:
1127; RV32IFD:       # %bb.0:
1128; RV32IFD-NEXT:    addi sp, sp, -16
1129; RV32IFD-NEXT:    sw a2, 0(sp)
1130; RV32IFD-NEXT:    sw a3, 4(sp)
1131; RV32IFD-NEXT:    fld ft0, 0(sp)
1132; RV32IFD-NEXT:    sw a0, 0(sp)
1133; RV32IFD-NEXT:    sw a1, 4(sp)
1134; RV32IFD-NEXT:    fld ft1, 0(sp)
1135; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0
1136; RV32IFD-NEXT:    fsd ft0, 8(sp)
1137; RV32IFD-NEXT:    lw a0, 8(sp)
1138; RV32IFD-NEXT:    lw a1, 12(sp)
1139; RV32IFD-NEXT:    addi sp, sp, 16
1140; RV32IFD-NEXT:    ret
1141;
1142; RV64IFD-LABEL: fmv_x_d:
1143; RV64IFD:       # %bb.0:
1144; RV64IFD-NEXT:    fmv.d.x ft0, a1
1145; RV64IFD-NEXT:    fmv.d.x ft1, a0
1146; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0
1147; RV64IFD-NEXT:    fmv.x.d a0, ft0
1148; RV64IFD-NEXT:    ret
1149;
1150; RV32I-LABEL: fmv_x_d:
1151; RV32I:       # %bb.0:
1152; RV32I-NEXT:    addi sp, sp, -16
1153; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1154; RV32I-NEXT:    call __adddf3@plt
1155; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1156; RV32I-NEXT:    addi sp, sp, 16
1157; RV32I-NEXT:    ret
1158;
1159; RV64I-LABEL: fmv_x_d:
1160; RV64I:       # %bb.0:
1161; RV64I-NEXT:    addi sp, sp, -16
1162; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1163; RV64I-NEXT:    call __adddf3@plt
1164; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1165; RV64I-NEXT:    addi sp, sp, 16
1166; RV64I-NEXT:    ret
1167  %1 = fadd double %a, %b
1168  %2 = bitcast double %1 to i64
1169  ret i64 %2
1170}
1171
1172define double @fcvt_d_l(i64 %a) nounwind {
1173; RV32IFD-LABEL: fcvt_d_l:
1174; RV32IFD:       # %bb.0:
1175; RV32IFD-NEXT:    addi sp, sp, -16
1176; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1177; RV32IFD-NEXT:    call __floatdidf@plt
1178; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1179; RV32IFD-NEXT:    addi sp, sp, 16
1180; RV32IFD-NEXT:    ret
1181;
1182; RV64IFD-LABEL: fcvt_d_l:
1183; RV64IFD:       # %bb.0:
1184; RV64IFD-NEXT:    fcvt.d.l ft0, a0
1185; RV64IFD-NEXT:    fmv.x.d a0, ft0
1186; RV64IFD-NEXT:    ret
1187;
1188; RV32I-LABEL: fcvt_d_l:
1189; RV32I:       # %bb.0:
1190; RV32I-NEXT:    addi sp, sp, -16
1191; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1192; RV32I-NEXT:    call __floatdidf@plt
1193; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1194; RV32I-NEXT:    addi sp, sp, 16
1195; RV32I-NEXT:    ret
1196;
1197; RV64I-LABEL: fcvt_d_l:
1198; RV64I:       # %bb.0:
1199; RV64I-NEXT:    addi sp, sp, -16
1200; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1201; RV64I-NEXT:    call __floatdidf@plt
1202; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1203; RV64I-NEXT:    addi sp, sp, 16
1204; RV64I-NEXT:    ret
1205  %1 = sitofp i64 %a to double
1206  ret double %1
1207}
1208
1209define double @fcvt_d_lu(i64 %a) nounwind {
1210; RV32IFD-LABEL: fcvt_d_lu:
1211; RV32IFD:       # %bb.0:
1212; RV32IFD-NEXT:    addi sp, sp, -16
1213; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1214; RV32IFD-NEXT:    call __floatundidf@plt
1215; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1216; RV32IFD-NEXT:    addi sp, sp, 16
1217; RV32IFD-NEXT:    ret
1218;
1219; RV64IFD-LABEL: fcvt_d_lu:
1220; RV64IFD:       # %bb.0:
1221; RV64IFD-NEXT:    fcvt.d.lu ft0, a0
1222; RV64IFD-NEXT:    fmv.x.d a0, ft0
1223; RV64IFD-NEXT:    ret
1224;
1225; RV32I-LABEL: fcvt_d_lu:
1226; RV32I:       # %bb.0:
1227; RV32I-NEXT:    addi sp, sp, -16
1228; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1229; RV32I-NEXT:    call __floatundidf@plt
1230; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1231; RV32I-NEXT:    addi sp, sp, 16
1232; RV32I-NEXT:    ret
1233;
1234; RV64I-LABEL: fcvt_d_lu:
1235; RV64I:       # %bb.0:
1236; RV64I-NEXT:    addi sp, sp, -16
1237; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1238; RV64I-NEXT:    call __floatundidf@plt
1239; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1240; RV64I-NEXT:    addi sp, sp, 16
1241; RV64I-NEXT:    ret
1242  %1 = uitofp i64 %a to double
1243  ret double %1
1244}
1245
1246define double @fmv_d_x(i64 %a, i64 %b) nounwind {
1247; Ensure fmv.w.x is generated even for a soft double calling convention
1248; RV32IFD-LABEL: fmv_d_x:
1249; RV32IFD:       # %bb.0:
1250; RV32IFD-NEXT:    addi sp, sp, -32
1251; RV32IFD-NEXT:    sw a3, 20(sp)
1252; RV32IFD-NEXT:    sw a2, 16(sp)
1253; RV32IFD-NEXT:    sw a1, 28(sp)
1254; RV32IFD-NEXT:    sw a0, 24(sp)
1255; RV32IFD-NEXT:    fld ft0, 16(sp)
1256; RV32IFD-NEXT:    fld ft1, 24(sp)
1257; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0
1258; RV32IFD-NEXT:    fsd ft0, 8(sp)
1259; RV32IFD-NEXT:    lw a0, 8(sp)
1260; RV32IFD-NEXT:    lw a1, 12(sp)
1261; RV32IFD-NEXT:    addi sp, sp, 32
1262; RV32IFD-NEXT:    ret
1263;
1264; RV64IFD-LABEL: fmv_d_x:
1265; RV64IFD:       # %bb.0:
1266; RV64IFD-NEXT:    fmv.d.x ft0, a0
1267; RV64IFD-NEXT:    fmv.d.x ft1, a1
1268; RV64IFD-NEXT:    fadd.d ft0, ft0, ft1
1269; RV64IFD-NEXT:    fmv.x.d a0, ft0
1270; RV64IFD-NEXT:    ret
1271;
1272; RV32I-LABEL: fmv_d_x:
1273; RV32I:       # %bb.0:
1274; RV32I-NEXT:    addi sp, sp, -16
1275; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1276; RV32I-NEXT:    call __adddf3@plt
1277; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1278; RV32I-NEXT:    addi sp, sp, 16
1279; RV32I-NEXT:    ret
1280;
1281; RV64I-LABEL: fmv_d_x:
1282; RV64I:       # %bb.0:
1283; RV64I-NEXT:    addi sp, sp, -16
1284; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1285; RV64I-NEXT:    call __adddf3@plt
1286; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1287; RV64I-NEXT:    addi sp, sp, 16
1288; RV64I-NEXT:    ret
1289  %1 = bitcast i64 %a to double
1290  %2 = bitcast i64 %b to double
1291  %3 = fadd double %1, %2
1292  ret double %3
1293}
1294
1295define double @fcvt_d_w_i8(i8 signext %a) nounwind {
1296; RV32IFD-LABEL: fcvt_d_w_i8:
1297; RV32IFD:       # %bb.0:
1298; RV32IFD-NEXT:    addi sp, sp, -16
1299; RV32IFD-NEXT:    fcvt.d.w ft0, a0
1300; RV32IFD-NEXT:    fsd ft0, 8(sp)
1301; RV32IFD-NEXT:    lw a0, 8(sp)
1302; RV32IFD-NEXT:    lw a1, 12(sp)
1303; RV32IFD-NEXT:    addi sp, sp, 16
1304; RV32IFD-NEXT:    ret
1305;
1306; RV64IFD-LABEL: fcvt_d_w_i8:
1307; RV64IFD:       # %bb.0:
1308; RV64IFD-NEXT:    fcvt.d.w ft0, a0
1309; RV64IFD-NEXT:    fmv.x.d a0, ft0
1310; RV64IFD-NEXT:    ret
1311;
1312; RV32I-LABEL: fcvt_d_w_i8:
1313; RV32I:       # %bb.0:
1314; RV32I-NEXT:    addi sp, sp, -16
1315; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1316; RV32I-NEXT:    call __floatsidf@plt
1317; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1318; RV32I-NEXT:    addi sp, sp, 16
1319; RV32I-NEXT:    ret
1320;
1321; RV64I-LABEL: fcvt_d_w_i8:
1322; RV64I:       # %bb.0:
1323; RV64I-NEXT:    addi sp, sp, -16
1324; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1325; RV64I-NEXT:    call __floatsidf@plt
1326; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1327; RV64I-NEXT:    addi sp, sp, 16
1328; RV64I-NEXT:    ret
1329  %1 = sitofp i8 %a to double
1330  ret double %1
1331}
1332
1333define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind {
1334; RV32IFD-LABEL: fcvt_d_wu_i8:
1335; RV32IFD:       # %bb.0:
1336; RV32IFD-NEXT:    addi sp, sp, -16
1337; RV32IFD-NEXT:    fcvt.d.wu ft0, a0
1338; RV32IFD-NEXT:    fsd ft0, 8(sp)
1339; RV32IFD-NEXT:    lw a0, 8(sp)
1340; RV32IFD-NEXT:    lw a1, 12(sp)
1341; RV32IFD-NEXT:    addi sp, sp, 16
1342; RV32IFD-NEXT:    ret
1343;
1344; RV64IFD-LABEL: fcvt_d_wu_i8:
1345; RV64IFD:       # %bb.0:
1346; RV64IFD-NEXT:    fcvt.d.wu ft0, a0
1347; RV64IFD-NEXT:    fmv.x.d a0, ft0
1348; RV64IFD-NEXT:    ret
1349;
1350; RV32I-LABEL: fcvt_d_wu_i8:
1351; RV32I:       # %bb.0:
1352; RV32I-NEXT:    addi sp, sp, -16
1353; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1354; RV32I-NEXT:    call __floatunsidf@plt
1355; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1356; RV32I-NEXT:    addi sp, sp, 16
1357; RV32I-NEXT:    ret
1358;
1359; RV64I-LABEL: fcvt_d_wu_i8:
1360; RV64I:       # %bb.0:
1361; RV64I-NEXT:    addi sp, sp, -16
1362; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1363; RV64I-NEXT:    call __floatunsidf@plt
1364; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1365; RV64I-NEXT:    addi sp, sp, 16
1366; RV64I-NEXT:    ret
1367  %1 = uitofp i8 %a to double
1368  ret double %1
1369}
1370
1371define double @fcvt_d_w_i16(i16 signext %a) nounwind {
1372; RV32IFD-LABEL: fcvt_d_w_i16:
1373; RV32IFD:       # %bb.0:
1374; RV32IFD-NEXT:    addi sp, sp, -16
1375; RV32IFD-NEXT:    fcvt.d.w ft0, a0
1376; RV32IFD-NEXT:    fsd ft0, 8(sp)
1377; RV32IFD-NEXT:    lw a0, 8(sp)
1378; RV32IFD-NEXT:    lw a1, 12(sp)
1379; RV32IFD-NEXT:    addi sp, sp, 16
1380; RV32IFD-NEXT:    ret
1381;
1382; RV64IFD-LABEL: fcvt_d_w_i16:
1383; RV64IFD:       # %bb.0:
1384; RV64IFD-NEXT:    fcvt.d.w ft0, a0
1385; RV64IFD-NEXT:    fmv.x.d a0, ft0
1386; RV64IFD-NEXT:    ret
1387;
1388; RV32I-LABEL: fcvt_d_w_i16:
1389; RV32I:       # %bb.0:
1390; RV32I-NEXT:    addi sp, sp, -16
1391; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1392; RV32I-NEXT:    call __floatsidf@plt
1393; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1394; RV32I-NEXT:    addi sp, sp, 16
1395; RV32I-NEXT:    ret
1396;
1397; RV64I-LABEL: fcvt_d_w_i16:
1398; RV64I:       # %bb.0:
1399; RV64I-NEXT:    addi sp, sp, -16
1400; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1401; RV64I-NEXT:    call __floatsidf@plt
1402; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1403; RV64I-NEXT:    addi sp, sp, 16
1404; RV64I-NEXT:    ret
1405  %1 = sitofp i16 %a to double
1406  ret double %1
1407}
1408
1409define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind {
1410; RV32IFD-LABEL: fcvt_d_wu_i16:
1411; RV32IFD:       # %bb.0:
1412; RV32IFD-NEXT:    addi sp, sp, -16
1413; RV32IFD-NEXT:    fcvt.d.wu ft0, a0
1414; RV32IFD-NEXT:    fsd ft0, 8(sp)
1415; RV32IFD-NEXT:    lw a0, 8(sp)
1416; RV32IFD-NEXT:    lw a1, 12(sp)
1417; RV32IFD-NEXT:    addi sp, sp, 16
1418; RV32IFD-NEXT:    ret
1419;
1420; RV64IFD-LABEL: fcvt_d_wu_i16:
1421; RV64IFD:       # %bb.0:
1422; RV64IFD-NEXT:    fcvt.d.wu ft0, a0
1423; RV64IFD-NEXT:    fmv.x.d a0, ft0
1424; RV64IFD-NEXT:    ret
1425;
1426; RV32I-LABEL: fcvt_d_wu_i16:
1427; RV32I:       # %bb.0:
1428; RV32I-NEXT:    addi sp, sp, -16
1429; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1430; RV32I-NEXT:    call __floatunsidf@plt
1431; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1432; RV32I-NEXT:    addi sp, sp, 16
1433; RV32I-NEXT:    ret
1434;
1435; RV64I-LABEL: fcvt_d_wu_i16:
1436; RV64I:       # %bb.0:
1437; RV64I-NEXT:    addi sp, sp, -16
1438; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1439; RV64I-NEXT:    call __floatunsidf@plt
1440; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1441; RV64I-NEXT:    addi sp, sp, 16
1442; RV64I-NEXT:    ret
1443  %1 = uitofp i16 %a to double
1444  ret double %1
1445}
1446
1447; Make sure we select W version of addi on RV64.
1448define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, double* %1) {
1449; RV32IFD-LABEL: fcvt_d_w_demanded_bits:
1450; RV32IFD:       # %bb.0:
1451; RV32IFD-NEXT:    addi a0, a0, 1
1452; RV32IFD-NEXT:    fcvt.d.w ft0, a0
1453; RV32IFD-NEXT:    fsd ft0, 0(a1)
1454; RV32IFD-NEXT:    ret
1455;
1456; RV64IFD-LABEL: fcvt_d_w_demanded_bits:
1457; RV64IFD:       # %bb.0:
1458; RV64IFD-NEXT:    addiw a0, a0, 1
1459; RV64IFD-NEXT:    fcvt.d.w ft0, a0
1460; RV64IFD-NEXT:    fsd ft0, 0(a1)
1461; RV64IFD-NEXT:    ret
1462;
1463; RV32I-LABEL: fcvt_d_w_demanded_bits:
1464; RV32I:       # %bb.0:
1465; RV32I-NEXT:    addi sp, sp, -16
1466; RV32I-NEXT:    .cfi_def_cfa_offset 16
1467; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1468; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
1469; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
1470; RV32I-NEXT:    .cfi_offset ra, -4
1471; RV32I-NEXT:    .cfi_offset s0, -8
1472; RV32I-NEXT:    .cfi_offset s1, -12
1473; RV32I-NEXT:    mv s0, a1
1474; RV32I-NEXT:    addi s1, a0, 1
1475; RV32I-NEXT:    mv a0, s1
1476; RV32I-NEXT:    call __floatsidf@plt
1477; RV32I-NEXT:    sw a1, 4(s0)
1478; RV32I-NEXT:    sw a0, 0(s0)
1479; RV32I-NEXT:    mv a0, s1
1480; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1481; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
1482; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
1483; RV32I-NEXT:    addi sp, sp, 16
1484; RV32I-NEXT:    ret
1485;
1486; RV64I-LABEL: fcvt_d_w_demanded_bits:
1487; RV64I:       # %bb.0:
1488; RV64I-NEXT:    addi sp, sp, -32
1489; RV64I-NEXT:    .cfi_def_cfa_offset 32
1490; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
1491; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
1492; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
1493; RV64I-NEXT:    .cfi_offset ra, -8
1494; RV64I-NEXT:    .cfi_offset s0, -16
1495; RV64I-NEXT:    .cfi_offset s1, -24
1496; RV64I-NEXT:    mv s0, a1
1497; RV64I-NEXT:    addiw s1, a0, 1
1498; RV64I-NEXT:    mv a0, s1
1499; RV64I-NEXT:    call __floatsidf@plt
1500; RV64I-NEXT:    sd a0, 0(s0)
1501; RV64I-NEXT:    mv a0, s1
1502; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
1503; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
1504; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
1505; RV64I-NEXT:    addi sp, sp, 32
1506; RV64I-NEXT:    ret
1507  %3 = add i32 %0, 1
1508  %4 = sitofp i32 %3 to double
1509  store double %4, double* %1, align 8
1510  ret i32 %3
1511}
1512
1513; Make sure we select W version of addi on RV64.
1514define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, double* %1) {
1515; RV32IFD-LABEL: fcvt_d_wu_demanded_bits:
1516; RV32IFD:       # %bb.0:
1517; RV32IFD-NEXT:    addi a0, a0, 1
1518; RV32IFD-NEXT:    fcvt.d.wu ft0, a0
1519; RV32IFD-NEXT:    fsd ft0, 0(a1)
1520; RV32IFD-NEXT:    ret
1521;
1522; RV64IFD-LABEL: fcvt_d_wu_demanded_bits:
1523; RV64IFD:       # %bb.0:
1524; RV64IFD-NEXT:    addiw a0, a0, 1
1525; RV64IFD-NEXT:    fcvt.d.wu ft0, a0
1526; RV64IFD-NEXT:    fsd ft0, 0(a1)
1527; RV64IFD-NEXT:    ret
1528;
1529; RV32I-LABEL: fcvt_d_wu_demanded_bits:
1530; RV32I:       # %bb.0:
1531; RV32I-NEXT:    addi sp, sp, -16
1532; RV32I-NEXT:    .cfi_def_cfa_offset 16
1533; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1534; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
1535; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
1536; RV32I-NEXT:    .cfi_offset ra, -4
1537; RV32I-NEXT:    .cfi_offset s0, -8
1538; RV32I-NEXT:    .cfi_offset s1, -12
1539; RV32I-NEXT:    mv s0, a1
1540; RV32I-NEXT:    addi s1, a0, 1
1541; RV32I-NEXT:    mv a0, s1
1542; RV32I-NEXT:    call __floatunsidf@plt
1543; RV32I-NEXT:    sw a1, 4(s0)
1544; RV32I-NEXT:    sw a0, 0(s0)
1545; RV32I-NEXT:    mv a0, s1
1546; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1547; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
1548; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
1549; RV32I-NEXT:    addi sp, sp, 16
1550; RV32I-NEXT:    ret
1551;
1552; RV64I-LABEL: fcvt_d_wu_demanded_bits:
1553; RV64I:       # %bb.0:
1554; RV64I-NEXT:    addi sp, sp, -32
1555; RV64I-NEXT:    .cfi_def_cfa_offset 32
1556; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
1557; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
1558; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
1559; RV64I-NEXT:    .cfi_offset ra, -8
1560; RV64I-NEXT:    .cfi_offset s0, -16
1561; RV64I-NEXT:    .cfi_offset s1, -24
1562; RV64I-NEXT:    mv s0, a1
1563; RV64I-NEXT:    addiw s1, a0, 1
1564; RV64I-NEXT:    mv a0, s1
1565; RV64I-NEXT:    call __floatunsidf@plt
1566; RV64I-NEXT:    sd a0, 0(s0)
1567; RV64I-NEXT:    mv a0, s1
1568; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
1569; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
1570; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
1571; RV64I-NEXT:    addi sp, sp, 32
1572; RV64I-NEXT:    ret
1573  %3 = add i32 %0, 1
1574  %4 = uitofp i32 %3 to double
1575  store double %4, double* %1, align 8
1576  ret i32 %3
1577}
1578