1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32IFD %s
4; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV64IFD %s
6
7define float @fcvt_s_d(double %a) nounwind {
8; RV32IFD-LABEL: fcvt_s_d:
9; RV32IFD:       # %bb.0:
10; RV32IFD-NEXT:    addi sp, sp, -16
11; RV32IFD-NEXT:    sw a0, 8(sp)
12; RV32IFD-NEXT:    sw a1, 12(sp)
13; RV32IFD-NEXT:    fld ft0, 8(sp)
14; RV32IFD-NEXT:    fcvt.s.d ft0, ft0
15; RV32IFD-NEXT:    fmv.x.w a0, ft0
16; RV32IFD-NEXT:    addi sp, sp, 16
17; RV32IFD-NEXT:    ret
18;
19; RV64IFD-LABEL: fcvt_s_d:
20; RV64IFD:       # %bb.0:
21; RV64IFD-NEXT:    fmv.d.x ft0, a0
22; RV64IFD-NEXT:    fcvt.s.d ft0, ft0
23; RV64IFD-NEXT:    fmv.x.w a0, ft0
24; RV64IFD-NEXT:    ret
25  %1 = fptrunc double %a to float
26  ret float %1
27}
28
29define double @fcvt_d_s(float %a) nounwind {
30; RV32IFD-LABEL: fcvt_d_s:
31; RV32IFD:       # %bb.0:
32; RV32IFD-NEXT:    addi sp, sp, -16
33; RV32IFD-NEXT:    fmv.w.x ft0, a0
34; RV32IFD-NEXT:    fcvt.d.s ft0, ft0
35; RV32IFD-NEXT:    fsd ft0, 8(sp)
36; RV32IFD-NEXT:    lw a0, 8(sp)
37; RV32IFD-NEXT:    lw a1, 12(sp)
38; RV32IFD-NEXT:    addi sp, sp, 16
39; RV32IFD-NEXT:    ret
40;
41; RV64IFD-LABEL: fcvt_d_s:
42; RV64IFD:       # %bb.0:
43; RV64IFD-NEXT:    fmv.w.x ft0, a0
44; RV64IFD-NEXT:    fcvt.d.s ft0, ft0
45; RV64IFD-NEXT:    fmv.x.d a0, ft0
46; RV64IFD-NEXT:    ret
47  %1 = fpext float %a to double
48  ret double %1
49}
50
51; For RV64D, fcvt.l.d is semantically equivalent to fcvt.w.d in this case
52; because fptosi will produce poison if the result doesn't fit into an i32.
53define i32 @fcvt_w_d(double %a) nounwind {
54; RV32IFD-LABEL: fcvt_w_d:
55; RV32IFD:       # %bb.0:
56; RV32IFD-NEXT:    addi sp, sp, -16
57; RV32IFD-NEXT:    sw a0, 8(sp)
58; RV32IFD-NEXT:    sw a1, 12(sp)
59; RV32IFD-NEXT:    fld ft0, 8(sp)
60; RV32IFD-NEXT:    fcvt.w.d a0, ft0, rtz
61; RV32IFD-NEXT:    addi sp, sp, 16
62; RV32IFD-NEXT:    ret
63;
64; RV64IFD-LABEL: fcvt_w_d:
65; RV64IFD:       # %bb.0:
66; RV64IFD-NEXT:    fmv.d.x ft0, a0
67; RV64IFD-NEXT:    fcvt.l.d a0, ft0, rtz
68; RV64IFD-NEXT:    ret
69  %1 = fptosi double %a to i32
70  ret i32 %1
71}
72
73define i32 @fcvt_w_d_sat(double %a) nounwind {
74; RV32IFD-LABEL: fcvt_w_d_sat:
75; RV32IFD:       # %bb.0: # %start
76; RV32IFD-NEXT:    addi sp, sp, -16
77; RV32IFD-NEXT:    sw a0, 8(sp)
78; RV32IFD-NEXT:    sw a1, 12(sp)
79; RV32IFD-NEXT:    fld ft0, 8(sp)
80; RV32IFD-NEXT:    feq.d a0, ft0, ft0
81; RV32IFD-NEXT:    bnez a0, .LBB3_2
82; RV32IFD-NEXT:  # %bb.1: # %start
83; RV32IFD-NEXT:    mv a0, zero
84; RV32IFD-NEXT:    addi sp, sp, 16
85; RV32IFD-NEXT:    ret
86; RV32IFD-NEXT:  .LBB3_2:
87; RV32IFD-NEXT:    lui a0, %hi(.LCPI3_0)
88; RV32IFD-NEXT:    fld ft1, %lo(.LCPI3_0)(a0)
89; RV32IFD-NEXT:    lui a0, %hi(.LCPI3_1)
90; RV32IFD-NEXT:    fld ft2, %lo(.LCPI3_1)(a0)
91; RV32IFD-NEXT:    fmax.d ft0, ft0, ft1
92; RV32IFD-NEXT:    fmin.d ft0, ft0, ft2
93; RV32IFD-NEXT:    fcvt.w.d a0, ft0, rtz
94; RV32IFD-NEXT:    addi sp, sp, 16
95; RV32IFD-NEXT:    ret
96;
97; RV64IFD-LABEL: fcvt_w_d_sat:
98; RV64IFD:       # %bb.0: # %start
99; RV64IFD-NEXT:    fmv.d.x ft0, a0
100; RV64IFD-NEXT:    feq.d a0, ft0, ft0
101; RV64IFD-NEXT:    bnez a0, .LBB3_2
102; RV64IFD-NEXT:  # %bb.1: # %start
103; RV64IFD-NEXT:    mv a0, zero
104; RV64IFD-NEXT:    ret
105; RV64IFD-NEXT:  .LBB3_2:
106; RV64IFD-NEXT:    lui a0, %hi(.LCPI3_0)
107; RV64IFD-NEXT:    fld ft1, %lo(.LCPI3_0)(a0)
108; RV64IFD-NEXT:    lui a0, %hi(.LCPI3_1)
109; RV64IFD-NEXT:    fld ft2, %lo(.LCPI3_1)(a0)
110; RV64IFD-NEXT:    fmax.d ft0, ft0, ft1
111; RV64IFD-NEXT:    fmin.d ft0, ft0, ft2
112; RV64IFD-NEXT:    fcvt.l.d a0, ft0, rtz
113; RV64IFD-NEXT:    ret
114start:
115  %0 = tail call i32 @llvm.fptosi.sat.i32.f64(double %a)
116  ret i32 %0
117}
118declare i32 @llvm.fptosi.sat.i32.f64(double)
119
120; For RV64D, fcvt.lu.d is semantically equivalent to fcvt.wu.d in this case
121; because fptosi will produce poison if the result doesn't fit into an i32.
122define i32 @fcvt_wu_d(double %a) nounwind {
123; RV32IFD-LABEL: fcvt_wu_d:
124; RV32IFD:       # %bb.0:
125; RV32IFD-NEXT:    addi sp, sp, -16
126; RV32IFD-NEXT:    sw a0, 8(sp)
127; RV32IFD-NEXT:    sw a1, 12(sp)
128; RV32IFD-NEXT:    fld ft0, 8(sp)
129; RV32IFD-NEXT:    fcvt.wu.d a0, ft0, rtz
130; RV32IFD-NEXT:    addi sp, sp, 16
131; RV32IFD-NEXT:    ret
132;
133; RV64IFD-LABEL: fcvt_wu_d:
134; RV64IFD:       # %bb.0:
135; RV64IFD-NEXT:    fmv.d.x ft0, a0
136; RV64IFD-NEXT:    fcvt.lu.d a0, ft0, rtz
137; RV64IFD-NEXT:    ret
138  %1 = fptoui double %a to i32
139  ret i32 %1
140}
141
142define i32 @fcvt_wu_d_sat(double %a) nounwind {
143; RV32IFD-LABEL: fcvt_wu_d_sat:
144; RV32IFD:       # %bb.0: # %start
145; RV32IFD-NEXT:    addi sp, sp, -16
146; RV32IFD-NEXT:    sw a0, 8(sp)
147; RV32IFD-NEXT:    sw a1, 12(sp)
148; RV32IFD-NEXT:    fld ft0, 8(sp)
149; RV32IFD-NEXT:    lui a0, %hi(.LCPI5_0)
150; RV32IFD-NEXT:    fld ft1, %lo(.LCPI5_0)(a0)
151; RV32IFD-NEXT:    fcvt.d.w ft2, zero
152; RV32IFD-NEXT:    fmax.d ft0, ft0, ft2
153; RV32IFD-NEXT:    fmin.d ft0, ft0, ft1
154; RV32IFD-NEXT:    fcvt.wu.d a0, ft0, rtz
155; RV32IFD-NEXT:    addi sp, sp, 16
156; RV32IFD-NEXT:    ret
157;
158; RV64IFD-LABEL: fcvt_wu_d_sat:
159; RV64IFD:       # %bb.0: # %start
160; RV64IFD-NEXT:    lui a1, %hi(.LCPI5_0)
161; RV64IFD-NEXT:    fld ft0, %lo(.LCPI5_0)(a1)
162; RV64IFD-NEXT:    fmv.d.x ft1, a0
163; RV64IFD-NEXT:    fmv.d.x ft2, zero
164; RV64IFD-NEXT:    fmax.d ft1, ft1, ft2
165; RV64IFD-NEXT:    fmin.d ft0, ft1, ft0
166; RV64IFD-NEXT:    fcvt.lu.d a0, ft0, rtz
167; RV64IFD-NEXT:    ret
168start:
169  %0 = tail call i32 @llvm.fptoui.sat.i32.f64(double %a)
170  ret i32 %0
171}
172declare i32 @llvm.fptoui.sat.i32.f64(double)
173
174define double @fcvt_d_w(i32 %a) nounwind {
175; RV32IFD-LABEL: fcvt_d_w:
176; RV32IFD:       # %bb.0:
177; RV32IFD-NEXT:    addi sp, sp, -16
178; RV32IFD-NEXT:    fcvt.d.w ft0, a0
179; RV32IFD-NEXT:    fsd ft0, 8(sp)
180; RV32IFD-NEXT:    lw a0, 8(sp)
181; RV32IFD-NEXT:    lw a1, 12(sp)
182; RV32IFD-NEXT:    addi sp, sp, 16
183; RV32IFD-NEXT:    ret
184;
185; RV64IFD-LABEL: fcvt_d_w:
186; RV64IFD:       # %bb.0:
187; RV64IFD-NEXT:    fcvt.d.w ft0, a0
188; RV64IFD-NEXT:    fmv.x.d a0, ft0
189; RV64IFD-NEXT:    ret
190  %1 = sitofp i32 %a to double
191  ret double %1
192}
193
194define double @fcvt_d_wu(i32 %a) nounwind {
195; RV32IFD-LABEL: fcvt_d_wu:
196; RV32IFD:       # %bb.0:
197; RV32IFD-NEXT:    addi sp, sp, -16
198; RV32IFD-NEXT:    fcvt.d.wu ft0, a0
199; RV32IFD-NEXT:    fsd ft0, 8(sp)
200; RV32IFD-NEXT:    lw a0, 8(sp)
201; RV32IFD-NEXT:    lw a1, 12(sp)
202; RV32IFD-NEXT:    addi sp, sp, 16
203; RV32IFD-NEXT:    ret
204;
205; RV64IFD-LABEL: fcvt_d_wu:
206; RV64IFD:       # %bb.0:
207; RV64IFD-NEXT:    fcvt.d.wu ft0, a0
208; RV64IFD-NEXT:    fmv.x.d a0, ft0
209; RV64IFD-NEXT:    ret
210  %1 = uitofp i32 %a to double
211  ret double %1
212}
213
214define i64 @fcvt_l_d(double %a) nounwind {
215; RV32IFD-LABEL: fcvt_l_d:
216; RV32IFD:       # %bb.0:
217; RV32IFD-NEXT:    addi sp, sp, -16
218; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
219; RV32IFD-NEXT:    call __fixdfdi@plt
220; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
221; RV32IFD-NEXT:    addi sp, sp, 16
222; RV32IFD-NEXT:    ret
223;
224; RV64IFD-LABEL: fcvt_l_d:
225; RV64IFD:       # %bb.0:
226; RV64IFD-NEXT:    fmv.d.x ft0, a0
227; RV64IFD-NEXT:    fcvt.l.d a0, ft0, rtz
228; RV64IFD-NEXT:    ret
229  %1 = fptosi double %a to i64
230  ret i64 %1
231}
232
233define i64 @fcvt_l_d_sat(double %a) nounwind {
234; RV32IFD-LABEL: fcvt_l_d_sat:
235; RV32IFD:       # %bb.0: # %start
236; RV32IFD-NEXT:    addi sp, sp, -32
237; RV32IFD-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
238; RV32IFD-NEXT:    sw a0, 16(sp)
239; RV32IFD-NEXT:    sw a1, 20(sp)
240; RV32IFD-NEXT:    fld ft0, 16(sp)
241; RV32IFD-NEXT:    fsd ft0, 8(sp) # 8-byte Folded Spill
242; RV32IFD-NEXT:    call __fixdfdi@plt
243; RV32IFD-NEXT:    fld ft1, 8(sp) # 8-byte Folded Reload
244; RV32IFD-NEXT:    lui a2, %hi(.LCPI9_0)
245; RV32IFD-NEXT:    fld ft0, %lo(.LCPI9_0)(a2)
246; RV32IFD-NEXT:    fle.d a3, ft0, ft1
247; RV32IFD-NEXT:    mv a2, a0
248; RV32IFD-NEXT:    bnez a3, .LBB9_2
249; RV32IFD-NEXT:  # %bb.1: # %start
250; RV32IFD-NEXT:    mv a2, zero
251; RV32IFD-NEXT:  .LBB9_2: # %start
252; RV32IFD-NEXT:    lui a0, %hi(.LCPI9_1)
253; RV32IFD-NEXT:    fld ft0, %lo(.LCPI9_1)(a0)
254; RV32IFD-NEXT:    flt.d a4, ft0, ft1
255; RV32IFD-NEXT:    addi a0, zero, -1
256; RV32IFD-NEXT:    beqz a4, .LBB9_9
257; RV32IFD-NEXT:  # %bb.3: # %start
258; RV32IFD-NEXT:    feq.d a2, ft1, ft1
259; RV32IFD-NEXT:    beqz a2, .LBB9_10
260; RV32IFD-NEXT:  .LBB9_4: # %start
261; RV32IFD-NEXT:    lui a5, 524288
262; RV32IFD-NEXT:    beqz a3, .LBB9_11
263; RV32IFD-NEXT:  .LBB9_5: # %start
264; RV32IFD-NEXT:    bnez a4, .LBB9_12
265; RV32IFD-NEXT:  .LBB9_6: # %start
266; RV32IFD-NEXT:    bnez a2, .LBB9_8
267; RV32IFD-NEXT:  .LBB9_7: # %start
268; RV32IFD-NEXT:    mv a1, zero
269; RV32IFD-NEXT:  .LBB9_8: # %start
270; RV32IFD-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
271; RV32IFD-NEXT:    addi sp, sp, 32
272; RV32IFD-NEXT:    ret
273; RV32IFD-NEXT:  .LBB9_9: # %start
274; RV32IFD-NEXT:    mv a0, a2
275; RV32IFD-NEXT:    feq.d a2, ft1, ft1
276; RV32IFD-NEXT:    bnez a2, .LBB9_4
277; RV32IFD-NEXT:  .LBB9_10: # %start
278; RV32IFD-NEXT:    mv a0, zero
279; RV32IFD-NEXT:    lui a5, 524288
280; RV32IFD-NEXT:    bnez a3, .LBB9_5
281; RV32IFD-NEXT:  .LBB9_11: # %start
282; RV32IFD-NEXT:    lui a1, 524288
283; RV32IFD-NEXT:    beqz a4, .LBB9_6
284; RV32IFD-NEXT:  .LBB9_12:
285; RV32IFD-NEXT:    addi a1, a5, -1
286; RV32IFD-NEXT:    beqz a2, .LBB9_7
287; RV32IFD-NEXT:    j .LBB9_8
288;
289; RV64IFD-LABEL: fcvt_l_d_sat:
290; RV64IFD:       # %bb.0: # %start
291; RV64IFD-NEXT:    lui a1, %hi(.LCPI9_0)
292; RV64IFD-NEXT:    fld ft1, %lo(.LCPI9_0)(a1)
293; RV64IFD-NEXT:    fmv.d.x ft0, a0
294; RV64IFD-NEXT:    fle.d a0, ft1, ft0
295; RV64IFD-NEXT:    addi a1, zero, -1
296; RV64IFD-NEXT:    bnez a0, .LBB9_2
297; RV64IFD-NEXT:  # %bb.1: # %start
298; RV64IFD-NEXT:    slli a0, a1, 63
299; RV64IFD-NEXT:    j .LBB9_3
300; RV64IFD-NEXT:  .LBB9_2:
301; RV64IFD-NEXT:    fcvt.l.d a0, ft0, rtz
302; RV64IFD-NEXT:  .LBB9_3: # %start
303; RV64IFD-NEXT:    lui a2, %hi(.LCPI9_1)
304; RV64IFD-NEXT:    fld ft1, %lo(.LCPI9_1)(a2)
305; RV64IFD-NEXT:    flt.d a2, ft1, ft0
306; RV64IFD-NEXT:    bnez a2, .LBB9_6
307; RV64IFD-NEXT:  # %bb.4: # %start
308; RV64IFD-NEXT:    feq.d a1, ft0, ft0
309; RV64IFD-NEXT:    beqz a1, .LBB9_7
310; RV64IFD-NEXT:  .LBB9_5: # %start
311; RV64IFD-NEXT:    ret
312; RV64IFD-NEXT:  .LBB9_6:
313; RV64IFD-NEXT:    srli a0, a1, 1
314; RV64IFD-NEXT:    feq.d a1, ft0, ft0
315; RV64IFD-NEXT:    bnez a1, .LBB9_5
316; RV64IFD-NEXT:  .LBB9_7: # %start
317; RV64IFD-NEXT:    mv a0, zero
318; RV64IFD-NEXT:    ret
319start:
320  %0 = tail call i64 @llvm.fptosi.sat.i64.f64(double %a)
321  ret i64 %0
322}
323declare i64 @llvm.fptosi.sat.i64.f64(double)
324
325define i64 @fcvt_lu_d(double %a) nounwind {
326; RV32IFD-LABEL: fcvt_lu_d:
327; RV32IFD:       # %bb.0:
328; RV32IFD-NEXT:    addi sp, sp, -16
329; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
330; RV32IFD-NEXT:    call __fixunsdfdi@plt
331; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
332; RV32IFD-NEXT:    addi sp, sp, 16
333; RV32IFD-NEXT:    ret
334;
335; RV64IFD-LABEL: fcvt_lu_d:
336; RV64IFD:       # %bb.0:
337; RV64IFD-NEXT:    fmv.d.x ft0, a0
338; RV64IFD-NEXT:    fcvt.lu.d a0, ft0, rtz
339; RV64IFD-NEXT:    ret
340  %1 = fptoui double %a to i64
341  ret i64 %1
342}
343
344define i64 @fcvt_lu_d_sat(double %a) nounwind {
345; RV32IFD-LABEL: fcvt_lu_d_sat:
346; RV32IFD:       # %bb.0: # %start
347; RV32IFD-NEXT:    addi sp, sp, -32
348; RV32IFD-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
349; RV32IFD-NEXT:    sw a0, 16(sp)
350; RV32IFD-NEXT:    sw a1, 20(sp)
351; RV32IFD-NEXT:    fld ft0, 16(sp)
352; RV32IFD-NEXT:    fsd ft0, 8(sp) # 8-byte Folded Spill
353; RV32IFD-NEXT:    call __fixunsdfdi@plt
354; RV32IFD-NEXT:    fld ft1, 8(sp) # 8-byte Folded Reload
355; RV32IFD-NEXT:    fcvt.d.w ft0, zero
356; RV32IFD-NEXT:    fle.d a4, ft0, ft1
357; RV32IFD-NEXT:    mv a3, a0
358; RV32IFD-NEXT:    bnez a4, .LBB11_2
359; RV32IFD-NEXT:  # %bb.1: # %start
360; RV32IFD-NEXT:    mv a3, zero
361; RV32IFD-NEXT:  .LBB11_2: # %start
362; RV32IFD-NEXT:    lui a0, %hi(.LCPI11_0)
363; RV32IFD-NEXT:    fld ft0, %lo(.LCPI11_0)(a0)
364; RV32IFD-NEXT:    flt.d a5, ft0, ft1
365; RV32IFD-NEXT:    addi a2, zero, -1
366; RV32IFD-NEXT:    addi a0, zero, -1
367; RV32IFD-NEXT:    beqz a5, .LBB11_7
368; RV32IFD-NEXT:  # %bb.3: # %start
369; RV32IFD-NEXT:    beqz a4, .LBB11_8
370; RV32IFD-NEXT:  .LBB11_4: # %start
371; RV32IFD-NEXT:    bnez a5, .LBB11_6
372; RV32IFD-NEXT:  .LBB11_5: # %start
373; RV32IFD-NEXT:    mv a2, a1
374; RV32IFD-NEXT:  .LBB11_6: # %start
375; RV32IFD-NEXT:    mv a1, a2
376; RV32IFD-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
377; RV32IFD-NEXT:    addi sp, sp, 32
378; RV32IFD-NEXT:    ret
379; RV32IFD-NEXT:  .LBB11_7: # %start
380; RV32IFD-NEXT:    mv a0, a3
381; RV32IFD-NEXT:    bnez a4, .LBB11_4
382; RV32IFD-NEXT:  .LBB11_8: # %start
383; RV32IFD-NEXT:    mv a1, zero
384; RV32IFD-NEXT:    beqz a5, .LBB11_5
385; RV32IFD-NEXT:    j .LBB11_6
386;
387; RV64IFD-LABEL: fcvt_lu_d_sat:
388; RV64IFD:       # %bb.0: # %start
389; RV64IFD-NEXT:    fmv.d.x ft0, a0
390; RV64IFD-NEXT:    fmv.d.x ft1, zero
391; RV64IFD-NEXT:    fle.d a0, ft1, ft0
392; RV64IFD-NEXT:    bnez a0, .LBB11_2
393; RV64IFD-NEXT:  # %bb.1: # %start
394; RV64IFD-NEXT:    mv a1, zero
395; RV64IFD-NEXT:    j .LBB11_3
396; RV64IFD-NEXT:  .LBB11_2:
397; RV64IFD-NEXT:    fcvt.lu.d a1, ft0, rtz
398; RV64IFD-NEXT:  .LBB11_3: # %start
399; RV64IFD-NEXT:    lui a0, %hi(.LCPI11_0)
400; RV64IFD-NEXT:    fld ft1, %lo(.LCPI11_0)(a0)
401; RV64IFD-NEXT:    flt.d a2, ft1, ft0
402; RV64IFD-NEXT:    addi a0, zero, -1
403; RV64IFD-NEXT:    bnez a2, .LBB11_5
404; RV64IFD-NEXT:  # %bb.4: # %start
405; RV64IFD-NEXT:    mv a0, a1
406; RV64IFD-NEXT:  .LBB11_5: # %start
407; RV64IFD-NEXT:    ret
408start:
409  %0 = tail call i64 @llvm.fptoui.sat.i64.f64(double %a)
410  ret i64 %0
411}
412declare i64 @llvm.fptoui.sat.i64.f64(double)
413
414define i64 @fmv_x_d(double %a, double %b) nounwind {
415; RV32IFD-LABEL: fmv_x_d:
416; RV32IFD:       # %bb.0:
417; RV32IFD-NEXT:    addi sp, sp, -16
418; RV32IFD-NEXT:    sw a2, 0(sp)
419; RV32IFD-NEXT:    sw a3, 4(sp)
420; RV32IFD-NEXT:    fld ft0, 0(sp)
421; RV32IFD-NEXT:    sw a0, 0(sp)
422; RV32IFD-NEXT:    sw a1, 4(sp)
423; RV32IFD-NEXT:    fld ft1, 0(sp)
424; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0
425; RV32IFD-NEXT:    fsd ft0, 8(sp)
426; RV32IFD-NEXT:    lw a0, 8(sp)
427; RV32IFD-NEXT:    lw a1, 12(sp)
428; RV32IFD-NEXT:    addi sp, sp, 16
429; RV32IFD-NEXT:    ret
430;
431; RV64IFD-LABEL: fmv_x_d:
432; RV64IFD:       # %bb.0:
433; RV64IFD-NEXT:    fmv.d.x ft0, a1
434; RV64IFD-NEXT:    fmv.d.x ft1, a0
435; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0
436; RV64IFD-NEXT:    fmv.x.d a0, ft0
437; RV64IFD-NEXT:    ret
438  %1 = fadd double %a, %b
439  %2 = bitcast double %1 to i64
440  ret i64 %2
441}
442
443define double @fcvt_d_l(i64 %a) nounwind {
444; RV32IFD-LABEL: fcvt_d_l:
445; RV32IFD:       # %bb.0:
446; RV32IFD-NEXT:    addi sp, sp, -16
447; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
448; RV32IFD-NEXT:    call __floatdidf@plt
449; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
450; RV32IFD-NEXT:    addi sp, sp, 16
451; RV32IFD-NEXT:    ret
452;
453; RV64IFD-LABEL: fcvt_d_l:
454; RV64IFD:       # %bb.0:
455; RV64IFD-NEXT:    fcvt.d.l ft0, a0
456; RV64IFD-NEXT:    fmv.x.d a0, ft0
457; RV64IFD-NEXT:    ret
458  %1 = sitofp i64 %a to double
459  ret double %1
460}
461
462define double @fcvt_d_lu(i64 %a) nounwind {
463; RV32IFD-LABEL: fcvt_d_lu:
464; RV32IFD:       # %bb.0:
465; RV32IFD-NEXT:    addi sp, sp, -16
466; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
467; RV32IFD-NEXT:    call __floatundidf@plt
468; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
469; RV32IFD-NEXT:    addi sp, sp, 16
470; RV32IFD-NEXT:    ret
471;
472; RV64IFD-LABEL: fcvt_d_lu:
473; RV64IFD:       # %bb.0:
474; RV64IFD-NEXT:    fcvt.d.lu ft0, a0
475; RV64IFD-NEXT:    fmv.x.d a0, ft0
476; RV64IFD-NEXT:    ret
477  %1 = uitofp i64 %a to double
478  ret double %1
479}
480
481define double @fmv_d_x(i64 %a, i64 %b) nounwind {
482; Ensure fmv.w.x is generated even for a soft double calling convention
483; RV32IFD-LABEL: fmv_d_x:
484; RV32IFD:       # %bb.0:
485; RV32IFD-NEXT:    addi sp, sp, -32
486; RV32IFD-NEXT:    sw a3, 20(sp)
487; RV32IFD-NEXT:    sw a2, 16(sp)
488; RV32IFD-NEXT:    sw a1, 28(sp)
489; RV32IFD-NEXT:    sw a0, 24(sp)
490; RV32IFD-NEXT:    fld ft0, 16(sp)
491; RV32IFD-NEXT:    fld ft1, 24(sp)
492; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0
493; RV32IFD-NEXT:    fsd ft0, 8(sp)
494; RV32IFD-NEXT:    lw a0, 8(sp)
495; RV32IFD-NEXT:    lw a1, 12(sp)
496; RV32IFD-NEXT:    addi sp, sp, 32
497; RV32IFD-NEXT:    ret
498;
499; RV64IFD-LABEL: fmv_d_x:
500; RV64IFD:       # %bb.0:
501; RV64IFD-NEXT:    fmv.d.x ft0, a0
502; RV64IFD-NEXT:    fmv.d.x ft1, a1
503; RV64IFD-NEXT:    fadd.d ft0, ft0, ft1
504; RV64IFD-NEXT:    fmv.x.d a0, ft0
505; RV64IFD-NEXT:    ret
506  %1 = bitcast i64 %a to double
507  %2 = bitcast i64 %b to double
508  %3 = fadd double %1, %2
509  ret double %3
510}
511
512define double @fcvt_d_w_i8(i8 signext %a) nounwind {
513; RV32IFD-LABEL: fcvt_d_w_i8:
514; RV32IFD:       # %bb.0:
515; RV32IFD-NEXT:    addi sp, sp, -16
516; RV32IFD-NEXT:    fcvt.d.w ft0, a0
517; RV32IFD-NEXT:    fsd ft0, 8(sp)
518; RV32IFD-NEXT:    lw a0, 8(sp)
519; RV32IFD-NEXT:    lw a1, 12(sp)
520; RV32IFD-NEXT:    addi sp, sp, 16
521; RV32IFD-NEXT:    ret
522;
523; RV64IFD-LABEL: fcvt_d_w_i8:
524; RV64IFD:       # %bb.0:
525; RV64IFD-NEXT:    fcvt.d.w ft0, a0
526; RV64IFD-NEXT:    fmv.x.d a0, ft0
527; RV64IFD-NEXT:    ret
528  %1 = sitofp i8 %a to double
529  ret double %1
530}
531
532define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind {
533; RV32IFD-LABEL: fcvt_d_wu_i8:
534; RV32IFD:       # %bb.0:
535; RV32IFD-NEXT:    addi sp, sp, -16
536; RV32IFD-NEXT:    fcvt.d.wu ft0, a0
537; RV32IFD-NEXT:    fsd ft0, 8(sp)
538; RV32IFD-NEXT:    lw a0, 8(sp)
539; RV32IFD-NEXT:    lw a1, 12(sp)
540; RV32IFD-NEXT:    addi sp, sp, 16
541; RV32IFD-NEXT:    ret
542;
543; RV64IFD-LABEL: fcvt_d_wu_i8:
544; RV64IFD:       # %bb.0:
545; RV64IFD-NEXT:    fcvt.d.wu ft0, a0
546; RV64IFD-NEXT:    fmv.x.d a0, ft0
547; RV64IFD-NEXT:    ret
548  %1 = uitofp i8 %a to double
549  ret double %1
550}
551
552define double @fcvt_d_w_i16(i16 signext %a) nounwind {
553; RV32IFD-LABEL: fcvt_d_w_i16:
554; RV32IFD:       # %bb.0:
555; RV32IFD-NEXT:    addi sp, sp, -16
556; RV32IFD-NEXT:    fcvt.d.w ft0, a0
557; RV32IFD-NEXT:    fsd ft0, 8(sp)
558; RV32IFD-NEXT:    lw a0, 8(sp)
559; RV32IFD-NEXT:    lw a1, 12(sp)
560; RV32IFD-NEXT:    addi sp, sp, 16
561; RV32IFD-NEXT:    ret
562;
563; RV64IFD-LABEL: fcvt_d_w_i16:
564; RV64IFD:       # %bb.0:
565; RV64IFD-NEXT:    fcvt.d.w ft0, a0
566; RV64IFD-NEXT:    fmv.x.d a0, ft0
567; RV64IFD-NEXT:    ret
568  %1 = sitofp i16 %a to double
569  ret double %1
570}
571
572define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind {
573; RV32IFD-LABEL: fcvt_d_wu_i16:
574; RV32IFD:       # %bb.0:
575; RV32IFD-NEXT:    addi sp, sp, -16
576; RV32IFD-NEXT:    fcvt.d.wu ft0, a0
577; RV32IFD-NEXT:    fsd ft0, 8(sp)
578; RV32IFD-NEXT:    lw a0, 8(sp)
579; RV32IFD-NEXT:    lw a1, 12(sp)
580; RV32IFD-NEXT:    addi sp, sp, 16
581; RV32IFD-NEXT:    ret
582;
583; RV64IFD-LABEL: fcvt_d_wu_i16:
584; RV64IFD:       # %bb.0:
585; RV64IFD-NEXT:    fcvt.d.wu ft0, a0
586; RV64IFD-NEXT:    fmv.x.d a0, ft0
587; RV64IFD-NEXT:    ret
588  %1 = uitofp i16 %a to double
589  ret double %1
590}
591