1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32I %s
4; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
5; RUN:   | FileCheck -check-prefix=RV32IM %s
6; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
7; RUN:   | FileCheck -check-prefix=RV64I %s
8; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
9; RUN:   | FileCheck -check-prefix=RV64IM %s
10
11define i32 @udiv(i32 %a, i32 %b) nounwind {
12; RV32I-LABEL: udiv:
13; RV32I:       # %bb.0:
14; RV32I-NEXT:    addi sp, sp, -16
15; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
16; RV32I-NEXT:    call __udivsi3@plt
17; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
18; RV32I-NEXT:    addi sp, sp, 16
19; RV32I-NEXT:    ret
20;
21; RV32IM-LABEL: udiv:
22; RV32IM:       # %bb.0:
23; RV32IM-NEXT:    divu a0, a0, a1
24; RV32IM-NEXT:    ret
25;
26; RV64I-LABEL: udiv:
27; RV64I:       # %bb.0:
28; RV64I-NEXT:    addi sp, sp, -16
29; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
30; RV64I-NEXT:    slli a0, a0, 32
31; RV64I-NEXT:    srli a0, a0, 32
32; RV64I-NEXT:    slli a1, a1, 32
33; RV64I-NEXT:    srli a1, a1, 32
34; RV64I-NEXT:    call __udivdi3@plt
35; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
36; RV64I-NEXT:    addi sp, sp, 16
37; RV64I-NEXT:    ret
38;
39; RV64IM-LABEL: udiv:
40; RV64IM:       # %bb.0:
41; RV64IM-NEXT:    divuw a0, a0, a1
42; RV64IM-NEXT:    ret
43  %1 = udiv i32 %a, %b
44  ret i32 %1
45}
46
47define i32 @udiv_constant(i32 %a) nounwind {
48; RV32I-LABEL: udiv_constant:
49; RV32I:       # %bb.0:
50; RV32I-NEXT:    addi sp, sp, -16
51; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
52; RV32I-NEXT:    addi a1, zero, 5
53; RV32I-NEXT:    call __udivsi3@plt
54; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
55; RV32I-NEXT:    addi sp, sp, 16
56; RV32I-NEXT:    ret
57;
58; RV32IM-LABEL: udiv_constant:
59; RV32IM:       # %bb.0:
60; RV32IM-NEXT:    lui a1, 838861
61; RV32IM-NEXT:    addi a1, a1, -819
62; RV32IM-NEXT:    mulhu a0, a0, a1
63; RV32IM-NEXT:    srli a0, a0, 2
64; RV32IM-NEXT:    ret
65;
66; RV64I-LABEL: udiv_constant:
67; RV64I:       # %bb.0:
68; RV64I-NEXT:    addi sp, sp, -16
69; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
70; RV64I-NEXT:    slli a0, a0, 32
71; RV64I-NEXT:    srli a0, a0, 32
72; RV64I-NEXT:    addi a1, zero, 5
73; RV64I-NEXT:    call __udivdi3@plt
74; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
75; RV64I-NEXT:    addi sp, sp, 16
76; RV64I-NEXT:    ret
77;
78; RV64IM-LABEL: udiv_constant:
79; RV64IM:       # %bb.0:
80; RV64IM-NEXT:    slli a0, a0, 32
81; RV64IM-NEXT:    srli a0, a0, 32
82; RV64IM-NEXT:    lui a1, 205
83; RV64IM-NEXT:    addiw a1, a1, -819
84; RV64IM-NEXT:    slli a1, a1, 12
85; RV64IM-NEXT:    addi a1, a1, -819
86; RV64IM-NEXT:    mul a0, a0, a1
87; RV64IM-NEXT:    srli a0, a0, 34
88; RV64IM-NEXT:    ret
89  %1 = udiv i32 %a, 5
90  ret i32 %1
91}
92
93define i32 @udiv_pow2(i32 %a) nounwind {
94; RV32I-LABEL: udiv_pow2:
95; RV32I:       # %bb.0:
96; RV32I-NEXT:    srli a0, a0, 3
97; RV32I-NEXT:    ret
98;
99; RV32IM-LABEL: udiv_pow2:
100; RV32IM:       # %bb.0:
101; RV32IM-NEXT:    srli a0, a0, 3
102; RV32IM-NEXT:    ret
103;
104; RV64I-LABEL: udiv_pow2:
105; RV64I:       # %bb.0:
106; RV64I-NEXT:    srliw a0, a0, 3
107; RV64I-NEXT:    ret
108;
109; RV64IM-LABEL: udiv_pow2:
110; RV64IM:       # %bb.0:
111; RV64IM-NEXT:    srliw a0, a0, 3
112; RV64IM-NEXT:    ret
113  %1 = udiv i32 %a, 8
114  ret i32 %1
115}
116
117define i32 @udiv_constant_lhs(i32 %a) nounwind {
118; RV32I-LABEL: udiv_constant_lhs:
119; RV32I:       # %bb.0:
120; RV32I-NEXT:    addi sp, sp, -16
121; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
122; RV32I-NEXT:    mv a1, a0
123; RV32I-NEXT:    addi a0, zero, 10
124; RV32I-NEXT:    call __udivsi3@plt
125; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
126; RV32I-NEXT:    addi sp, sp, 16
127; RV32I-NEXT:    ret
128;
129; RV32IM-LABEL: udiv_constant_lhs:
130; RV32IM:       # %bb.0:
131; RV32IM-NEXT:    addi a1, zero, 10
132; RV32IM-NEXT:    divu a0, a1, a0
133; RV32IM-NEXT:    ret
134;
135; RV64I-LABEL: udiv_constant_lhs:
136; RV64I:       # %bb.0:
137; RV64I-NEXT:    addi sp, sp, -16
138; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
139; RV64I-NEXT:    slli a0, a0, 32
140; RV64I-NEXT:    srli a1, a0, 32
141; RV64I-NEXT:    addi a0, zero, 10
142; RV64I-NEXT:    call __udivdi3@plt
143; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
144; RV64I-NEXT:    addi sp, sp, 16
145; RV64I-NEXT:    ret
146;
147; RV64IM-LABEL: udiv_constant_lhs:
148; RV64IM:       # %bb.0:
149; RV64IM-NEXT:    addi a1, zero, 10
150; RV64IM-NEXT:    divuw a0, a1, a0
151; RV64IM-NEXT:    ret
152  %1 = udiv i32 10, %a
153  ret i32 %1
154}
155
156define i64 @udiv64(i64 %a, i64 %b) nounwind {
157; RV32I-LABEL: udiv64:
158; RV32I:       # %bb.0:
159; RV32I-NEXT:    addi sp, sp, -16
160; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
161; RV32I-NEXT:    call __udivdi3@plt
162; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
163; RV32I-NEXT:    addi sp, sp, 16
164; RV32I-NEXT:    ret
165;
166; RV32IM-LABEL: udiv64:
167; RV32IM:       # %bb.0:
168; RV32IM-NEXT:    addi sp, sp, -16
169; RV32IM-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
170; RV32IM-NEXT:    call __udivdi3@plt
171; RV32IM-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
172; RV32IM-NEXT:    addi sp, sp, 16
173; RV32IM-NEXT:    ret
174;
175; RV64I-LABEL: udiv64:
176; RV64I:       # %bb.0:
177; RV64I-NEXT:    addi sp, sp, -16
178; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
179; RV64I-NEXT:    call __udivdi3@plt
180; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
181; RV64I-NEXT:    addi sp, sp, 16
182; RV64I-NEXT:    ret
183;
184; RV64IM-LABEL: udiv64:
185; RV64IM:       # %bb.0:
186; RV64IM-NEXT:    divu a0, a0, a1
187; RV64IM-NEXT:    ret
188  %1 = udiv i64 %a, %b
189  ret i64 %1
190}
191
192define i64 @udiv64_constant(i64 %a) nounwind {
193; RV32I-LABEL: udiv64_constant:
194; RV32I:       # %bb.0:
195; RV32I-NEXT:    addi sp, sp, -16
196; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
197; RV32I-NEXT:    addi a2, zero, 5
198; RV32I-NEXT:    mv a3, zero
199; RV32I-NEXT:    call __udivdi3@plt
200; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
201; RV32I-NEXT:    addi sp, sp, 16
202; RV32I-NEXT:    ret
203;
204; RV32IM-LABEL: udiv64_constant:
205; RV32IM:       # %bb.0:
206; RV32IM-NEXT:    addi sp, sp, -16
207; RV32IM-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
208; RV32IM-NEXT:    addi a2, zero, 5
209; RV32IM-NEXT:    mv a3, zero
210; RV32IM-NEXT:    call __udivdi3@plt
211; RV32IM-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
212; RV32IM-NEXT:    addi sp, sp, 16
213; RV32IM-NEXT:    ret
214;
215; RV64I-LABEL: udiv64_constant:
216; RV64I:       # %bb.0:
217; RV64I-NEXT:    addi sp, sp, -16
218; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
219; RV64I-NEXT:    addi a1, zero, 5
220; RV64I-NEXT:    call __udivdi3@plt
221; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
222; RV64I-NEXT:    addi sp, sp, 16
223; RV64I-NEXT:    ret
224;
225; RV64IM-LABEL: udiv64_constant:
226; RV64IM:       # %bb.0:
227; RV64IM-NEXT:    lui a1, 1035469
228; RV64IM-NEXT:    addiw a1, a1, -819
229; RV64IM-NEXT:    slli a1, a1, 12
230; RV64IM-NEXT:    addi a1, a1, -819
231; RV64IM-NEXT:    slli a1, a1, 12
232; RV64IM-NEXT:    addi a1, a1, -819
233; RV64IM-NEXT:    slli a1, a1, 12
234; RV64IM-NEXT:    addi a1, a1, -819
235; RV64IM-NEXT:    mulhu a0, a0, a1
236; RV64IM-NEXT:    srli a0, a0, 2
237; RV64IM-NEXT:    ret
238  %1 = udiv i64 %a, 5
239  ret i64 %1
240}
241
242define i64 @udiv64_constant_lhs(i64 %a) nounwind {
243; RV32I-LABEL: udiv64_constant_lhs:
244; RV32I:       # %bb.0:
245; RV32I-NEXT:    addi sp, sp, -16
246; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
247; RV32I-NEXT:    mv a3, a1
248; RV32I-NEXT:    mv a2, a0
249; RV32I-NEXT:    addi a0, zero, 10
250; RV32I-NEXT:    mv a1, zero
251; RV32I-NEXT:    call __udivdi3@plt
252; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
253; RV32I-NEXT:    addi sp, sp, 16
254; RV32I-NEXT:    ret
255;
256; RV32IM-LABEL: udiv64_constant_lhs:
257; RV32IM:       # %bb.0:
258; RV32IM-NEXT:    addi sp, sp, -16
259; RV32IM-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
260; RV32IM-NEXT:    mv a3, a1
261; RV32IM-NEXT:    mv a2, a0
262; RV32IM-NEXT:    addi a0, zero, 10
263; RV32IM-NEXT:    mv a1, zero
264; RV32IM-NEXT:    call __udivdi3@plt
265; RV32IM-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
266; RV32IM-NEXT:    addi sp, sp, 16
267; RV32IM-NEXT:    ret
268;
269; RV64I-LABEL: udiv64_constant_lhs:
270; RV64I:       # %bb.0:
271; RV64I-NEXT:    addi sp, sp, -16
272; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
273; RV64I-NEXT:    mv a1, a0
274; RV64I-NEXT:    addi a0, zero, 10
275; RV64I-NEXT:    call __udivdi3@plt
276; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
277; RV64I-NEXT:    addi sp, sp, 16
278; RV64I-NEXT:    ret
279;
280; RV64IM-LABEL: udiv64_constant_lhs:
281; RV64IM:       # %bb.0:
282; RV64IM-NEXT:    addi a1, zero, 10
283; RV64IM-NEXT:    divu a0, a1, a0
284; RV64IM-NEXT:    ret
285  %1 = udiv i64 10, %a
286  ret i64 %1
287}
288
289define i8 @udiv8(i8 %a, i8 %b) nounwind {
290; RV32I-LABEL: udiv8:
291; RV32I:       # %bb.0:
292; RV32I-NEXT:    addi sp, sp, -16
293; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
294; RV32I-NEXT:    andi a0, a0, 255
295; RV32I-NEXT:    andi a1, a1, 255
296; RV32I-NEXT:    call __udivsi3@plt
297; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
298; RV32I-NEXT:    addi sp, sp, 16
299; RV32I-NEXT:    ret
300;
301; RV32IM-LABEL: udiv8:
302; RV32IM:       # %bb.0:
303; RV32IM-NEXT:    andi a1, a1, 255
304; RV32IM-NEXT:    andi a0, a0, 255
305; RV32IM-NEXT:    divu a0, a0, a1
306; RV32IM-NEXT:    ret
307;
308; RV64I-LABEL: udiv8:
309; RV64I:       # %bb.0:
310; RV64I-NEXT:    addi sp, sp, -16
311; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
312; RV64I-NEXT:    andi a0, a0, 255
313; RV64I-NEXT:    andi a1, a1, 255
314; RV64I-NEXT:    call __udivdi3@plt
315; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
316; RV64I-NEXT:    addi sp, sp, 16
317; RV64I-NEXT:    ret
318;
319; RV64IM-LABEL: udiv8:
320; RV64IM:       # %bb.0:
321; RV64IM-NEXT:    andi a1, a1, 255
322; RV64IM-NEXT:    andi a0, a0, 255
323; RV64IM-NEXT:    divuw a0, a0, a1
324; RV64IM-NEXT:    ret
325  %1 = udiv i8 %a, %b
326  ret i8 %1
327}
328
329define i8 @udiv8_constant(i8 %a) nounwind {
330; RV32I-LABEL: udiv8_constant:
331; RV32I:       # %bb.0:
332; RV32I-NEXT:    addi sp, sp, -16
333; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
334; RV32I-NEXT:    andi a0, a0, 255
335; RV32I-NEXT:    addi a1, zero, 5
336; RV32I-NEXT:    call __udivsi3@plt
337; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
338; RV32I-NEXT:    addi sp, sp, 16
339; RV32I-NEXT:    ret
340;
341; RV32IM-LABEL: udiv8_constant:
342; RV32IM:       # %bb.0:
343; RV32IM-NEXT:    andi a0, a0, 255
344; RV32IM-NEXT:    addi a1, zero, 205
345; RV32IM-NEXT:    mul a0, a0, a1
346; RV32IM-NEXT:    srli a0, a0, 10
347; RV32IM-NEXT:    ret
348;
349; RV64I-LABEL: udiv8_constant:
350; RV64I:       # %bb.0:
351; RV64I-NEXT:    addi sp, sp, -16
352; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
353; RV64I-NEXT:    andi a0, a0, 255
354; RV64I-NEXT:    addi a1, zero, 5
355; RV64I-NEXT:    call __udivdi3@plt
356; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
357; RV64I-NEXT:    addi sp, sp, 16
358; RV64I-NEXT:    ret
359;
360; RV64IM-LABEL: udiv8_constant:
361; RV64IM:       # %bb.0:
362; RV64IM-NEXT:    andi a0, a0, 255
363; RV64IM-NEXT:    addi a1, zero, 205
364; RV64IM-NEXT:    mul a0, a0, a1
365; RV64IM-NEXT:    srli a0, a0, 10
366; RV64IM-NEXT:    ret
367  %1 = udiv i8 %a, 5
368  ret i8 %1
369}
370
371define i8 @udiv8_pow2(i8 %a) nounwind {
372; RV32I-LABEL: udiv8_pow2:
373; RV32I:       # %bb.0:
374; RV32I-NEXT:    andi a0, a0, 248
375; RV32I-NEXT:    srli a0, a0, 3
376; RV32I-NEXT:    ret
377;
378; RV32IM-LABEL: udiv8_pow2:
379; RV32IM:       # %bb.0:
380; RV32IM-NEXT:    andi a0, a0, 248
381; RV32IM-NEXT:    srli a0, a0, 3
382; RV32IM-NEXT:    ret
383;
384; RV64I-LABEL: udiv8_pow2:
385; RV64I:       # %bb.0:
386; RV64I-NEXT:    andi a0, a0, 248
387; RV64I-NEXT:    srli a0, a0, 3
388; RV64I-NEXT:    ret
389;
390; RV64IM-LABEL: udiv8_pow2:
391; RV64IM:       # %bb.0:
392; RV64IM-NEXT:    andi a0, a0, 248
393; RV64IM-NEXT:    srli a0, a0, 3
394; RV64IM-NEXT:    ret
395  %1 = udiv i8 %a, 8
396  ret i8 %1
397}
398
399define i8 @udiv8_constant_lhs(i8 %a) nounwind {
400; RV32I-LABEL: udiv8_constant_lhs:
401; RV32I:       # %bb.0:
402; RV32I-NEXT:    addi sp, sp, -16
403; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
404; RV32I-NEXT:    andi a1, a0, 255
405; RV32I-NEXT:    addi a0, zero, 10
406; RV32I-NEXT:    call __udivsi3@plt
407; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
408; RV32I-NEXT:    addi sp, sp, 16
409; RV32I-NEXT:    ret
410;
411; RV32IM-LABEL: udiv8_constant_lhs:
412; RV32IM:       # %bb.0:
413; RV32IM-NEXT:    andi a0, a0, 255
414; RV32IM-NEXT:    addi a1, zero, 10
415; RV32IM-NEXT:    divu a0, a1, a0
416; RV32IM-NEXT:    ret
417;
418; RV64I-LABEL: udiv8_constant_lhs:
419; RV64I:       # %bb.0:
420; RV64I-NEXT:    addi sp, sp, -16
421; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
422; RV64I-NEXT:    andi a1, a0, 255
423; RV64I-NEXT:    addi a0, zero, 10
424; RV64I-NEXT:    call __udivdi3@plt
425; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
426; RV64I-NEXT:    addi sp, sp, 16
427; RV64I-NEXT:    ret
428;
429; RV64IM-LABEL: udiv8_constant_lhs:
430; RV64IM:       # %bb.0:
431; RV64IM-NEXT:    andi a0, a0, 255
432; RV64IM-NEXT:    addi a1, zero, 10
433; RV64IM-NEXT:    divuw a0, a1, a0
434; RV64IM-NEXT:    ret
435  %1 = udiv i8 10, %a
436  ret i8 %1
437}
438
439define i16 @udiv16(i16 %a, i16 %b) nounwind {
440; RV32I-LABEL: udiv16:
441; RV32I:       # %bb.0:
442; RV32I-NEXT:    addi sp, sp, -16
443; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
444; RV32I-NEXT:    lui a2, 16
445; RV32I-NEXT:    addi a2, a2, -1
446; RV32I-NEXT:    and a0, a0, a2
447; RV32I-NEXT:    and a1, a1, a2
448; RV32I-NEXT:    call __udivsi3@plt
449; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
450; RV32I-NEXT:    addi sp, sp, 16
451; RV32I-NEXT:    ret
452;
453; RV32IM-LABEL: udiv16:
454; RV32IM:       # %bb.0:
455; RV32IM-NEXT:    lui a2, 16
456; RV32IM-NEXT:    addi a2, a2, -1
457; RV32IM-NEXT:    and a1, a1, a2
458; RV32IM-NEXT:    and a0, a0, a2
459; RV32IM-NEXT:    divu a0, a0, a1
460; RV32IM-NEXT:    ret
461;
462; RV64I-LABEL: udiv16:
463; RV64I:       # %bb.0:
464; RV64I-NEXT:    addi sp, sp, -16
465; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
466; RV64I-NEXT:    lui a2, 16
467; RV64I-NEXT:    addiw a2, a2, -1
468; RV64I-NEXT:    and a0, a0, a2
469; RV64I-NEXT:    and a1, a1, a2
470; RV64I-NEXT:    call __udivdi3@plt
471; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
472; RV64I-NEXT:    addi sp, sp, 16
473; RV64I-NEXT:    ret
474;
475; RV64IM-LABEL: udiv16:
476; RV64IM:       # %bb.0:
477; RV64IM-NEXT:    lui a2, 16
478; RV64IM-NEXT:    addiw a2, a2, -1
479; RV64IM-NEXT:    and a1, a1, a2
480; RV64IM-NEXT:    and a0, a0, a2
481; RV64IM-NEXT:    divuw a0, a0, a1
482; RV64IM-NEXT:    ret
483  %1 = udiv i16 %a, %b
484  ret i16 %1
485}
486
487define i16 @udiv16_constant(i16 %a) nounwind {
488; RV32I-LABEL: udiv16_constant:
489; RV32I:       # %bb.0:
490; RV32I-NEXT:    addi sp, sp, -16
491; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
492; RV32I-NEXT:    lui a1, 16
493; RV32I-NEXT:    addi a1, a1, -1
494; RV32I-NEXT:    and a0, a0, a1
495; RV32I-NEXT:    addi a1, zero, 5
496; RV32I-NEXT:    call __udivsi3@plt
497; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
498; RV32I-NEXT:    addi sp, sp, 16
499; RV32I-NEXT:    ret
500;
501; RV32IM-LABEL: udiv16_constant:
502; RV32IM:       # %bb.0:
503; RV32IM-NEXT:    lui a1, 16
504; RV32IM-NEXT:    addi a1, a1, -1
505; RV32IM-NEXT:    and a0, a0, a1
506; RV32IM-NEXT:    lui a1, 13
507; RV32IM-NEXT:    addi a1, a1, -819
508; RV32IM-NEXT:    mul a0, a0, a1
509; RV32IM-NEXT:    srli a0, a0, 18
510; RV32IM-NEXT:    ret
511;
512; RV64I-LABEL: udiv16_constant:
513; RV64I:       # %bb.0:
514; RV64I-NEXT:    addi sp, sp, -16
515; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
516; RV64I-NEXT:    lui a1, 16
517; RV64I-NEXT:    addiw a1, a1, -1
518; RV64I-NEXT:    and a0, a0, a1
519; RV64I-NEXT:    addi a1, zero, 5
520; RV64I-NEXT:    call __udivdi3@plt
521; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
522; RV64I-NEXT:    addi sp, sp, 16
523; RV64I-NEXT:    ret
524;
525; RV64IM-LABEL: udiv16_constant:
526; RV64IM:       # %bb.0:
527; RV64IM-NEXT:    lui a1, 16
528; RV64IM-NEXT:    addiw a1, a1, -1
529; RV64IM-NEXT:    and a0, a0, a1
530; RV64IM-NEXT:    lui a1, 13
531; RV64IM-NEXT:    addiw a1, a1, -819
532; RV64IM-NEXT:    mul a0, a0, a1
533; RV64IM-NEXT:    srli a0, a0, 18
534; RV64IM-NEXT:    ret
535  %1 = udiv i16 %a, 5
536  ret i16 %1
537}
538
539define i16 @udiv16_pow2(i16 %a) nounwind {
540; RV32I-LABEL: udiv16_pow2:
541; RV32I:       # %bb.0:
542; RV32I-NEXT:    slli a0, a0, 16
543; RV32I-NEXT:    srli a0, a0, 19
544; RV32I-NEXT:    ret
545;
546; RV32IM-LABEL: udiv16_pow2:
547; RV32IM:       # %bb.0:
548; RV32IM-NEXT:    slli a0, a0, 16
549; RV32IM-NEXT:    srli a0, a0, 19
550; RV32IM-NEXT:    ret
551;
552; RV64I-LABEL: udiv16_pow2:
553; RV64I:       # %bb.0:
554; RV64I-NEXT:    slli a0, a0, 48
555; RV64I-NEXT:    srli a0, a0, 51
556; RV64I-NEXT:    ret
557;
558; RV64IM-LABEL: udiv16_pow2:
559; RV64IM:       # %bb.0:
560; RV64IM-NEXT:    slli a0, a0, 48
561; RV64IM-NEXT:    srli a0, a0, 51
562; RV64IM-NEXT:    ret
563  %1 = udiv i16 %a, 8
564  ret i16 %1
565}
566
567define i16 @udiv16_constant_lhs(i16 %a) nounwind {
568; RV32I-LABEL: udiv16_constant_lhs:
569; RV32I:       # %bb.0:
570; RV32I-NEXT:    addi sp, sp, -16
571; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
572; RV32I-NEXT:    lui a1, 16
573; RV32I-NEXT:    addi a1, a1, -1
574; RV32I-NEXT:    and a1, a0, a1
575; RV32I-NEXT:    addi a0, zero, 10
576; RV32I-NEXT:    call __udivsi3@plt
577; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
578; RV32I-NEXT:    addi sp, sp, 16
579; RV32I-NEXT:    ret
580;
581; RV32IM-LABEL: udiv16_constant_lhs:
582; RV32IM:       # %bb.0:
583; RV32IM-NEXT:    lui a1, 16
584; RV32IM-NEXT:    addi a1, a1, -1
585; RV32IM-NEXT:    and a0, a0, a1
586; RV32IM-NEXT:    addi a1, zero, 10
587; RV32IM-NEXT:    divu a0, a1, a0
588; RV32IM-NEXT:    ret
589;
590; RV64I-LABEL: udiv16_constant_lhs:
591; RV64I:       # %bb.0:
592; RV64I-NEXT:    addi sp, sp, -16
593; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
594; RV64I-NEXT:    lui a1, 16
595; RV64I-NEXT:    addiw a1, a1, -1
596; RV64I-NEXT:    and a1, a0, a1
597; RV64I-NEXT:    addi a0, zero, 10
598; RV64I-NEXT:    call __udivdi3@plt
599; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
600; RV64I-NEXT:    addi sp, sp, 16
601; RV64I-NEXT:    ret
602;
603; RV64IM-LABEL: udiv16_constant_lhs:
604; RV64IM:       # %bb.0:
605; RV64IM-NEXT:    lui a1, 16
606; RV64IM-NEXT:    addiw a1, a1, -1
607; RV64IM-NEXT:    and a0, a0, a1
608; RV64IM-NEXT:    addi a1, zero, 10
609; RV64IM-NEXT:    divuw a0, a1, a0
610; RV64IM-NEXT:    ret
611  %1 = udiv i16 10, %a
612  ret i16 %1
613}
614
615define i32 @sdiv(i32 %a, i32 %b) nounwind {
616; RV32I-LABEL: sdiv:
617; RV32I:       # %bb.0:
618; RV32I-NEXT:    addi sp, sp, -16
619; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
620; RV32I-NEXT:    call __divsi3@plt
621; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
622; RV32I-NEXT:    addi sp, sp, 16
623; RV32I-NEXT:    ret
624;
625; RV32IM-LABEL: sdiv:
626; RV32IM:       # %bb.0:
627; RV32IM-NEXT:    div a0, a0, a1
628; RV32IM-NEXT:    ret
629;
630; RV64I-LABEL: sdiv:
631; RV64I:       # %bb.0:
632; RV64I-NEXT:    addi sp, sp, -16
633; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
634; RV64I-NEXT:    sext.w a0, a0
635; RV64I-NEXT:    sext.w a1, a1
636; RV64I-NEXT:    call __divdi3@plt
637; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
638; RV64I-NEXT:    addi sp, sp, 16
639; RV64I-NEXT:    ret
640;
641; RV64IM-LABEL: sdiv:
642; RV64IM:       # %bb.0:
643; RV64IM-NEXT:    divw a0, a0, a1
644; RV64IM-NEXT:    ret
645  %1 = sdiv i32 %a, %b
646  ret i32 %1
647}
648
649define i32 @sdiv_constant(i32 %a) nounwind {
650; RV32I-LABEL: sdiv_constant:
651; RV32I:       # %bb.0:
652; RV32I-NEXT:    addi sp, sp, -16
653; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
654; RV32I-NEXT:    addi a1, zero, 5
655; RV32I-NEXT:    call __divsi3@plt
656; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
657; RV32I-NEXT:    addi sp, sp, 16
658; RV32I-NEXT:    ret
659;
660; RV32IM-LABEL: sdiv_constant:
661; RV32IM:       # %bb.0:
662; RV32IM-NEXT:    lui a1, 419430
663; RV32IM-NEXT:    addi a1, a1, 1639
664; RV32IM-NEXT:    mulh a0, a0, a1
665; RV32IM-NEXT:    srli a1, a0, 31
666; RV32IM-NEXT:    srai a0, a0, 1
667; RV32IM-NEXT:    add a0, a0, a1
668; RV32IM-NEXT:    ret
669;
670; RV64I-LABEL: sdiv_constant:
671; RV64I:       # %bb.0:
672; RV64I-NEXT:    addi sp, sp, -16
673; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
674; RV64I-NEXT:    sext.w a0, a0
675; RV64I-NEXT:    addi a1, zero, 5
676; RV64I-NEXT:    call __divdi3@plt
677; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
678; RV64I-NEXT:    addi sp, sp, 16
679; RV64I-NEXT:    ret
680;
681; RV64IM-LABEL: sdiv_constant:
682; RV64IM:       # %bb.0:
683; RV64IM-NEXT:    sext.w a0, a0
684; RV64IM-NEXT:    lui a1, 419430
685; RV64IM-NEXT:    addiw a1, a1, 1639
686; RV64IM-NEXT:    mul a0, a0, a1
687; RV64IM-NEXT:    srli a1, a0, 63
688; RV64IM-NEXT:    srai a0, a0, 33
689; RV64IM-NEXT:    add a0, a0, a1
690; RV64IM-NEXT:    ret
691  %1 = sdiv i32 %a, 5
692  ret i32 %1
693}
694
695define i32 @sdiv_pow2(i32 %a) nounwind {
696; RV32I-LABEL: sdiv_pow2:
697; RV32I:       # %bb.0:
698; RV32I-NEXT:    srai a1, a0, 31
699; RV32I-NEXT:    srli a1, a1, 29
700; RV32I-NEXT:    add a0, a0, a1
701; RV32I-NEXT:    srai a0, a0, 3
702; RV32I-NEXT:    ret
703;
704; RV32IM-LABEL: sdiv_pow2:
705; RV32IM:       # %bb.0:
706; RV32IM-NEXT:    srai a1, a0, 31
707; RV32IM-NEXT:    srli a1, a1, 29
708; RV32IM-NEXT:    add a0, a0, a1
709; RV32IM-NEXT:    srai a0, a0, 3
710; RV32IM-NEXT:    ret
711;
712; RV64I-LABEL: sdiv_pow2:
713; RV64I:       # %bb.0:
714; RV64I-NEXT:    sraiw a1, a0, 31
715; RV64I-NEXT:    srliw a1, a1, 29
716; RV64I-NEXT:    add a0, a0, a1
717; RV64I-NEXT:    sraiw a0, a0, 3
718; RV64I-NEXT:    ret
719;
720; RV64IM-LABEL: sdiv_pow2:
721; RV64IM:       # %bb.0:
722; RV64IM-NEXT:    sraiw a1, a0, 31
723; RV64IM-NEXT:    srliw a1, a1, 29
724; RV64IM-NEXT:    add a0, a0, a1
725; RV64IM-NEXT:    sraiw a0, a0, 3
726; RV64IM-NEXT:    ret
727  %1 = sdiv i32 %a, 8
728  ret i32 %1
729}
730
731define i32 @sdiv_pow2_2(i32 %a) nounwind {
732; RV32I-LABEL: sdiv_pow2_2:
733; RV32I:       # %bb.0:
734; RV32I-NEXT:    srai a1, a0, 31
735; RV32I-NEXT:    srli a1, a1, 16
736; RV32I-NEXT:    add a0, a0, a1
737; RV32I-NEXT:    srai a0, a0, 16
738; RV32I-NEXT:    ret
739;
740; RV32IM-LABEL: sdiv_pow2_2:
741; RV32IM:       # %bb.0:
742; RV32IM-NEXT:    srai a1, a0, 31
743; RV32IM-NEXT:    srli a1, a1, 16
744; RV32IM-NEXT:    add a0, a0, a1
745; RV32IM-NEXT:    srai a0, a0, 16
746; RV32IM-NEXT:    ret
747;
748; RV64I-LABEL: sdiv_pow2_2:
749; RV64I:       # %bb.0:
750; RV64I-NEXT:    sraiw a1, a0, 31
751; RV64I-NEXT:    srliw a1, a1, 16
752; RV64I-NEXT:    add a0, a0, a1
753; RV64I-NEXT:    sraiw a0, a0, 16
754; RV64I-NEXT:    ret
755;
756; RV64IM-LABEL: sdiv_pow2_2:
757; RV64IM:       # %bb.0:
758; RV64IM-NEXT:    sraiw a1, a0, 31
759; RV64IM-NEXT:    srliw a1, a1, 16
760; RV64IM-NEXT:    add a0, a0, a1
761; RV64IM-NEXT:    sraiw a0, a0, 16
762; RV64IM-NEXT:    ret
763  %1 = sdiv i32 %a, 65536
764  ret i32 %1
765}
766
767define i32 @sdiv_constant_lhs(i32 %a) nounwind {
768; RV32I-LABEL: sdiv_constant_lhs:
769; RV32I:       # %bb.0:
770; RV32I-NEXT:    addi sp, sp, -16
771; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
772; RV32I-NEXT:    mv a1, a0
773; RV32I-NEXT:    addi a0, zero, -10
774; RV32I-NEXT:    call __divsi3@plt
775; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
776; RV32I-NEXT:    addi sp, sp, 16
777; RV32I-NEXT:    ret
778;
779; RV32IM-LABEL: sdiv_constant_lhs:
780; RV32IM:       # %bb.0:
781; RV32IM-NEXT:    addi a1, zero, -10
782; RV32IM-NEXT:    div a0, a1, a0
783; RV32IM-NEXT:    ret
784;
785; RV64I-LABEL: sdiv_constant_lhs:
786; RV64I:       # %bb.0:
787; RV64I-NEXT:    addi sp, sp, -16
788; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
789; RV64I-NEXT:    sext.w a1, a0
790; RV64I-NEXT:    addi a0, zero, -10
791; RV64I-NEXT:    call __divdi3@plt
792; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
793; RV64I-NEXT:    addi sp, sp, 16
794; RV64I-NEXT:    ret
795;
796; RV64IM-LABEL: sdiv_constant_lhs:
797; RV64IM:       # %bb.0:
798; RV64IM-NEXT:    addi a1, zero, -10
799; RV64IM-NEXT:    divw a0, a1, a0
800; RV64IM-NEXT:    ret
801  %1 = sdiv i32 -10, %a
802  ret i32 %1
803}
804
805define i64 @sdiv64(i64 %a, i64 %b) nounwind {
806; RV32I-LABEL: sdiv64:
807; RV32I:       # %bb.0:
808; RV32I-NEXT:    addi sp, sp, -16
809; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
810; RV32I-NEXT:    call __divdi3@plt
811; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
812; RV32I-NEXT:    addi sp, sp, 16
813; RV32I-NEXT:    ret
814;
815; RV32IM-LABEL: sdiv64:
816; RV32IM:       # %bb.0:
817; RV32IM-NEXT:    addi sp, sp, -16
818; RV32IM-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
819; RV32IM-NEXT:    call __divdi3@plt
820; RV32IM-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
821; RV32IM-NEXT:    addi sp, sp, 16
822; RV32IM-NEXT:    ret
823;
824; RV64I-LABEL: sdiv64:
825; RV64I:       # %bb.0:
826; RV64I-NEXT:    addi sp, sp, -16
827; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
828; RV64I-NEXT:    call __divdi3@plt
829; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
830; RV64I-NEXT:    addi sp, sp, 16
831; RV64I-NEXT:    ret
832;
833; RV64IM-LABEL: sdiv64:
834; RV64IM:       # %bb.0:
835; RV64IM-NEXT:    div a0, a0, a1
836; RV64IM-NEXT:    ret
837  %1 = sdiv i64 %a, %b
838  ret i64 %1
839}
840
841define i64 @sdiv64_constant(i64 %a) nounwind {
842; RV32I-LABEL: sdiv64_constant:
843; RV32I:       # %bb.0:
844; RV32I-NEXT:    addi sp, sp, -16
845; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
846; RV32I-NEXT:    addi a2, zero, 5
847; RV32I-NEXT:    mv a3, zero
848; RV32I-NEXT:    call __divdi3@plt
849; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
850; RV32I-NEXT:    addi sp, sp, 16
851; RV32I-NEXT:    ret
852;
853; RV32IM-LABEL: sdiv64_constant:
854; RV32IM:       # %bb.0:
855; RV32IM-NEXT:    addi sp, sp, -16
856; RV32IM-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
857; RV32IM-NEXT:    addi a2, zero, 5
858; RV32IM-NEXT:    mv a3, zero
859; RV32IM-NEXT:    call __divdi3@plt
860; RV32IM-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
861; RV32IM-NEXT:    addi sp, sp, 16
862; RV32IM-NEXT:    ret
863;
864; RV64I-LABEL: sdiv64_constant:
865; RV64I:       # %bb.0:
866; RV64I-NEXT:    addi sp, sp, -16
867; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
868; RV64I-NEXT:    addi a1, zero, 5
869; RV64I-NEXT:    call __divdi3@plt
870; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
871; RV64I-NEXT:    addi sp, sp, 16
872; RV64I-NEXT:    ret
873;
874; RV64IM-LABEL: sdiv64_constant:
875; RV64IM:       # %bb.0:
876; RV64IM-NEXT:    lui a1, 13107
877; RV64IM-NEXT:    addiw a1, a1, 819
878; RV64IM-NEXT:    slli a1, a1, 12
879; RV64IM-NEXT:    addi a1, a1, 819
880; RV64IM-NEXT:    slli a1, a1, 12
881; RV64IM-NEXT:    addi a1, a1, 819
882; RV64IM-NEXT:    slli a1, a1, 13
883; RV64IM-NEXT:    addi a1, a1, 1639
884; RV64IM-NEXT:    mulh a0, a0, a1
885; RV64IM-NEXT:    srli a1, a0, 63
886; RV64IM-NEXT:    srai a0, a0, 1
887; RV64IM-NEXT:    add a0, a0, a1
888; RV64IM-NEXT:    ret
889  %1 = sdiv i64 %a, 5
890  ret i64 %1
891}
892
893define i64 @sdiv64_constant_lhs(i64 %a) nounwind {
894; RV32I-LABEL: sdiv64_constant_lhs:
895; RV32I:       # %bb.0:
896; RV32I-NEXT:    addi sp, sp, -16
897; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
898; RV32I-NEXT:    mv a3, a1
899; RV32I-NEXT:    mv a2, a0
900; RV32I-NEXT:    addi a0, zero, 10
901; RV32I-NEXT:    mv a1, zero
902; RV32I-NEXT:    call __divdi3@plt
903; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
904; RV32I-NEXT:    addi sp, sp, 16
905; RV32I-NEXT:    ret
906;
907; RV32IM-LABEL: sdiv64_constant_lhs:
908; RV32IM:       # %bb.0:
909; RV32IM-NEXT:    addi sp, sp, -16
910; RV32IM-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
911; RV32IM-NEXT:    mv a3, a1
912; RV32IM-NEXT:    mv a2, a0
913; RV32IM-NEXT:    addi a0, zero, 10
914; RV32IM-NEXT:    mv a1, zero
915; RV32IM-NEXT:    call __divdi3@plt
916; RV32IM-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
917; RV32IM-NEXT:    addi sp, sp, 16
918; RV32IM-NEXT:    ret
919;
920; RV64I-LABEL: sdiv64_constant_lhs:
921; RV64I:       # %bb.0:
922; RV64I-NEXT:    addi sp, sp, -16
923; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
924; RV64I-NEXT:    mv a1, a0
925; RV64I-NEXT:    addi a0, zero, 10
926; RV64I-NEXT:    call __divdi3@plt
927; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
928; RV64I-NEXT:    addi sp, sp, 16
929; RV64I-NEXT:    ret
930;
931; RV64IM-LABEL: sdiv64_constant_lhs:
932; RV64IM:       # %bb.0:
933; RV64IM-NEXT:    addi a1, zero, 10
934; RV64IM-NEXT:    div a0, a1, a0
935; RV64IM-NEXT:    ret
936  %1 = sdiv i64 10, %a
937  ret i64 %1
938}
939
940; Although this sdiv has two sexti32 operands, it shouldn't compile to divw on
941; RV64M as that wouldn't produce the correct result for e.g. INT_MIN/-1.
942
943define i64 @sdiv64_sext_operands(i32 %a, i32 %b) nounwind {
944; RV32I-LABEL: sdiv64_sext_operands:
945; RV32I:       # %bb.0:
946; RV32I-NEXT:    addi sp, sp, -16
947; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
948; RV32I-NEXT:    mv a2, a1
949; RV32I-NEXT:    srai a1, a0, 31
950; RV32I-NEXT:    srai a3, a2, 31
951; RV32I-NEXT:    call __divdi3@plt
952; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
953; RV32I-NEXT:    addi sp, sp, 16
954; RV32I-NEXT:    ret
955;
956; RV32IM-LABEL: sdiv64_sext_operands:
957; RV32IM:       # %bb.0:
958; RV32IM-NEXT:    addi sp, sp, -16
959; RV32IM-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
960; RV32IM-NEXT:    mv a2, a1
961; RV32IM-NEXT:    srai a1, a0, 31
962; RV32IM-NEXT:    srai a3, a2, 31
963; RV32IM-NEXT:    call __divdi3@plt
964; RV32IM-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
965; RV32IM-NEXT:    addi sp, sp, 16
966; RV32IM-NEXT:    ret
967;
968; RV64I-LABEL: sdiv64_sext_operands:
969; RV64I:       # %bb.0:
970; RV64I-NEXT:    addi sp, sp, -16
971; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
972; RV64I-NEXT:    sext.w a0, a0
973; RV64I-NEXT:    sext.w a1, a1
974; RV64I-NEXT:    call __divdi3@plt
975; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
976; RV64I-NEXT:    addi sp, sp, 16
977; RV64I-NEXT:    ret
978;
979; RV64IM-LABEL: sdiv64_sext_operands:
980; RV64IM:       # %bb.0:
981; RV64IM-NEXT:    sext.w a0, a0
982; RV64IM-NEXT:    sext.w a1, a1
983; RV64IM-NEXT:    div a0, a0, a1
984; RV64IM-NEXT:    ret
985  %1 = sext i32 %a to i64
986  %2 = sext i32 %b to i64
987  %3 = sdiv i64 %1, %2
988  ret i64 %3
989}
990
991define i8 @sdiv8(i8 %a, i8 %b) nounwind {
992; RV32I-LABEL: sdiv8:
993; RV32I:       # %bb.0:
994; RV32I-NEXT:    addi sp, sp, -16
995; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
996; RV32I-NEXT:    slli a0, a0, 24
997; RV32I-NEXT:    srai a0, a0, 24
998; RV32I-NEXT:    slli a1, a1, 24
999; RV32I-NEXT:    srai a1, a1, 24
1000; RV32I-NEXT:    call __divsi3@plt
1001; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1002; RV32I-NEXT:    addi sp, sp, 16
1003; RV32I-NEXT:    ret
1004;
1005; RV32IM-LABEL: sdiv8:
1006; RV32IM:       # %bb.0:
1007; RV32IM-NEXT:    slli a1, a1, 24
1008; RV32IM-NEXT:    srai a1, a1, 24
1009; RV32IM-NEXT:    slli a0, a0, 24
1010; RV32IM-NEXT:    srai a0, a0, 24
1011; RV32IM-NEXT:    div a0, a0, a1
1012; RV32IM-NEXT:    ret
1013;
1014; RV64I-LABEL: sdiv8:
1015; RV64I:       # %bb.0:
1016; RV64I-NEXT:    addi sp, sp, -16
1017; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1018; RV64I-NEXT:    slli a0, a0, 56
1019; RV64I-NEXT:    srai a0, a0, 56
1020; RV64I-NEXT:    slli a1, a1, 56
1021; RV64I-NEXT:    srai a1, a1, 56
1022; RV64I-NEXT:    call __divdi3@plt
1023; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1024; RV64I-NEXT:    addi sp, sp, 16
1025; RV64I-NEXT:    ret
1026;
1027; RV64IM-LABEL: sdiv8:
1028; RV64IM:       # %bb.0:
1029; RV64IM-NEXT:    slli a1, a1, 56
1030; RV64IM-NEXT:    srai a1, a1, 56
1031; RV64IM-NEXT:    slli a0, a0, 56
1032; RV64IM-NEXT:    srai a0, a0, 56
1033; RV64IM-NEXT:    divw a0, a0, a1
1034; RV64IM-NEXT:    ret
1035  %1 = sdiv i8 %a, %b
1036  ret i8 %1
1037}
1038
1039define i8 @sdiv8_constant(i8 %a) nounwind {
1040; RV32I-LABEL: sdiv8_constant:
1041; RV32I:       # %bb.0:
1042; RV32I-NEXT:    addi sp, sp, -16
1043; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1044; RV32I-NEXT:    slli a0, a0, 24
1045; RV32I-NEXT:    srai a0, a0, 24
1046; RV32I-NEXT:    addi a1, zero, 5
1047; RV32I-NEXT:    call __divsi3@plt
1048; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1049; RV32I-NEXT:    addi sp, sp, 16
1050; RV32I-NEXT:    ret
1051;
1052; RV32IM-LABEL: sdiv8_constant:
1053; RV32IM:       # %bb.0:
1054; RV32IM-NEXT:    slli a0, a0, 24
1055; RV32IM-NEXT:    srai a0, a0, 24
1056; RV32IM-NEXT:    addi a1, zero, 103
1057; RV32IM-NEXT:    mul a0, a0, a1
1058; RV32IM-NEXT:    srai a1, a0, 9
1059; RV32IM-NEXT:    srli a0, a0, 15
1060; RV32IM-NEXT:    andi a0, a0, 1
1061; RV32IM-NEXT:    add a0, a1, a0
1062; RV32IM-NEXT:    ret
1063;
1064; RV64I-LABEL: sdiv8_constant:
1065; RV64I:       # %bb.0:
1066; RV64I-NEXT:    addi sp, sp, -16
1067; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1068; RV64I-NEXT:    slli a0, a0, 56
1069; RV64I-NEXT:    srai a0, a0, 56
1070; RV64I-NEXT:    addi a1, zero, 5
1071; RV64I-NEXT:    call __divdi3@plt
1072; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1073; RV64I-NEXT:    addi sp, sp, 16
1074; RV64I-NEXT:    ret
1075;
1076; RV64IM-LABEL: sdiv8_constant:
1077; RV64IM:       # %bb.0:
1078; RV64IM-NEXT:    slli a0, a0, 56
1079; RV64IM-NEXT:    srai a0, a0, 56
1080; RV64IM-NEXT:    addi a1, zero, 103
1081; RV64IM-NEXT:    mul a0, a0, a1
1082; RV64IM-NEXT:    srai a1, a0, 9
1083; RV64IM-NEXT:    srli a0, a0, 15
1084; RV64IM-NEXT:    andi a0, a0, 1
1085; RV64IM-NEXT:    add a0, a1, a0
1086; RV64IM-NEXT:    ret
1087  %1 = sdiv i8 %a, 5
1088  ret i8 %1
1089}
1090
1091define i8 @sdiv8_pow2(i8 %a) nounwind {
1092; RV32I-LABEL: sdiv8_pow2:
1093; RV32I:       # %bb.0:
1094; RV32I-NEXT:    slli a1, a0, 24
1095; RV32I-NEXT:    srai a1, a1, 24
1096; RV32I-NEXT:    srli a1, a1, 12
1097; RV32I-NEXT:    andi a1, a1, 7
1098; RV32I-NEXT:    add a0, a0, a1
1099; RV32I-NEXT:    slli a0, a0, 24
1100; RV32I-NEXT:    srai a0, a0, 27
1101; RV32I-NEXT:    ret
1102;
1103; RV32IM-LABEL: sdiv8_pow2:
1104; RV32IM:       # %bb.0:
1105; RV32IM-NEXT:    slli a1, a0, 24
1106; RV32IM-NEXT:    srai a1, a1, 24
1107; RV32IM-NEXT:    srli a1, a1, 12
1108; RV32IM-NEXT:    andi a1, a1, 7
1109; RV32IM-NEXT:    add a0, a0, a1
1110; RV32IM-NEXT:    slli a0, a0, 24
1111; RV32IM-NEXT:    srai a0, a0, 27
1112; RV32IM-NEXT:    ret
1113;
1114; RV64I-LABEL: sdiv8_pow2:
1115; RV64I:       # %bb.0:
1116; RV64I-NEXT:    slli a1, a0, 56
1117; RV64I-NEXT:    srai a1, a1, 56
1118; RV64I-NEXT:    srli a1, a1, 12
1119; RV64I-NEXT:    andi a1, a1, 7
1120; RV64I-NEXT:    add a0, a0, a1
1121; RV64I-NEXT:    slli a0, a0, 56
1122; RV64I-NEXT:    srai a0, a0, 59
1123; RV64I-NEXT:    ret
1124;
1125; RV64IM-LABEL: sdiv8_pow2:
1126; RV64IM:       # %bb.0:
1127; RV64IM-NEXT:    slli a1, a0, 56
1128; RV64IM-NEXT:    srai a1, a1, 56
1129; RV64IM-NEXT:    srli a1, a1, 12
1130; RV64IM-NEXT:    andi a1, a1, 7
1131; RV64IM-NEXT:    add a0, a0, a1
1132; RV64IM-NEXT:    slli a0, a0, 56
1133; RV64IM-NEXT:    srai a0, a0, 59
1134; RV64IM-NEXT:    ret
1135  %1 = sdiv i8 %a, 8
1136  ret i8 %1
1137}
1138
1139define i8 @sdiv8_constant_lhs(i8 %a) nounwind {
1140; RV32I-LABEL: sdiv8_constant_lhs:
1141; RV32I:       # %bb.0:
1142; RV32I-NEXT:    addi sp, sp, -16
1143; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1144; RV32I-NEXT:    slli a0, a0, 24
1145; RV32I-NEXT:    srai a1, a0, 24
1146; RV32I-NEXT:    addi a0, zero, -10
1147; RV32I-NEXT:    call __divsi3@plt
1148; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1149; RV32I-NEXT:    addi sp, sp, 16
1150; RV32I-NEXT:    ret
1151;
1152; RV32IM-LABEL: sdiv8_constant_lhs:
1153; RV32IM:       # %bb.0:
1154; RV32IM-NEXT:    slli a0, a0, 24
1155; RV32IM-NEXT:    srai a0, a0, 24
1156; RV32IM-NEXT:    addi a1, zero, -10
1157; RV32IM-NEXT:    div a0, a1, a0
1158; RV32IM-NEXT:    ret
1159;
1160; RV64I-LABEL: sdiv8_constant_lhs:
1161; RV64I:       # %bb.0:
1162; RV64I-NEXT:    addi sp, sp, -16
1163; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1164; RV64I-NEXT:    slli a0, a0, 56
1165; RV64I-NEXT:    srai a1, a0, 56
1166; RV64I-NEXT:    addi a0, zero, -10
1167; RV64I-NEXT:    call __divdi3@plt
1168; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1169; RV64I-NEXT:    addi sp, sp, 16
1170; RV64I-NEXT:    ret
1171;
1172; RV64IM-LABEL: sdiv8_constant_lhs:
1173; RV64IM:       # %bb.0:
1174; RV64IM-NEXT:    slli a0, a0, 56
1175; RV64IM-NEXT:    srai a0, a0, 56
1176; RV64IM-NEXT:    addi a1, zero, -10
1177; RV64IM-NEXT:    divw a0, a1, a0
1178; RV64IM-NEXT:    ret
1179  %1 = sdiv i8 -10, %a
1180  ret i8 %1
1181}
1182
1183define i16 @sdiv16(i16 %a, i16 %b) nounwind {
1184; RV32I-LABEL: sdiv16:
1185; RV32I:       # %bb.0:
1186; RV32I-NEXT:    addi sp, sp, -16
1187; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1188; RV32I-NEXT:    slli a0, a0, 16
1189; RV32I-NEXT:    srai a0, a0, 16
1190; RV32I-NEXT:    slli a1, a1, 16
1191; RV32I-NEXT:    srai a1, a1, 16
1192; RV32I-NEXT:    call __divsi3@plt
1193; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1194; RV32I-NEXT:    addi sp, sp, 16
1195; RV32I-NEXT:    ret
1196;
1197; RV32IM-LABEL: sdiv16:
1198; RV32IM:       # %bb.0:
1199; RV32IM-NEXT:    slli a1, a1, 16
1200; RV32IM-NEXT:    srai a1, a1, 16
1201; RV32IM-NEXT:    slli a0, a0, 16
1202; RV32IM-NEXT:    srai a0, a0, 16
1203; RV32IM-NEXT:    div a0, a0, a1
1204; RV32IM-NEXT:    ret
1205;
1206; RV64I-LABEL: sdiv16:
1207; RV64I:       # %bb.0:
1208; RV64I-NEXT:    addi sp, sp, -16
1209; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1210; RV64I-NEXT:    slli a0, a0, 48
1211; RV64I-NEXT:    srai a0, a0, 48
1212; RV64I-NEXT:    slli a1, a1, 48
1213; RV64I-NEXT:    srai a1, a1, 48
1214; RV64I-NEXT:    call __divdi3@plt
1215; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1216; RV64I-NEXT:    addi sp, sp, 16
1217; RV64I-NEXT:    ret
1218;
1219; RV64IM-LABEL: sdiv16:
1220; RV64IM:       # %bb.0:
1221; RV64IM-NEXT:    slli a1, a1, 48
1222; RV64IM-NEXT:    srai a1, a1, 48
1223; RV64IM-NEXT:    slli a0, a0, 48
1224; RV64IM-NEXT:    srai a0, a0, 48
1225; RV64IM-NEXT:    divw a0, a0, a1
1226; RV64IM-NEXT:    ret
1227  %1 = sdiv i16 %a, %b
1228  ret i16 %1
1229}
1230
1231define i16 @sdiv16_constant(i16 %a) nounwind {
1232; RV32I-LABEL: sdiv16_constant:
1233; RV32I:       # %bb.0:
1234; RV32I-NEXT:    addi sp, sp, -16
1235; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1236; RV32I-NEXT:    slli a0, a0, 16
1237; RV32I-NEXT:    srai a0, a0, 16
1238; RV32I-NEXT:    addi a1, zero, 5
1239; RV32I-NEXT:    call __divsi3@plt
1240; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1241; RV32I-NEXT:    addi sp, sp, 16
1242; RV32I-NEXT:    ret
1243;
1244; RV32IM-LABEL: sdiv16_constant:
1245; RV32IM:       # %bb.0:
1246; RV32IM-NEXT:    slli a0, a0, 16
1247; RV32IM-NEXT:    srai a0, a0, 16
1248; RV32IM-NEXT:    lui a1, 6
1249; RV32IM-NEXT:    addi a1, a1, 1639
1250; RV32IM-NEXT:    mul a0, a0, a1
1251; RV32IM-NEXT:    srli a1, a0, 31
1252; RV32IM-NEXT:    srai a0, a0, 17
1253; RV32IM-NEXT:    add a0, a0, a1
1254; RV32IM-NEXT:    ret
1255;
1256; RV64I-LABEL: sdiv16_constant:
1257; RV64I:       # %bb.0:
1258; RV64I-NEXT:    addi sp, sp, -16
1259; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1260; RV64I-NEXT:    slli a0, a0, 48
1261; RV64I-NEXT:    srai a0, a0, 48
1262; RV64I-NEXT:    addi a1, zero, 5
1263; RV64I-NEXT:    call __divdi3@plt
1264; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1265; RV64I-NEXT:    addi sp, sp, 16
1266; RV64I-NEXT:    ret
1267;
1268; RV64IM-LABEL: sdiv16_constant:
1269; RV64IM:       # %bb.0:
1270; RV64IM-NEXT:    slli a0, a0, 48
1271; RV64IM-NEXT:    srai a0, a0, 48
1272; RV64IM-NEXT:    lui a1, 6
1273; RV64IM-NEXT:    addiw a1, a1, 1639
1274; RV64IM-NEXT:    mul a0, a0, a1
1275; RV64IM-NEXT:    srliw a1, a0, 31
1276; RV64IM-NEXT:    srai a0, a0, 17
1277; RV64IM-NEXT:    add a0, a0, a1
1278; RV64IM-NEXT:    ret
1279  %1 = sdiv i16 %a, 5
1280  ret i16 %1
1281}
1282
1283define i16 @sdiv16_pow2(i16 %a) nounwind {
1284; RV32I-LABEL: sdiv16_pow2:
1285; RV32I:       # %bb.0:
1286; RV32I-NEXT:    slli a1, a0, 16
1287; RV32I-NEXT:    srai a1, a1, 16
1288; RV32I-NEXT:    srli a1, a1, 28
1289; RV32I-NEXT:    andi a1, a1, 7
1290; RV32I-NEXT:    add a0, a0, a1
1291; RV32I-NEXT:    slli a0, a0, 16
1292; RV32I-NEXT:    srai a0, a0, 19
1293; RV32I-NEXT:    ret
1294;
1295; RV32IM-LABEL: sdiv16_pow2:
1296; RV32IM:       # %bb.0:
1297; RV32IM-NEXT:    slli a1, a0, 16
1298; RV32IM-NEXT:    srai a1, a1, 16
1299; RV32IM-NEXT:    srli a1, a1, 28
1300; RV32IM-NEXT:    andi a1, a1, 7
1301; RV32IM-NEXT:    add a0, a0, a1
1302; RV32IM-NEXT:    slli a0, a0, 16
1303; RV32IM-NEXT:    srai a0, a0, 19
1304; RV32IM-NEXT:    ret
1305;
1306; RV64I-LABEL: sdiv16_pow2:
1307; RV64I:       # %bb.0:
1308; RV64I-NEXT:    slli a1, a0, 48
1309; RV64I-NEXT:    srai a1, a1, 48
1310; RV64I-NEXT:    srli a1, a1, 28
1311; RV64I-NEXT:    andi a1, a1, 7
1312; RV64I-NEXT:    add a0, a0, a1
1313; RV64I-NEXT:    slli a0, a0, 48
1314; RV64I-NEXT:    srai a0, a0, 51
1315; RV64I-NEXT:    ret
1316;
1317; RV64IM-LABEL: sdiv16_pow2:
1318; RV64IM:       # %bb.0:
1319; RV64IM-NEXT:    slli a1, a0, 48
1320; RV64IM-NEXT:    srai a1, a1, 48
1321; RV64IM-NEXT:    srli a1, a1, 28
1322; RV64IM-NEXT:    andi a1, a1, 7
1323; RV64IM-NEXT:    add a0, a0, a1
1324; RV64IM-NEXT:    slli a0, a0, 48
1325; RV64IM-NEXT:    srai a0, a0, 51
1326; RV64IM-NEXT:    ret
1327  %1 = sdiv i16 %a, 8
1328  ret i16 %1
1329}
1330
1331define i16 @sdiv16_constant_lhs(i16 %a) nounwind {
1332; RV32I-LABEL: sdiv16_constant_lhs:
1333; RV32I:       # %bb.0:
1334; RV32I-NEXT:    addi sp, sp, -16
1335; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
1336; RV32I-NEXT:    slli a0, a0, 16
1337; RV32I-NEXT:    srai a1, a0, 16
1338; RV32I-NEXT:    addi a0, zero, -10
1339; RV32I-NEXT:    call __divsi3@plt
1340; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
1341; RV32I-NEXT:    addi sp, sp, 16
1342; RV32I-NEXT:    ret
1343;
1344; RV32IM-LABEL: sdiv16_constant_lhs:
1345; RV32IM:       # %bb.0:
1346; RV32IM-NEXT:    slli a0, a0, 16
1347; RV32IM-NEXT:    srai a0, a0, 16
1348; RV32IM-NEXT:    addi a1, zero, -10
1349; RV32IM-NEXT:    div a0, a1, a0
1350; RV32IM-NEXT:    ret
1351;
1352; RV64I-LABEL: sdiv16_constant_lhs:
1353; RV64I:       # %bb.0:
1354; RV64I-NEXT:    addi sp, sp, -16
1355; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
1356; RV64I-NEXT:    slli a0, a0, 48
1357; RV64I-NEXT:    srai a1, a0, 48
1358; RV64I-NEXT:    addi a0, zero, -10
1359; RV64I-NEXT:    call __divdi3@plt
1360; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
1361; RV64I-NEXT:    addi sp, sp, 16
1362; RV64I-NEXT:    ret
1363;
1364; RV64IM-LABEL: sdiv16_constant_lhs:
1365; RV64IM:       # %bb.0:
1366; RV64IM-NEXT:    slli a0, a0, 48
1367; RV64IM-NEXT:    srai a0, a0, 48
1368; RV64IM-NEXT:    addi a1, zero, -10
1369; RV64IM-NEXT:    divw a0, a1, a0
1370; RV64IM-NEXT:    ret
1371  %1 = sdiv i16 -10, %a
1372  ret i16 %1
1373}
1374