1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefixes=RV32,RV32IM %s
4; RUN: llc -mtriple=riscv32 -mattr=+m,+zba,+zbb \
5; RUN:    -verify-machineinstrs < %s \
6; RUN:   | FileCheck -check-prefixes=RV32,RV32IMZB %s
7; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
8; RUN:   | FileCheck -check-prefixes=RV64,RV64IM %s
9; RUN: llc -mtriple=riscv64 -mattr=+m,+zba,+zbb \
10; RUN:   -verify-machineinstrs < %s \
11; RUN:   | FileCheck -check-prefixes=RV64,RV64IMZB %s
12
13; Test that there is a single shift after the mul and no addition.
14define i32 @udiv_constant_no_add(i32 %a) nounwind {
15; RV32-LABEL: udiv_constant_no_add:
16; RV32:       # %bb.0:
17; RV32-NEXT:    lui a1, 838861
18; RV32-NEXT:    addi a1, a1, -819
19; RV32-NEXT:    mulhu a0, a0, a1
20; RV32-NEXT:    srli a0, a0, 2
21; RV32-NEXT:    ret
22;
23; RV64-LABEL: udiv_constant_no_add:
24; RV64:       # %bb.0:
25; RV64-NEXT:    slli a0, a0, 32
26; RV64-NEXT:    lui a1, 838861
27; RV64-NEXT:    addiw a1, a1, -819
28; RV64-NEXT:    slli a1, a1, 32
29; RV64-NEXT:    mulhu a0, a0, a1
30; RV64-NEXT:    srli a0, a0, 34
31; RV64-NEXT:    ret
32  %1 = udiv i32 %a, 5
33  ret i32 %1
34}
35
36; This constant requires a sub, shrli, add sequence after the mul.
37define i32 @udiv_constant_add(i32 %a) nounwind {
38; RV32-LABEL: udiv_constant_add:
39; RV32:       # %bb.0:
40; RV32-NEXT:    lui a1, 149797
41; RV32-NEXT:    addi a1, a1, -1755
42; RV32-NEXT:    mulhu a1, a0, a1
43; RV32-NEXT:    sub a0, a0, a1
44; RV32-NEXT:    srli a0, a0, 1
45; RV32-NEXT:    add a0, a0, a1
46; RV32-NEXT:    srli a0, a0, 2
47; RV32-NEXT:    ret
48;
49; RV64-LABEL: udiv_constant_add:
50; RV64:       # %bb.0:
51; RV64-NEXT:    slli a1, a0, 32
52; RV64-NEXT:    lui a2, 149797
53; RV64-NEXT:    addiw a2, a2, -1755
54; RV64-NEXT:    slli a2, a2, 32
55; RV64-NEXT:    mulhu a1, a1, a2
56; RV64-NEXT:    srli a1, a1, 32
57; RV64-NEXT:    subw a0, a0, a1
58; RV64-NEXT:    srliw a0, a0, 1
59; RV64-NEXT:    add a0, a0, a1
60; RV64-NEXT:    srli a0, a0, 2
61; RV64-NEXT:    ret
62  %1 = udiv i32 %a, 7
63  ret i32 %1
64}
65
66define i64 @udiv64_constant_no_add(i64 %a) nounwind {
67; RV32-LABEL: udiv64_constant_no_add:
68; RV32:       # %bb.0:
69; RV32-NEXT:    addi sp, sp, -16
70; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
71; RV32-NEXT:    li a2, 5
72; RV32-NEXT:    li a3, 0
73; RV32-NEXT:    call __udivdi3@plt
74; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
75; RV32-NEXT:    addi sp, sp, 16
76; RV32-NEXT:    ret
77;
78; RV64-LABEL: udiv64_constant_no_add:
79; RV64:       # %bb.0:
80; RV64-NEXT:    lui a1, %hi(.LCPI2_0)
81; RV64-NEXT:    ld a1, %lo(.LCPI2_0)(a1)
82; RV64-NEXT:    mulhu a0, a0, a1
83; RV64-NEXT:    srli a0, a0, 2
84; RV64-NEXT:    ret
85  %1 = udiv i64 %a, 5
86  ret i64 %1
87}
88
89define i64 @udiv64_constant_add(i64 %a) nounwind {
90; RV32-LABEL: udiv64_constant_add:
91; RV32:       # %bb.0:
92; RV32-NEXT:    addi sp, sp, -16
93; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
94; RV32-NEXT:    li a2, 7
95; RV32-NEXT:    li a3, 0
96; RV32-NEXT:    call __udivdi3@plt
97; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
98; RV32-NEXT:    addi sp, sp, 16
99; RV32-NEXT:    ret
100;
101; RV64-LABEL: udiv64_constant_add:
102; RV64:       # %bb.0:
103; RV64-NEXT:    lui a1, %hi(.LCPI3_0)
104; RV64-NEXT:    ld a1, %lo(.LCPI3_0)(a1)
105; RV64-NEXT:    mulhu a1, a0, a1
106; RV64-NEXT:    sub a0, a0, a1
107; RV64-NEXT:    srli a0, a0, 1
108; RV64-NEXT:    add a0, a0, a1
109; RV64-NEXT:    srli a0, a0, 2
110; RV64-NEXT:    ret
111  %1 = udiv i64 %a, 7
112  ret i64 %1
113}
114
115define i8 @udiv8_constant_no_add(i8 %a) nounwind {
116; RV32-LABEL: udiv8_constant_no_add:
117; RV32:       # %bb.0:
118; RV32-NEXT:    andi a0, a0, 255
119; RV32-NEXT:    li a1, 205
120; RV32-NEXT:    mul a0, a0, a1
121; RV32-NEXT:    srli a0, a0, 10
122; RV32-NEXT:    ret
123;
124; RV64-LABEL: udiv8_constant_no_add:
125; RV64:       # %bb.0:
126; RV64-NEXT:    andi a0, a0, 255
127; RV64-NEXT:    li a1, 205
128; RV64-NEXT:    mul a0, a0, a1
129; RV64-NEXT:    srli a0, a0, 10
130; RV64-NEXT:    ret
131  %1 = udiv i8 %a, 5
132  ret i8 %1
133}
134
135define i8 @udiv8_constant_add(i8 %a) nounwind {
136; RV32IM-LABEL: udiv8_constant_add:
137; RV32IM:       # %bb.0:
138; RV32IM-NEXT:    andi a1, a0, 255
139; RV32IM-NEXT:    li a2, 37
140; RV32IM-NEXT:    mul a1, a1, a2
141; RV32IM-NEXT:    srli a1, a1, 8
142; RV32IM-NEXT:    sub a0, a0, a1
143; RV32IM-NEXT:    slli a0, a0, 24
144; RV32IM-NEXT:    srli a0, a0, 25
145; RV32IM-NEXT:    add a0, a0, a1
146; RV32IM-NEXT:    srli a0, a0, 2
147; RV32IM-NEXT:    ret
148;
149; RV32IMZB-LABEL: udiv8_constant_add:
150; RV32IMZB:       # %bb.0:
151; RV32IMZB-NEXT:    andi a1, a0, 255
152; RV32IMZB-NEXT:    sh3add a2, a1, a1
153; RV32IMZB-NEXT:    sh2add a1, a2, a1
154; RV32IMZB-NEXT:    srli a1, a1, 8
155; RV32IMZB-NEXT:    sub a0, a0, a1
156; RV32IMZB-NEXT:    slli a0, a0, 24
157; RV32IMZB-NEXT:    srli a0, a0, 25
158; RV32IMZB-NEXT:    add a0, a0, a1
159; RV32IMZB-NEXT:    srli a0, a0, 2
160; RV32IMZB-NEXT:    ret
161;
162; RV64IM-LABEL: udiv8_constant_add:
163; RV64IM:       # %bb.0:
164; RV64IM-NEXT:    andi a1, a0, 255
165; RV64IM-NEXT:    li a2, 37
166; RV64IM-NEXT:    mul a1, a1, a2
167; RV64IM-NEXT:    srli a1, a1, 8
168; RV64IM-NEXT:    subw a0, a0, a1
169; RV64IM-NEXT:    slli a0, a0, 56
170; RV64IM-NEXT:    srli a0, a0, 57
171; RV64IM-NEXT:    add a0, a0, a1
172; RV64IM-NEXT:    srli a0, a0, 2
173; RV64IM-NEXT:    ret
174;
175; RV64IMZB-LABEL: udiv8_constant_add:
176; RV64IMZB:       # %bb.0:
177; RV64IMZB-NEXT:    andi a1, a0, 255
178; RV64IMZB-NEXT:    sh3add a2, a1, a1
179; RV64IMZB-NEXT:    sh2add a1, a2, a1
180; RV64IMZB-NEXT:    srli a1, a1, 8
181; RV64IMZB-NEXT:    subw a0, a0, a1
182; RV64IMZB-NEXT:    slli a0, a0, 56
183; RV64IMZB-NEXT:    srli a0, a0, 57
184; RV64IMZB-NEXT:    add a0, a0, a1
185; RV64IMZB-NEXT:    srli a0, a0, 2
186; RV64IMZB-NEXT:    ret
187  %1 = udiv i8 %a, 7
188  ret i8 %1
189}
190
191define i16 @udiv16_constant_no_add(i16 %a) nounwind {
192; RV32-LABEL: udiv16_constant_no_add:
193; RV32:       # %bb.0:
194; RV32-NEXT:    slli a0, a0, 16
195; RV32-NEXT:    lui a1, 838864
196; RV32-NEXT:    mulhu a0, a0, a1
197; RV32-NEXT:    srli a0, a0, 18
198; RV32-NEXT:    ret
199;
200; RV64-LABEL: udiv16_constant_no_add:
201; RV64:       # %bb.0:
202; RV64-NEXT:    lui a1, 52429
203; RV64-NEXT:    slli a1, a1, 4
204; RV64-NEXT:    slli a0, a0, 48
205; RV64-NEXT:    mulhu a0, a0, a1
206; RV64-NEXT:    srli a0, a0, 18
207; RV64-NEXT:    ret
208  %1 = udiv i16 %a, 5
209  ret i16 %1
210}
211
212define i16 @udiv16_constant_add(i16 %a) nounwind {
213; RV32-LABEL: udiv16_constant_add:
214; RV32:       # %bb.0:
215; RV32-NEXT:    slli a1, a0, 16
216; RV32-NEXT:    lui a2, 149808
217; RV32-NEXT:    mulhu a1, a1, a2
218; RV32-NEXT:    srli a1, a1, 16
219; RV32-NEXT:    sub a0, a0, a1
220; RV32-NEXT:    slli a0, a0, 16
221; RV32-NEXT:    srli a0, a0, 17
222; RV32-NEXT:    add a0, a0, a1
223; RV32-NEXT:    srli a0, a0, 2
224; RV32-NEXT:    ret
225;
226; RV64-LABEL: udiv16_constant_add:
227; RV64:       # %bb.0:
228; RV64-NEXT:    slli a1, a0, 48
229; RV64-NEXT:    lui a2, 149808
230; RV64-NEXT:    mulhu a1, a1, a2
231; RV64-NEXT:    srli a1, a1, 16
232; RV64-NEXT:    subw a0, a0, a1
233; RV64-NEXT:    slli a0, a0, 48
234; RV64-NEXT:    srli a0, a0, 49
235; RV64-NEXT:    add a0, a0, a1
236; RV64-NEXT:    srli a0, a0, 2
237; RV64-NEXT:    ret
238  %1 = udiv i16 %a, 7
239  ret i16 %1
240}
241
242; Test the simplest case a srli and an add after the mul. No srai.
243define i32 @sdiv_constant_no_srai(i32 %a) nounwind {
244; RV32-LABEL: sdiv_constant_no_srai:
245; RV32:       # %bb.0:
246; RV32-NEXT:    lui a1, 349525
247; RV32-NEXT:    addi a1, a1, 1366
248; RV32-NEXT:    mulh a0, a0, a1
249; RV32-NEXT:    srli a1, a0, 31
250; RV32-NEXT:    add a0, a0, a1
251; RV32-NEXT:    ret
252;
253; RV64-LABEL: sdiv_constant_no_srai:
254; RV64:       # %bb.0:
255; RV64-NEXT:    sext.w a0, a0
256; RV64-NEXT:    lui a1, 349525
257; RV64-NEXT:    addiw a1, a1, 1366
258; RV64-NEXT:    mul a0, a0, a1
259; RV64-NEXT:    srli a1, a0, 63
260; RV64-NEXT:    srli a0, a0, 32
261; RV64-NEXT:    addw a0, a0, a1
262; RV64-NEXT:    ret
263  %1 = sdiv i32 %a, 3
264  ret i32 %1
265}
266
267; This constant requires an srai between the mul and the add.
268define i32 @sdiv_constant_srai(i32 %a) nounwind {
269; RV32-LABEL: sdiv_constant_srai:
270; RV32:       # %bb.0:
271; RV32-NEXT:    lui a1, 419430
272; RV32-NEXT:    addi a1, a1, 1639
273; RV32-NEXT:    mulh a0, a0, a1
274; RV32-NEXT:    srli a1, a0, 31
275; RV32-NEXT:    srai a0, a0, 1
276; RV32-NEXT:    add a0, a0, a1
277; RV32-NEXT:    ret
278;
279; RV64-LABEL: sdiv_constant_srai:
280; RV64:       # %bb.0:
281; RV64-NEXT:    sext.w a0, a0
282; RV64-NEXT:    lui a1, 419430
283; RV64-NEXT:    addiw a1, a1, 1639
284; RV64-NEXT:    mul a0, a0, a1
285; RV64-NEXT:    srli a1, a0, 63
286; RV64-NEXT:    srai a0, a0, 33
287; RV64-NEXT:    add a0, a0, a1
288; RV64-NEXT:    ret
289  %1 = sdiv i32 %a, 5
290  ret i32 %1
291}
292
293; This constant requires an add and an srai after the mul.
294define i32 @sdiv_constant_add_srai(i32 %a) nounwind {
295; RV32-LABEL: sdiv_constant_add_srai:
296; RV32:       # %bb.0:
297; RV32-NEXT:    lui a1, 599186
298; RV32-NEXT:    addi a1, a1, 1171
299; RV32-NEXT:    mulh a1, a0, a1
300; RV32-NEXT:    add a0, a1, a0
301; RV32-NEXT:    srli a1, a0, 31
302; RV32-NEXT:    srai a0, a0, 2
303; RV32-NEXT:    add a0, a0, a1
304; RV32-NEXT:    ret
305;
306; RV64-LABEL: sdiv_constant_add_srai:
307; RV64:       # %bb.0:
308; RV64-NEXT:    sext.w a1, a0
309; RV64-NEXT:    lui a2, 599186
310; RV64-NEXT:    addiw a2, a2, 1171
311; RV64-NEXT:    mul a1, a1, a2
312; RV64-NEXT:    srli a1, a1, 32
313; RV64-NEXT:    addw a0, a1, a0
314; RV64-NEXT:    srliw a1, a0, 31
315; RV64-NEXT:    sraiw a0, a0, 2
316; RV64-NEXT:    add a0, a0, a1
317; RV64-NEXT:    ret
318  %1 = sdiv i32 %a, 7
319  ret i32 %1
320}
321
322; This constant requires a sub and an srai after the mul.
323define i32 @sdiv_constant_sub_srai(i32 %a) nounwind {
324; RV32-LABEL: sdiv_constant_sub_srai:
325; RV32:       # %bb.0:
326; RV32-NEXT:    lui a1, 449390
327; RV32-NEXT:    addi a1, a1, -1171
328; RV32-NEXT:    mulh a1, a0, a1
329; RV32-NEXT:    sub a0, a1, a0
330; RV32-NEXT:    srli a1, a0, 31
331; RV32-NEXT:    srai a0, a0, 2
332; RV32-NEXT:    add a0, a0, a1
333; RV32-NEXT:    ret
334;
335; RV64-LABEL: sdiv_constant_sub_srai:
336; RV64:       # %bb.0:
337; RV64-NEXT:    sext.w a1, a0
338; RV64-NEXT:    lui a2, 449390
339; RV64-NEXT:    addiw a2, a2, -1171
340; RV64-NEXT:    mul a1, a1, a2
341; RV64-NEXT:    srli a1, a1, 32
342; RV64-NEXT:    subw a0, a1, a0
343; RV64-NEXT:    srliw a1, a0, 31
344; RV64-NEXT:    sraiw a0, a0, 2
345; RV64-NEXT:    add a0, a0, a1
346; RV64-NEXT:    ret
347  %1 = sdiv i32 %a, -7
348  ret i32 %1
349}
350
351define i64 @sdiv64_constant_no_srai(i64 %a) nounwind {
352; RV32-LABEL: sdiv64_constant_no_srai:
353; RV32:       # %bb.0:
354; RV32-NEXT:    addi sp, sp, -16
355; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
356; RV32-NEXT:    li a2, 3
357; RV32-NEXT:    li a3, 0
358; RV32-NEXT:    call __divdi3@plt
359; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
360; RV32-NEXT:    addi sp, sp, 16
361; RV32-NEXT:    ret
362;
363; RV64-LABEL: sdiv64_constant_no_srai:
364; RV64:       # %bb.0:
365; RV64-NEXT:    lui a1, %hi(.LCPI12_0)
366; RV64-NEXT:    ld a1, %lo(.LCPI12_0)(a1)
367; RV64-NEXT:    mulh a0, a0, a1
368; RV64-NEXT:    srli a1, a0, 63
369; RV64-NEXT:    add a0, a0, a1
370; RV64-NEXT:    ret
371  %1 = sdiv i64 %a, 3
372  ret i64 %1
373}
374
375define i64 @sdiv64_constant_srai(i64 %a) nounwind {
376; RV32-LABEL: sdiv64_constant_srai:
377; RV32:       # %bb.0:
378; RV32-NEXT:    addi sp, sp, -16
379; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
380; RV32-NEXT:    li a2, 5
381; RV32-NEXT:    li a3, 0
382; RV32-NEXT:    call __divdi3@plt
383; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
384; RV32-NEXT:    addi sp, sp, 16
385; RV32-NEXT:    ret
386;
387; RV64-LABEL: sdiv64_constant_srai:
388; RV64:       # %bb.0:
389; RV64-NEXT:    lui a1, %hi(.LCPI13_0)
390; RV64-NEXT:    ld a1, %lo(.LCPI13_0)(a1)
391; RV64-NEXT:    mulh a0, a0, a1
392; RV64-NEXT:    srli a1, a0, 63
393; RV64-NEXT:    srai a0, a0, 1
394; RV64-NEXT:    add a0, a0, a1
395; RV64-NEXT:    ret
396  %1 = sdiv i64 %a, 5
397  ret i64 %1
398}
399
400define i64 @sdiv64_constant_add_srai(i64 %a) nounwind {
401; RV32-LABEL: sdiv64_constant_add_srai:
402; RV32:       # %bb.0:
403; RV32-NEXT:    addi sp, sp, -16
404; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
405; RV32-NEXT:    li a2, 15
406; RV32-NEXT:    li a3, 0
407; RV32-NEXT:    call __divdi3@plt
408; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
409; RV32-NEXT:    addi sp, sp, 16
410; RV32-NEXT:    ret
411;
412; RV64-LABEL: sdiv64_constant_add_srai:
413; RV64:       # %bb.0:
414; RV64-NEXT:    lui a1, %hi(.LCPI14_0)
415; RV64-NEXT:    ld a1, %lo(.LCPI14_0)(a1)
416; RV64-NEXT:    mulh a1, a0, a1
417; RV64-NEXT:    add a0, a1, a0
418; RV64-NEXT:    srli a1, a0, 63
419; RV64-NEXT:    srai a0, a0, 3
420; RV64-NEXT:    add a0, a0, a1
421; RV64-NEXT:    ret
422  %1 = sdiv i64 %a, 15
423  ret i64 %1
424}
425
426define i64 @sdiv64_constant_sub_srai(i64 %a) nounwind {
427; RV32-LABEL: sdiv64_constant_sub_srai:
428; RV32:       # %bb.0:
429; RV32-NEXT:    addi sp, sp, -16
430; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
431; RV32-NEXT:    li a2, -3
432; RV32-NEXT:    li a3, -1
433; RV32-NEXT:    call __divdi3@plt
434; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
435; RV32-NEXT:    addi sp, sp, 16
436; RV32-NEXT:    ret
437;
438; RV64-LABEL: sdiv64_constant_sub_srai:
439; RV64:       # %bb.0:
440; RV64-NEXT:    lui a1, %hi(.LCPI15_0)
441; RV64-NEXT:    ld a1, %lo(.LCPI15_0)(a1)
442; RV64-NEXT:    mulh a1, a0, a1
443; RV64-NEXT:    sub a0, a1, a0
444; RV64-NEXT:    srli a1, a0, 63
445; RV64-NEXT:    srai a0, a0, 1
446; RV64-NEXT:    add a0, a0, a1
447; RV64-NEXT:    ret
448  %1 = sdiv i64 %a, -3
449  ret i64 %1
450}
451
452define i8 @sdiv8_constant_no_srai(i8 %a) nounwind {
453; RV32IM-LABEL: sdiv8_constant_no_srai:
454; RV32IM:       # %bb.0:
455; RV32IM-NEXT:    slli a0, a0, 24
456; RV32IM-NEXT:    srai a0, a0, 24
457; RV32IM-NEXT:    li a1, 86
458; RV32IM-NEXT:    mul a0, a0, a1
459; RV32IM-NEXT:    srli a1, a0, 8
460; RV32IM-NEXT:    slli a0, a0, 16
461; RV32IM-NEXT:    srli a0, a0, 31
462; RV32IM-NEXT:    add a0, a1, a0
463; RV32IM-NEXT:    ret
464;
465; RV32IMZB-LABEL: sdiv8_constant_no_srai:
466; RV32IMZB:       # %bb.0:
467; RV32IMZB-NEXT:    sext.b a0, a0
468; RV32IMZB-NEXT:    li a1, 86
469; RV32IMZB-NEXT:    mul a0, a0, a1
470; RV32IMZB-NEXT:    srli a1, a0, 8
471; RV32IMZB-NEXT:    slli a0, a0, 16
472; RV32IMZB-NEXT:    srli a0, a0, 31
473; RV32IMZB-NEXT:    add a0, a1, a0
474; RV32IMZB-NEXT:    ret
475;
476; RV64IM-LABEL: sdiv8_constant_no_srai:
477; RV64IM:       # %bb.0:
478; RV64IM-NEXT:    slli a0, a0, 56
479; RV64IM-NEXT:    srai a0, a0, 56
480; RV64IM-NEXT:    li a1, 86
481; RV64IM-NEXT:    mul a0, a0, a1
482; RV64IM-NEXT:    srli a1, a0, 8
483; RV64IM-NEXT:    slli a0, a0, 48
484; RV64IM-NEXT:    srli a0, a0, 63
485; RV64IM-NEXT:    add a0, a1, a0
486; RV64IM-NEXT:    ret
487;
488; RV64IMZB-LABEL: sdiv8_constant_no_srai:
489; RV64IMZB:       # %bb.0:
490; RV64IMZB-NEXT:    sext.b a0, a0
491; RV64IMZB-NEXT:    li a1, 86
492; RV64IMZB-NEXT:    mul a0, a0, a1
493; RV64IMZB-NEXT:    srli a1, a0, 8
494; RV64IMZB-NEXT:    slli a0, a0, 48
495; RV64IMZB-NEXT:    srli a0, a0, 63
496; RV64IMZB-NEXT:    add a0, a1, a0
497; RV64IMZB-NEXT:    ret
498  %1 = sdiv i8 %a, 3
499  ret i8 %1
500}
501
502define i8 @sdiv8_constant_srai(i8 %a) nounwind {
503; RV32IM-LABEL: sdiv8_constant_srai:
504; RV32IM:       # %bb.0:
505; RV32IM-NEXT:    slli a0, a0, 24
506; RV32IM-NEXT:    srai a0, a0, 24
507; RV32IM-NEXT:    li a1, 103
508; RV32IM-NEXT:    mul a0, a0, a1
509; RV32IM-NEXT:    srai a1, a0, 9
510; RV32IM-NEXT:    slli a0, a0, 16
511; RV32IM-NEXT:    srli a0, a0, 31
512; RV32IM-NEXT:    add a0, a1, a0
513; RV32IM-NEXT:    ret
514;
515; RV32IMZB-LABEL: sdiv8_constant_srai:
516; RV32IMZB:       # %bb.0:
517; RV32IMZB-NEXT:    sext.b a0, a0
518; RV32IMZB-NEXT:    li a1, 103
519; RV32IMZB-NEXT:    mul a0, a0, a1
520; RV32IMZB-NEXT:    srai a1, a0, 9
521; RV32IMZB-NEXT:    slli a0, a0, 16
522; RV32IMZB-NEXT:    srli a0, a0, 31
523; RV32IMZB-NEXT:    add a0, a1, a0
524; RV32IMZB-NEXT:    ret
525;
526; RV64IM-LABEL: sdiv8_constant_srai:
527; RV64IM:       # %bb.0:
528; RV64IM-NEXT:    slli a0, a0, 56
529; RV64IM-NEXT:    srai a0, a0, 56
530; RV64IM-NEXT:    li a1, 103
531; RV64IM-NEXT:    mul a0, a0, a1
532; RV64IM-NEXT:    srai a1, a0, 9
533; RV64IM-NEXT:    slli a0, a0, 48
534; RV64IM-NEXT:    srli a0, a0, 63
535; RV64IM-NEXT:    add a0, a1, a0
536; RV64IM-NEXT:    ret
537;
538; RV64IMZB-LABEL: sdiv8_constant_srai:
539; RV64IMZB:       # %bb.0:
540; RV64IMZB-NEXT:    sext.b a0, a0
541; RV64IMZB-NEXT:    li a1, 103
542; RV64IMZB-NEXT:    mul a0, a0, a1
543; RV64IMZB-NEXT:    srai a1, a0, 9
544; RV64IMZB-NEXT:    slli a0, a0, 48
545; RV64IMZB-NEXT:    srli a0, a0, 63
546; RV64IMZB-NEXT:    add a0, a1, a0
547; RV64IMZB-NEXT:    ret
548  %1 = sdiv i8 %a, 5
549  ret i8 %1
550}
551
552define i8 @sdiv8_constant_add_srai(i8 %a) nounwind {
553; RV32IM-LABEL: sdiv8_constant_add_srai:
554; RV32IM:       # %bb.0:
555; RV32IM-NEXT:    slli a1, a0, 24
556; RV32IM-NEXT:    srai a1, a1, 24
557; RV32IM-NEXT:    li a2, -109
558; RV32IM-NEXT:    mul a1, a1, a2
559; RV32IM-NEXT:    srli a1, a1, 8
560; RV32IM-NEXT:    add a0, a1, a0
561; RV32IM-NEXT:    slli a0, a0, 24
562; RV32IM-NEXT:    srli a1, a0, 31
563; RV32IM-NEXT:    srai a0, a0, 26
564; RV32IM-NEXT:    add a0, a0, a1
565; RV32IM-NEXT:    ret
566;
567; RV32IMZB-LABEL: sdiv8_constant_add_srai:
568; RV32IMZB:       # %bb.0:
569; RV32IMZB-NEXT:    sext.b a1, a0
570; RV32IMZB-NEXT:    li a2, -109
571; RV32IMZB-NEXT:    mul a1, a1, a2
572; RV32IMZB-NEXT:    srli a1, a1, 8
573; RV32IMZB-NEXT:    add a0, a1, a0
574; RV32IMZB-NEXT:    slli a0, a0, 24
575; RV32IMZB-NEXT:    srli a1, a0, 31
576; RV32IMZB-NEXT:    srai a0, a0, 26
577; RV32IMZB-NEXT:    add a0, a0, a1
578; RV32IMZB-NEXT:    ret
579;
580; RV64IM-LABEL: sdiv8_constant_add_srai:
581; RV64IM:       # %bb.0:
582; RV64IM-NEXT:    slli a1, a0, 56
583; RV64IM-NEXT:    srai a1, a1, 56
584; RV64IM-NEXT:    li a2, -109
585; RV64IM-NEXT:    mul a1, a1, a2
586; RV64IM-NEXT:    srli a1, a1, 8
587; RV64IM-NEXT:    addw a0, a1, a0
588; RV64IM-NEXT:    slli a0, a0, 56
589; RV64IM-NEXT:    srli a1, a0, 63
590; RV64IM-NEXT:    srai a0, a0, 58
591; RV64IM-NEXT:    add a0, a0, a1
592; RV64IM-NEXT:    ret
593;
594; RV64IMZB-LABEL: sdiv8_constant_add_srai:
595; RV64IMZB:       # %bb.0:
596; RV64IMZB-NEXT:    sext.b a1, a0
597; RV64IMZB-NEXT:    li a2, -109
598; RV64IMZB-NEXT:    mul a1, a1, a2
599; RV64IMZB-NEXT:    srli a1, a1, 8
600; RV64IMZB-NEXT:    addw a0, a1, a0
601; RV64IMZB-NEXT:    slli a0, a0, 56
602; RV64IMZB-NEXT:    srli a1, a0, 63
603; RV64IMZB-NEXT:    srai a0, a0, 58
604; RV64IMZB-NEXT:    add a0, a0, a1
605; RV64IMZB-NEXT:    ret
606  %1 = sdiv i8 %a, 7
607  ret i8 %1
608}
609
610define i8 @sdiv8_constant_sub_srai(i8 %a) nounwind {
611; RV32IM-LABEL: sdiv8_constant_sub_srai:
612; RV32IM:       # %bb.0:
613; RV32IM-NEXT:    slli a1, a0, 24
614; RV32IM-NEXT:    srai a1, a1, 24
615; RV32IM-NEXT:    li a2, 109
616; RV32IM-NEXT:    mul a1, a1, a2
617; RV32IM-NEXT:    srli a1, a1, 8
618; RV32IM-NEXT:    sub a0, a1, a0
619; RV32IM-NEXT:    slli a0, a0, 24
620; RV32IM-NEXT:    srli a1, a0, 31
621; RV32IM-NEXT:    srai a0, a0, 26
622; RV32IM-NEXT:    add a0, a0, a1
623; RV32IM-NEXT:    ret
624;
625; RV32IMZB-LABEL: sdiv8_constant_sub_srai:
626; RV32IMZB:       # %bb.0:
627; RV32IMZB-NEXT:    sext.b a1, a0
628; RV32IMZB-NEXT:    li a2, 109
629; RV32IMZB-NEXT:    mul a1, a1, a2
630; RV32IMZB-NEXT:    srli a1, a1, 8
631; RV32IMZB-NEXT:    sub a0, a1, a0
632; RV32IMZB-NEXT:    slli a0, a0, 24
633; RV32IMZB-NEXT:    srli a1, a0, 31
634; RV32IMZB-NEXT:    srai a0, a0, 26
635; RV32IMZB-NEXT:    add a0, a0, a1
636; RV32IMZB-NEXT:    ret
637;
638; RV64IM-LABEL: sdiv8_constant_sub_srai:
639; RV64IM:       # %bb.0:
640; RV64IM-NEXT:    slli a1, a0, 56
641; RV64IM-NEXT:    srai a1, a1, 56
642; RV64IM-NEXT:    li a2, 109
643; RV64IM-NEXT:    mul a1, a1, a2
644; RV64IM-NEXT:    srli a1, a1, 8
645; RV64IM-NEXT:    subw a0, a1, a0
646; RV64IM-NEXT:    slli a0, a0, 56
647; RV64IM-NEXT:    srli a1, a0, 63
648; RV64IM-NEXT:    srai a0, a0, 58
649; RV64IM-NEXT:    add a0, a0, a1
650; RV64IM-NEXT:    ret
651;
652; RV64IMZB-LABEL: sdiv8_constant_sub_srai:
653; RV64IMZB:       # %bb.0:
654; RV64IMZB-NEXT:    sext.b a1, a0
655; RV64IMZB-NEXT:    li a2, 109
656; RV64IMZB-NEXT:    mul a1, a1, a2
657; RV64IMZB-NEXT:    srli a1, a1, 8
658; RV64IMZB-NEXT:    subw a0, a1, a0
659; RV64IMZB-NEXT:    slli a0, a0, 56
660; RV64IMZB-NEXT:    srli a1, a0, 63
661; RV64IMZB-NEXT:    srai a0, a0, 58
662; RV64IMZB-NEXT:    add a0, a0, a1
663; RV64IMZB-NEXT:    ret
664  %1 = sdiv i8 %a, -7
665  ret i8 %1
666}
667
668define i16 @sdiv16_constant_no_srai(i16 %a) nounwind {
669; RV32IM-LABEL: sdiv16_constant_no_srai:
670; RV32IM:       # %bb.0:
671; RV32IM-NEXT:    slli a0, a0, 16
672; RV32IM-NEXT:    srai a0, a0, 16
673; RV32IM-NEXT:    lui a1, 5
674; RV32IM-NEXT:    addi a1, a1, 1366
675; RV32IM-NEXT:    mul a0, a0, a1
676; RV32IM-NEXT:    srli a1, a0, 31
677; RV32IM-NEXT:    srli a0, a0, 16
678; RV32IM-NEXT:    add a0, a0, a1
679; RV32IM-NEXT:    ret
680;
681; RV32IMZB-LABEL: sdiv16_constant_no_srai:
682; RV32IMZB:       # %bb.0:
683; RV32IMZB-NEXT:    sext.h a0, a0
684; RV32IMZB-NEXT:    lui a1, 5
685; RV32IMZB-NEXT:    addi a1, a1, 1366
686; RV32IMZB-NEXT:    mul a0, a0, a1
687; RV32IMZB-NEXT:    srli a1, a0, 31
688; RV32IMZB-NEXT:    srli a0, a0, 16
689; RV32IMZB-NEXT:    add a0, a0, a1
690; RV32IMZB-NEXT:    ret
691;
692; RV64IM-LABEL: sdiv16_constant_no_srai:
693; RV64IM:       # %bb.0:
694; RV64IM-NEXT:    slli a0, a0, 48
695; RV64IM-NEXT:    srai a0, a0, 48
696; RV64IM-NEXT:    lui a1, 5
697; RV64IM-NEXT:    addiw a1, a1, 1366
698; RV64IM-NEXT:    mul a0, a0, a1
699; RV64IM-NEXT:    srliw a1, a0, 31
700; RV64IM-NEXT:    srli a0, a0, 16
701; RV64IM-NEXT:    add a0, a0, a1
702; RV64IM-NEXT:    ret
703;
704; RV64IMZB-LABEL: sdiv16_constant_no_srai:
705; RV64IMZB:       # %bb.0:
706; RV64IMZB-NEXT:    sext.h a0, a0
707; RV64IMZB-NEXT:    lui a1, 5
708; RV64IMZB-NEXT:    addiw a1, a1, 1366
709; RV64IMZB-NEXT:    mul a0, a0, a1
710; RV64IMZB-NEXT:    srliw a1, a0, 31
711; RV64IMZB-NEXT:    srli a0, a0, 16
712; RV64IMZB-NEXT:    add a0, a0, a1
713; RV64IMZB-NEXT:    ret
714  %1 = sdiv i16 %a, 3
715  ret i16 %1
716}
717
718define i16 @sdiv16_constant_srai(i16 %a) nounwind {
719; RV32IM-LABEL: sdiv16_constant_srai:
720; RV32IM:       # %bb.0:
721; RV32IM-NEXT:    slli a0, a0, 16
722; RV32IM-NEXT:    srai a0, a0, 16
723; RV32IM-NEXT:    lui a1, 6
724; RV32IM-NEXT:    addi a1, a1, 1639
725; RV32IM-NEXT:    mul a0, a0, a1
726; RV32IM-NEXT:    srli a1, a0, 31
727; RV32IM-NEXT:    srai a0, a0, 17
728; RV32IM-NEXT:    add a0, a0, a1
729; RV32IM-NEXT:    ret
730;
731; RV32IMZB-LABEL: sdiv16_constant_srai:
732; RV32IMZB:       # %bb.0:
733; RV32IMZB-NEXT:    sext.h a0, a0
734; RV32IMZB-NEXT:    lui a1, 6
735; RV32IMZB-NEXT:    addi a1, a1, 1639
736; RV32IMZB-NEXT:    mul a0, a0, a1
737; RV32IMZB-NEXT:    srli a1, a0, 31
738; RV32IMZB-NEXT:    srai a0, a0, 17
739; RV32IMZB-NEXT:    add a0, a0, a1
740; RV32IMZB-NEXT:    ret
741;
742; RV64IM-LABEL: sdiv16_constant_srai:
743; RV64IM:       # %bb.0:
744; RV64IM-NEXT:    slli a0, a0, 48
745; RV64IM-NEXT:    srai a0, a0, 48
746; RV64IM-NEXT:    lui a1, 6
747; RV64IM-NEXT:    addiw a1, a1, 1639
748; RV64IM-NEXT:    mul a0, a0, a1
749; RV64IM-NEXT:    srliw a1, a0, 31
750; RV64IM-NEXT:    srai a0, a0, 17
751; RV64IM-NEXT:    add a0, a0, a1
752; RV64IM-NEXT:    ret
753;
754; RV64IMZB-LABEL: sdiv16_constant_srai:
755; RV64IMZB:       # %bb.0:
756; RV64IMZB-NEXT:    sext.h a0, a0
757; RV64IMZB-NEXT:    lui a1, 6
758; RV64IMZB-NEXT:    addiw a1, a1, 1639
759; RV64IMZB-NEXT:    mul a0, a0, a1
760; RV64IMZB-NEXT:    srliw a1, a0, 31
761; RV64IMZB-NEXT:    srai a0, a0, 17
762; RV64IMZB-NEXT:    add a0, a0, a1
763; RV64IMZB-NEXT:    ret
764  %1 = sdiv i16 %a, 5
765  ret i16 %1
766}
767
768define i16 @sdiv16_constant_add_srai(i16 %a) nounwind {
769; RV32IM-LABEL: sdiv16_constant_add_srai:
770; RV32IM:       # %bb.0:
771; RV32IM-NEXT:    slli a1, a0, 16
772; RV32IM-NEXT:    srai a1, a1, 16
773; RV32IM-NEXT:    lui a2, 1048569
774; RV32IM-NEXT:    addi a2, a2, -1911
775; RV32IM-NEXT:    mul a1, a1, a2
776; RV32IM-NEXT:    srli a1, a1, 16
777; RV32IM-NEXT:    add a0, a1, a0
778; RV32IM-NEXT:    slli a0, a0, 16
779; RV32IM-NEXT:    srli a1, a0, 31
780; RV32IM-NEXT:    srai a0, a0, 19
781; RV32IM-NEXT:    add a0, a0, a1
782; RV32IM-NEXT:    ret
783;
784; RV32IMZB-LABEL: sdiv16_constant_add_srai:
785; RV32IMZB:       # %bb.0:
786; RV32IMZB-NEXT:    sext.h a1, a0
787; RV32IMZB-NEXT:    lui a2, 1048569
788; RV32IMZB-NEXT:    addi a2, a2, -1911
789; RV32IMZB-NEXT:    mul a1, a1, a2
790; RV32IMZB-NEXT:    srli a1, a1, 16
791; RV32IMZB-NEXT:    add a0, a1, a0
792; RV32IMZB-NEXT:    slli a0, a0, 16
793; RV32IMZB-NEXT:    srli a1, a0, 31
794; RV32IMZB-NEXT:    srai a0, a0, 19
795; RV32IMZB-NEXT:    add a0, a0, a1
796; RV32IMZB-NEXT:    ret
797;
798; RV64IM-LABEL: sdiv16_constant_add_srai:
799; RV64IM:       # %bb.0:
800; RV64IM-NEXT:    slli a1, a0, 48
801; RV64IM-NEXT:    srai a1, a1, 48
802; RV64IM-NEXT:    lui a2, 1048569
803; RV64IM-NEXT:    addiw a2, a2, -1911
804; RV64IM-NEXT:    mul a1, a1, a2
805; RV64IM-NEXT:    srli a1, a1, 16
806; RV64IM-NEXT:    addw a0, a1, a0
807; RV64IM-NEXT:    slli a0, a0, 48
808; RV64IM-NEXT:    srli a1, a0, 63
809; RV64IM-NEXT:    srai a0, a0, 51
810; RV64IM-NEXT:    add a0, a0, a1
811; RV64IM-NEXT:    ret
812;
813; RV64IMZB-LABEL: sdiv16_constant_add_srai:
814; RV64IMZB:       # %bb.0:
815; RV64IMZB-NEXT:    sext.h a1, a0
816; RV64IMZB-NEXT:    lui a2, 1048569
817; RV64IMZB-NEXT:    addiw a2, a2, -1911
818; RV64IMZB-NEXT:    mul a1, a1, a2
819; RV64IMZB-NEXT:    srli a1, a1, 16
820; RV64IMZB-NEXT:    addw a0, a1, a0
821; RV64IMZB-NEXT:    slli a0, a0, 48
822; RV64IMZB-NEXT:    srli a1, a0, 63
823; RV64IMZB-NEXT:    srai a0, a0, 51
824; RV64IMZB-NEXT:    add a0, a0, a1
825; RV64IMZB-NEXT:    ret
826  %1 = sdiv i16 %a, 15
827  ret i16 %1
828}
829
830define i16 @sdiv16_constant_sub_srai(i16 %a) nounwind {
831; RV32IM-LABEL: sdiv16_constant_sub_srai:
832; RV32IM:       # %bb.0:
833; RV32IM-NEXT:    slli a1, a0, 16
834; RV32IM-NEXT:    srai a1, a1, 16
835; RV32IM-NEXT:    lui a2, 7
836; RV32IM-NEXT:    addi a2, a2, 1911
837; RV32IM-NEXT:    mul a1, a1, a2
838; RV32IM-NEXT:    srli a1, a1, 16
839; RV32IM-NEXT:    sub a0, a1, a0
840; RV32IM-NEXT:    slli a0, a0, 16
841; RV32IM-NEXT:    srli a1, a0, 31
842; RV32IM-NEXT:    srai a0, a0, 19
843; RV32IM-NEXT:    add a0, a0, a1
844; RV32IM-NEXT:    ret
845;
846; RV32IMZB-LABEL: sdiv16_constant_sub_srai:
847; RV32IMZB:       # %bb.0:
848; RV32IMZB-NEXT:    sext.h a1, a0
849; RV32IMZB-NEXT:    lui a2, 7
850; RV32IMZB-NEXT:    addi a2, a2, 1911
851; RV32IMZB-NEXT:    mul a1, a1, a2
852; RV32IMZB-NEXT:    srli a1, a1, 16
853; RV32IMZB-NEXT:    sub a0, a1, a0
854; RV32IMZB-NEXT:    slli a0, a0, 16
855; RV32IMZB-NEXT:    srli a1, a0, 31
856; RV32IMZB-NEXT:    srai a0, a0, 19
857; RV32IMZB-NEXT:    add a0, a0, a1
858; RV32IMZB-NEXT:    ret
859;
860; RV64IM-LABEL: sdiv16_constant_sub_srai:
861; RV64IM:       # %bb.0:
862; RV64IM-NEXT:    slli a1, a0, 48
863; RV64IM-NEXT:    srai a1, a1, 48
864; RV64IM-NEXT:    lui a2, 7
865; RV64IM-NEXT:    addiw a2, a2, 1911
866; RV64IM-NEXT:    mul a1, a1, a2
867; RV64IM-NEXT:    srli a1, a1, 16
868; RV64IM-NEXT:    subw a0, a1, a0
869; RV64IM-NEXT:    slli a0, a0, 48
870; RV64IM-NEXT:    srli a1, a0, 63
871; RV64IM-NEXT:    srai a0, a0, 51
872; RV64IM-NEXT:    add a0, a0, a1
873; RV64IM-NEXT:    ret
874;
875; RV64IMZB-LABEL: sdiv16_constant_sub_srai:
876; RV64IMZB:       # %bb.0:
877; RV64IMZB-NEXT:    sext.h a1, a0
878; RV64IMZB-NEXT:    lui a2, 7
879; RV64IMZB-NEXT:    addiw a2, a2, 1911
880; RV64IMZB-NEXT:    mul a1, a1, a2
881; RV64IMZB-NEXT:    srli a1, a1, 16
882; RV64IMZB-NEXT:    subw a0, a1, a0
883; RV64IMZB-NEXT:    slli a0, a0, 48
884; RV64IMZB-NEXT:    srli a1, a0, 63
885; RV64IMZB-NEXT:    srai a0, a0, 51
886; RV64IMZB-NEXT:    add a0, a0, a1
887; RV64IMZB-NEXT:    ret
888  %1 = sdiv i16 %a, -15
889  ret i16 %1
890}
891