1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s  | FileCheck %s -check-prefix=RV32I
3; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s  | FileCheck %s -check-prefix=RV64I
4; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s  | FileCheck %s -check-prefix=RV32IF
5; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s  | FileCheck %s -check-prefix=RV64IF
6; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32f -verify-machineinstrs < %s  | FileCheck %s -check-prefix=RV32-ILP32F
7; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s  | FileCheck %s -check-prefix=RV64-LP64F
8; RUN: llc -mtriple=riscv32 -mattr=+f,+zfhmin -target-abi=ilp32f -verify-machineinstrs < %s  | FileCheck %s -check-prefix=RV32-ILP32ZFHMIN
9; RUN: llc -mtriple=riscv64 -mattr=+f,+zfhmin -target-abi=lp64f -verify-machineinstrs < %s  | FileCheck %s -check-prefix=RV64-LP64ZFHMIN
10
11; Tests passing half arguments and returns without Zfh.
12; Covers with and without F extension and ilp32f/ilp64f
13; calling conventions.
14
15define i32 @callee_half_in_regs(i32 %a, half %b) nounwind {
16; RV32I-LABEL: callee_half_in_regs:
17; RV32I:       # %bb.0:
18; RV32I-NEXT:    addi sp, sp, -16
19; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
20; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
21; RV32I-NEXT:    mv s0, a0
22; RV32I-NEXT:    slli a0, a1, 16
23; RV32I-NEXT:    srli a0, a0, 16
24; RV32I-NEXT:    call __extendhfsf2@plt
25; RV32I-NEXT:    call __fixsfsi@plt
26; RV32I-NEXT:    add a0, s0, a0
27; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
28; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
29; RV32I-NEXT:    addi sp, sp, 16
30; RV32I-NEXT:    ret
31;
32; RV64I-LABEL: callee_half_in_regs:
33; RV64I:       # %bb.0:
34; RV64I-NEXT:    addi sp, sp, -16
35; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
36; RV64I-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
37; RV64I-NEXT:    mv s0, a0
38; RV64I-NEXT:    slli a0, a1, 48
39; RV64I-NEXT:    srli a0, a0, 48
40; RV64I-NEXT:    call __extendhfsf2@plt
41; RV64I-NEXT:    call __fixsfdi@plt
42; RV64I-NEXT:    addw a0, s0, a0
43; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
44; RV64I-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
45; RV64I-NEXT:    addi sp, sp, 16
46; RV64I-NEXT:    ret
47;
48; RV32IF-LABEL: callee_half_in_regs:
49; RV32IF:       # %bb.0:
50; RV32IF-NEXT:    addi sp, sp, -16
51; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
52; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
53; RV32IF-NEXT:    mv s0, a0
54; RV32IF-NEXT:    mv a0, a1
55; RV32IF-NEXT:    call __extendhfsf2@plt
56; RV32IF-NEXT:    fmv.w.x ft0, a0
57; RV32IF-NEXT:    fcvt.w.s a0, ft0, rtz
58; RV32IF-NEXT:    add a0, s0, a0
59; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
60; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
61; RV32IF-NEXT:    addi sp, sp, 16
62; RV32IF-NEXT:    ret
63;
64; RV64IF-LABEL: callee_half_in_regs:
65; RV64IF:       # %bb.0:
66; RV64IF-NEXT:    addi sp, sp, -16
67; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
68; RV64IF-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
69; RV64IF-NEXT:    mv s0, a0
70; RV64IF-NEXT:    mv a0, a1
71; RV64IF-NEXT:    call __extendhfsf2@plt
72; RV64IF-NEXT:    fmv.w.x ft0, a0
73; RV64IF-NEXT:    fcvt.l.s a0, ft0, rtz
74; RV64IF-NEXT:    addw a0, s0, a0
75; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
76; RV64IF-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
77; RV64IF-NEXT:    addi sp, sp, 16
78; RV64IF-NEXT:    ret
79;
80; RV32-ILP32F-LABEL: callee_half_in_regs:
81; RV32-ILP32F:       # %bb.0:
82; RV32-ILP32F-NEXT:    addi sp, sp, -16
83; RV32-ILP32F-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
84; RV32-ILP32F-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
85; RV32-ILP32F-NEXT:    mv s0, a0
86; RV32-ILP32F-NEXT:    fmv.x.w a0, fa0
87; RV32-ILP32F-NEXT:    call __extendhfsf2@plt
88; RV32-ILP32F-NEXT:    fcvt.w.s a0, fa0, rtz
89; RV32-ILP32F-NEXT:    add a0, s0, a0
90; RV32-ILP32F-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
91; RV32-ILP32F-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
92; RV32-ILP32F-NEXT:    addi sp, sp, 16
93; RV32-ILP32F-NEXT:    ret
94;
95; RV64-LP64F-LABEL: callee_half_in_regs:
96; RV64-LP64F:       # %bb.0:
97; RV64-LP64F-NEXT:    addi sp, sp, -16
98; RV64-LP64F-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
99; RV64-LP64F-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
100; RV64-LP64F-NEXT:    mv s0, a0
101; RV64-LP64F-NEXT:    fmv.x.w a0, fa0
102; RV64-LP64F-NEXT:    call __extendhfsf2@plt
103; RV64-LP64F-NEXT:    fcvt.l.s a0, fa0, rtz
104; RV64-LP64F-NEXT:    addw a0, s0, a0
105; RV64-LP64F-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
106; RV64-LP64F-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
107; RV64-LP64F-NEXT:    addi sp, sp, 16
108; RV64-LP64F-NEXT:    ret
109;
110; RV32-ILP32ZFHMIN-LABEL: callee_half_in_regs:
111; RV32-ILP32ZFHMIN:       # %bb.0:
112; RV32-ILP32ZFHMIN-NEXT:    addi sp, sp, -16
113; RV32-ILP32ZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
114; RV32-ILP32ZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
115; RV32-ILP32ZFHMIN-NEXT:    mv s0, a0
116; RV32-ILP32ZFHMIN-NEXT:    fmv.x.w a0, fa0
117; RV32-ILP32ZFHMIN-NEXT:    call __extendhfsf2@plt
118; RV32-ILP32ZFHMIN-NEXT:    fcvt.w.s a0, fa0, rtz
119; RV32-ILP32ZFHMIN-NEXT:    add a0, s0, a0
120; RV32-ILP32ZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
121; RV32-ILP32ZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
122; RV32-ILP32ZFHMIN-NEXT:    addi sp, sp, 16
123; RV32-ILP32ZFHMIN-NEXT:    ret
124;
125; RV64-LP64ZFHMIN-LABEL: callee_half_in_regs:
126; RV64-LP64ZFHMIN:       # %bb.0:
127; RV64-LP64ZFHMIN-NEXT:    addi sp, sp, -16
128; RV64-LP64ZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
129; RV64-LP64ZFHMIN-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
130; RV64-LP64ZFHMIN-NEXT:    mv s0, a0
131; RV64-LP64ZFHMIN-NEXT:    fmv.x.w a0, fa0
132; RV64-LP64ZFHMIN-NEXT:    call __extendhfsf2@plt
133; RV64-LP64ZFHMIN-NEXT:    fcvt.l.s a0, fa0, rtz
134; RV64-LP64ZFHMIN-NEXT:    addw a0, s0, a0
135; RV64-LP64ZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
136; RV64-LP64ZFHMIN-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
137; RV64-LP64ZFHMIN-NEXT:    addi sp, sp, 16
138; RV64-LP64ZFHMIN-NEXT:    ret
139  %b_fptosi = fptosi half %b to i32
140  %1 = add i32 %a, %b_fptosi
141  ret i32 %1
142}
143
144define i32 @caller_half_in_regs() nounwind {
145; RV32I-LABEL: caller_half_in_regs:
146; RV32I:       # %bb.0:
147; RV32I-NEXT:    addi sp, sp, -16
148; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
149; RV32I-NEXT:    li a0, 1
150; RV32I-NEXT:    lui a1, 4
151; RV32I-NEXT:    call callee_half_in_regs@plt
152; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
153; RV32I-NEXT:    addi sp, sp, 16
154; RV32I-NEXT:    ret
155;
156; RV64I-LABEL: caller_half_in_regs:
157; RV64I:       # %bb.0:
158; RV64I-NEXT:    addi sp, sp, -16
159; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
160; RV64I-NEXT:    li a0, 1
161; RV64I-NEXT:    lui a1, 4
162; RV64I-NEXT:    call callee_half_in_regs@plt
163; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
164; RV64I-NEXT:    addi sp, sp, 16
165; RV64I-NEXT:    ret
166;
167; RV32IF-LABEL: caller_half_in_regs:
168; RV32IF:       # %bb.0:
169; RV32IF-NEXT:    addi sp, sp, -16
170; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
171; RV32IF-NEXT:    li a0, 1
172; RV32IF-NEXT:    lui a1, 1048564
173; RV32IF-NEXT:    call callee_half_in_regs@plt
174; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
175; RV32IF-NEXT:    addi sp, sp, 16
176; RV32IF-NEXT:    ret
177;
178; RV64IF-LABEL: caller_half_in_regs:
179; RV64IF:       # %bb.0:
180; RV64IF-NEXT:    addi sp, sp, -16
181; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
182; RV64IF-NEXT:    lui a0, %hi(.LCPI1_0)
183; RV64IF-NEXT:    flw ft0, %lo(.LCPI1_0)(a0)
184; RV64IF-NEXT:    fmv.x.w a1, ft0
185; RV64IF-NEXT:    li a0, 1
186; RV64IF-NEXT:    call callee_half_in_regs@plt
187; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
188; RV64IF-NEXT:    addi sp, sp, 16
189; RV64IF-NEXT:    ret
190;
191; RV32-ILP32F-LABEL: caller_half_in_regs:
192; RV32-ILP32F:       # %bb.0:
193; RV32-ILP32F-NEXT:    addi sp, sp, -16
194; RV32-ILP32F-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
195; RV32-ILP32F-NEXT:    lui a0, %hi(.LCPI1_0)
196; RV32-ILP32F-NEXT:    flw fa0, %lo(.LCPI1_0)(a0)
197; RV32-ILP32F-NEXT:    li a0, 1
198; RV32-ILP32F-NEXT:    call callee_half_in_regs@plt
199; RV32-ILP32F-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
200; RV32-ILP32F-NEXT:    addi sp, sp, 16
201; RV32-ILP32F-NEXT:    ret
202;
203; RV64-LP64F-LABEL: caller_half_in_regs:
204; RV64-LP64F:       # %bb.0:
205; RV64-LP64F-NEXT:    addi sp, sp, -16
206; RV64-LP64F-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
207; RV64-LP64F-NEXT:    lui a0, %hi(.LCPI1_0)
208; RV64-LP64F-NEXT:    flw fa0, %lo(.LCPI1_0)(a0)
209; RV64-LP64F-NEXT:    li a0, 1
210; RV64-LP64F-NEXT:    call callee_half_in_regs@plt
211; RV64-LP64F-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
212; RV64-LP64F-NEXT:    addi sp, sp, 16
213; RV64-LP64F-NEXT:    ret
214;
215; RV32-ILP32ZFHMIN-LABEL: caller_half_in_regs:
216; RV32-ILP32ZFHMIN:       # %bb.0:
217; RV32-ILP32ZFHMIN-NEXT:    addi sp, sp, -16
218; RV32-ILP32ZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
219; RV32-ILP32ZFHMIN-NEXT:    lui a0, %hi(.LCPI1_0)
220; RV32-ILP32ZFHMIN-NEXT:    flw fa0, %lo(.LCPI1_0)(a0)
221; RV32-ILP32ZFHMIN-NEXT:    li a0, 1
222; RV32-ILP32ZFHMIN-NEXT:    call callee_half_in_regs@plt
223; RV32-ILP32ZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
224; RV32-ILP32ZFHMIN-NEXT:    addi sp, sp, 16
225; RV32-ILP32ZFHMIN-NEXT:    ret
226;
227; RV64-LP64ZFHMIN-LABEL: caller_half_in_regs:
228; RV64-LP64ZFHMIN:       # %bb.0:
229; RV64-LP64ZFHMIN-NEXT:    addi sp, sp, -16
230; RV64-LP64ZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
231; RV64-LP64ZFHMIN-NEXT:    lui a0, %hi(.LCPI1_0)
232; RV64-LP64ZFHMIN-NEXT:    flw fa0, %lo(.LCPI1_0)(a0)
233; RV64-LP64ZFHMIN-NEXT:    li a0, 1
234; RV64-LP64ZFHMIN-NEXT:    call callee_half_in_regs@plt
235; RV64-LP64ZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
236; RV64-LP64ZFHMIN-NEXT:    addi sp, sp, 16
237; RV64-LP64ZFHMIN-NEXT:    ret
238  %1 = call i32 @callee_half_in_regs(i32 1, half 2.0)
239  ret i32 %1
240}
241
242define i32 @callee_half_on_stack(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, half %i) nounwind {
243; RV32I-LABEL: callee_half_on_stack:
244; RV32I:       # %bb.0:
245; RV32I-NEXT:    addi sp, sp, -16
246; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
247; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
248; RV32I-NEXT:    lhu a0, 16(sp)
249; RV32I-NEXT:    mv s0, a7
250; RV32I-NEXT:    call __extendhfsf2@plt
251; RV32I-NEXT:    call __fixsfsi@plt
252; RV32I-NEXT:    add a0, s0, a0
253; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
254; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
255; RV32I-NEXT:    addi sp, sp, 16
256; RV32I-NEXT:    ret
257;
258; RV64I-LABEL: callee_half_on_stack:
259; RV64I:       # %bb.0:
260; RV64I-NEXT:    addi sp, sp, -16
261; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
262; RV64I-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
263; RV64I-NEXT:    lhu a0, 16(sp)
264; RV64I-NEXT:    mv s0, a7
265; RV64I-NEXT:    call __extendhfsf2@plt
266; RV64I-NEXT:    call __fixsfdi@plt
267; RV64I-NEXT:    addw a0, s0, a0
268; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
269; RV64I-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
270; RV64I-NEXT:    addi sp, sp, 16
271; RV64I-NEXT:    ret
272;
273; RV32IF-LABEL: callee_half_on_stack:
274; RV32IF:       # %bb.0:
275; RV32IF-NEXT:    addi sp, sp, -16
276; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
277; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
278; RV32IF-NEXT:    lhu a0, 16(sp)
279; RV32IF-NEXT:    mv s0, a7
280; RV32IF-NEXT:    call __extendhfsf2@plt
281; RV32IF-NEXT:    fmv.w.x ft0, a0
282; RV32IF-NEXT:    fcvt.w.s a0, ft0, rtz
283; RV32IF-NEXT:    add a0, s0, a0
284; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
285; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
286; RV32IF-NEXT:    addi sp, sp, 16
287; RV32IF-NEXT:    ret
288;
289; RV64IF-LABEL: callee_half_on_stack:
290; RV64IF:       # %bb.0:
291; RV64IF-NEXT:    addi sp, sp, -16
292; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
293; RV64IF-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
294; RV64IF-NEXT:    lhu a0, 16(sp)
295; RV64IF-NEXT:    mv s0, a7
296; RV64IF-NEXT:    call __extendhfsf2@plt
297; RV64IF-NEXT:    fmv.w.x ft0, a0
298; RV64IF-NEXT:    fcvt.l.s a0, ft0, rtz
299; RV64IF-NEXT:    addw a0, s0, a0
300; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
301; RV64IF-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
302; RV64IF-NEXT:    addi sp, sp, 16
303; RV64IF-NEXT:    ret
304;
305; RV32-ILP32F-LABEL: callee_half_on_stack:
306; RV32-ILP32F:       # %bb.0:
307; RV32-ILP32F-NEXT:    addi sp, sp, -16
308; RV32-ILP32F-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
309; RV32-ILP32F-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
310; RV32-ILP32F-NEXT:    mv s0, a7
311; RV32-ILP32F-NEXT:    fmv.x.w a0, fa0
312; RV32-ILP32F-NEXT:    call __extendhfsf2@plt
313; RV32-ILP32F-NEXT:    fcvt.w.s a0, fa0, rtz
314; RV32-ILP32F-NEXT:    add a0, s0, a0
315; RV32-ILP32F-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
316; RV32-ILP32F-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
317; RV32-ILP32F-NEXT:    addi sp, sp, 16
318; RV32-ILP32F-NEXT:    ret
319;
320; RV64-LP64F-LABEL: callee_half_on_stack:
321; RV64-LP64F:       # %bb.0:
322; RV64-LP64F-NEXT:    addi sp, sp, -16
323; RV64-LP64F-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
324; RV64-LP64F-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
325; RV64-LP64F-NEXT:    mv s0, a7
326; RV64-LP64F-NEXT:    fmv.x.w a0, fa0
327; RV64-LP64F-NEXT:    call __extendhfsf2@plt
328; RV64-LP64F-NEXT:    fcvt.l.s a0, fa0, rtz
329; RV64-LP64F-NEXT:    addw a0, s0, a0
330; RV64-LP64F-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
331; RV64-LP64F-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
332; RV64-LP64F-NEXT:    addi sp, sp, 16
333; RV64-LP64F-NEXT:    ret
334;
335; RV32-ILP32ZFHMIN-LABEL: callee_half_on_stack:
336; RV32-ILP32ZFHMIN:       # %bb.0:
337; RV32-ILP32ZFHMIN-NEXT:    addi sp, sp, -16
338; RV32-ILP32ZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
339; RV32-ILP32ZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
340; RV32-ILP32ZFHMIN-NEXT:    mv s0, a7
341; RV32-ILP32ZFHMIN-NEXT:    fmv.x.w a0, fa0
342; RV32-ILP32ZFHMIN-NEXT:    call __extendhfsf2@plt
343; RV32-ILP32ZFHMIN-NEXT:    fcvt.w.s a0, fa0, rtz
344; RV32-ILP32ZFHMIN-NEXT:    add a0, s0, a0
345; RV32-ILP32ZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
346; RV32-ILP32ZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
347; RV32-ILP32ZFHMIN-NEXT:    addi sp, sp, 16
348; RV32-ILP32ZFHMIN-NEXT:    ret
349;
350; RV64-LP64ZFHMIN-LABEL: callee_half_on_stack:
351; RV64-LP64ZFHMIN:       # %bb.0:
352; RV64-LP64ZFHMIN-NEXT:    addi sp, sp, -16
353; RV64-LP64ZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
354; RV64-LP64ZFHMIN-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
355; RV64-LP64ZFHMIN-NEXT:    mv s0, a7
356; RV64-LP64ZFHMIN-NEXT:    fmv.x.w a0, fa0
357; RV64-LP64ZFHMIN-NEXT:    call __extendhfsf2@plt
358; RV64-LP64ZFHMIN-NEXT:    fcvt.l.s a0, fa0, rtz
359; RV64-LP64ZFHMIN-NEXT:    addw a0, s0, a0
360; RV64-LP64ZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
361; RV64-LP64ZFHMIN-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
362; RV64-LP64ZFHMIN-NEXT:    addi sp, sp, 16
363; RV64-LP64ZFHMIN-NEXT:    ret
364  %1 = fptosi half %i to i32
365  %2 = add i32 %h, %1
366  ret i32 %2
367}
368
369define i32 @caller_half_on_stack() nounwind {
370; RV32I-LABEL: caller_half_on_stack:
371; RV32I:       # %bb.0:
372; RV32I-NEXT:    addi sp, sp, -16
373; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
374; RV32I-NEXT:    lui a0, 5
375; RV32I-NEXT:    addi t0, a0, -1792
376; RV32I-NEXT:    li a0, 1
377; RV32I-NEXT:    li a1, 2
378; RV32I-NEXT:    li a2, 3
379; RV32I-NEXT:    li a3, 4
380; RV32I-NEXT:    li a4, 5
381; RV32I-NEXT:    li a5, 6
382; RV32I-NEXT:    li a6, 7
383; RV32I-NEXT:    li a7, 8
384; RV32I-NEXT:    sw t0, 0(sp)
385; RV32I-NEXT:    call callee_half_on_stack@plt
386; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
387; RV32I-NEXT:    addi sp, sp, 16
388; RV32I-NEXT:    ret
389;
390; RV64I-LABEL: caller_half_on_stack:
391; RV64I:       # %bb.0:
392; RV64I-NEXT:    addi sp, sp, -16
393; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
394; RV64I-NEXT:    lui a0, 5
395; RV64I-NEXT:    addiw t0, a0, -1792
396; RV64I-NEXT:    li a0, 1
397; RV64I-NEXT:    li a1, 2
398; RV64I-NEXT:    li a2, 3
399; RV64I-NEXT:    li a3, 4
400; RV64I-NEXT:    li a4, 5
401; RV64I-NEXT:    li a5, 6
402; RV64I-NEXT:    li a6, 7
403; RV64I-NEXT:    li a7, 8
404; RV64I-NEXT:    sd t0, 0(sp)
405; RV64I-NEXT:    call callee_half_on_stack@plt
406; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
407; RV64I-NEXT:    addi sp, sp, 16
408; RV64I-NEXT:    ret
409;
410; RV32IF-LABEL: caller_half_on_stack:
411; RV32IF:       # %bb.0:
412; RV32IF-NEXT:    addi sp, sp, -16
413; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
414; RV32IF-NEXT:    lui a0, 1048565
415; RV32IF-NEXT:    addi t0, a0, -1792
416; RV32IF-NEXT:    li a0, 1
417; RV32IF-NEXT:    li a1, 2
418; RV32IF-NEXT:    li a2, 3
419; RV32IF-NEXT:    li a3, 4
420; RV32IF-NEXT:    li a4, 5
421; RV32IF-NEXT:    li a5, 6
422; RV32IF-NEXT:    li a6, 7
423; RV32IF-NEXT:    li a7, 8
424; RV32IF-NEXT:    sw t0, 0(sp)
425; RV32IF-NEXT:    call callee_half_on_stack@plt
426; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
427; RV32IF-NEXT:    addi sp, sp, 16
428; RV32IF-NEXT:    ret
429;
430; RV64IF-LABEL: caller_half_on_stack:
431; RV64IF:       # %bb.0:
432; RV64IF-NEXT:    addi sp, sp, -16
433; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
434; RV64IF-NEXT:    lui a0, 1048565
435; RV64IF-NEXT:    addiw t0, a0, -1792
436; RV64IF-NEXT:    li a0, 1
437; RV64IF-NEXT:    li a1, 2
438; RV64IF-NEXT:    li a2, 3
439; RV64IF-NEXT:    li a3, 4
440; RV64IF-NEXT:    li a4, 5
441; RV64IF-NEXT:    li a5, 6
442; RV64IF-NEXT:    li a6, 7
443; RV64IF-NEXT:    li a7, 8
444; RV64IF-NEXT:    sw t0, 0(sp)
445; RV64IF-NEXT:    call callee_half_on_stack@plt
446; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
447; RV64IF-NEXT:    addi sp, sp, 16
448; RV64IF-NEXT:    ret
449;
450; RV32-ILP32F-LABEL: caller_half_on_stack:
451; RV32-ILP32F:       # %bb.0:
452; RV32-ILP32F-NEXT:    addi sp, sp, -16
453; RV32-ILP32F-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
454; RV32-ILP32F-NEXT:    lui a0, %hi(.LCPI3_0)
455; RV32-ILP32F-NEXT:    flw fa0, %lo(.LCPI3_0)(a0)
456; RV32-ILP32F-NEXT:    li a0, 1
457; RV32-ILP32F-NEXT:    li a1, 2
458; RV32-ILP32F-NEXT:    li a2, 3
459; RV32-ILP32F-NEXT:    li a3, 4
460; RV32-ILP32F-NEXT:    li a4, 5
461; RV32-ILP32F-NEXT:    li a5, 6
462; RV32-ILP32F-NEXT:    li a6, 7
463; RV32-ILP32F-NEXT:    li a7, 8
464; RV32-ILP32F-NEXT:    call callee_half_on_stack@plt
465; RV32-ILP32F-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
466; RV32-ILP32F-NEXT:    addi sp, sp, 16
467; RV32-ILP32F-NEXT:    ret
468;
469; RV64-LP64F-LABEL: caller_half_on_stack:
470; RV64-LP64F:       # %bb.0:
471; RV64-LP64F-NEXT:    addi sp, sp, -16
472; RV64-LP64F-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
473; RV64-LP64F-NEXT:    lui a0, %hi(.LCPI3_0)
474; RV64-LP64F-NEXT:    flw fa0, %lo(.LCPI3_0)(a0)
475; RV64-LP64F-NEXT:    li a0, 1
476; RV64-LP64F-NEXT:    li a1, 2
477; RV64-LP64F-NEXT:    li a2, 3
478; RV64-LP64F-NEXT:    li a3, 4
479; RV64-LP64F-NEXT:    li a4, 5
480; RV64-LP64F-NEXT:    li a5, 6
481; RV64-LP64F-NEXT:    li a6, 7
482; RV64-LP64F-NEXT:    li a7, 8
483; RV64-LP64F-NEXT:    call callee_half_on_stack@plt
484; RV64-LP64F-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
485; RV64-LP64F-NEXT:    addi sp, sp, 16
486; RV64-LP64F-NEXT:    ret
487;
488; RV32-ILP32ZFHMIN-LABEL: caller_half_on_stack:
489; RV32-ILP32ZFHMIN:       # %bb.0:
490; RV32-ILP32ZFHMIN-NEXT:    addi sp, sp, -16
491; RV32-ILP32ZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
492; RV32-ILP32ZFHMIN-NEXT:    lui a0, %hi(.LCPI3_0)
493; RV32-ILP32ZFHMIN-NEXT:    flw fa0, %lo(.LCPI3_0)(a0)
494; RV32-ILP32ZFHMIN-NEXT:    li a0, 1
495; RV32-ILP32ZFHMIN-NEXT:    li a1, 2
496; RV32-ILP32ZFHMIN-NEXT:    li a2, 3
497; RV32-ILP32ZFHMIN-NEXT:    li a3, 4
498; RV32-ILP32ZFHMIN-NEXT:    li a4, 5
499; RV32-ILP32ZFHMIN-NEXT:    li a5, 6
500; RV32-ILP32ZFHMIN-NEXT:    li a6, 7
501; RV32-ILP32ZFHMIN-NEXT:    li a7, 8
502; RV32-ILP32ZFHMIN-NEXT:    call callee_half_on_stack@plt
503; RV32-ILP32ZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
504; RV32-ILP32ZFHMIN-NEXT:    addi sp, sp, 16
505; RV32-ILP32ZFHMIN-NEXT:    ret
506;
507; RV64-LP64ZFHMIN-LABEL: caller_half_on_stack:
508; RV64-LP64ZFHMIN:       # %bb.0:
509; RV64-LP64ZFHMIN-NEXT:    addi sp, sp, -16
510; RV64-LP64ZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
511; RV64-LP64ZFHMIN-NEXT:    lui a0, %hi(.LCPI3_0)
512; RV64-LP64ZFHMIN-NEXT:    flw fa0, %lo(.LCPI3_0)(a0)
513; RV64-LP64ZFHMIN-NEXT:    li a0, 1
514; RV64-LP64ZFHMIN-NEXT:    li a1, 2
515; RV64-LP64ZFHMIN-NEXT:    li a2, 3
516; RV64-LP64ZFHMIN-NEXT:    li a3, 4
517; RV64-LP64ZFHMIN-NEXT:    li a4, 5
518; RV64-LP64ZFHMIN-NEXT:    li a5, 6
519; RV64-LP64ZFHMIN-NEXT:    li a6, 7
520; RV64-LP64ZFHMIN-NEXT:    li a7, 8
521; RV64-LP64ZFHMIN-NEXT:    call callee_half_on_stack@plt
522; RV64-LP64ZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
523; RV64-LP64ZFHMIN-NEXT:    addi sp, sp, 16
524; RV64-LP64ZFHMIN-NEXT:    ret
525  %1 = call i32 @callee_half_on_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, half 10.0)
526  ret i32 %1
527}
528
529define half @callee_half_ret() nounwind {
530; RV32I-LABEL: callee_half_ret:
531; RV32I:       # %bb.0:
532; RV32I-NEXT:    lui a0, 4
533; RV32I-NEXT:    addi a0, a0, -1024
534; RV32I-NEXT:    ret
535;
536; RV64I-LABEL: callee_half_ret:
537; RV64I:       # %bb.0:
538; RV64I-NEXT:    lui a0, 4
539; RV64I-NEXT:    addiw a0, a0, -1024
540; RV64I-NEXT:    ret
541;
542; RV32IF-LABEL: callee_half_ret:
543; RV32IF:       # %bb.0:
544; RV32IF-NEXT:    lui a0, 1048564
545; RV32IF-NEXT:    addi a0, a0, -1024
546; RV32IF-NEXT:    ret
547;
548; RV64IF-LABEL: callee_half_ret:
549; RV64IF:       # %bb.0:
550; RV64IF-NEXT:    lui a0, %hi(.LCPI4_0)
551; RV64IF-NEXT:    flw ft0, %lo(.LCPI4_0)(a0)
552; RV64IF-NEXT:    fmv.x.w a0, ft0
553; RV64IF-NEXT:    ret
554;
555; RV32-ILP32F-LABEL: callee_half_ret:
556; RV32-ILP32F:       # %bb.0:
557; RV32-ILP32F-NEXT:    lui a0, %hi(.LCPI4_0)
558; RV32-ILP32F-NEXT:    flw fa0, %lo(.LCPI4_0)(a0)
559; RV32-ILP32F-NEXT:    ret
560;
561; RV64-LP64F-LABEL: callee_half_ret:
562; RV64-LP64F:       # %bb.0:
563; RV64-LP64F-NEXT:    lui a0, %hi(.LCPI4_0)
564; RV64-LP64F-NEXT:    flw fa0, %lo(.LCPI4_0)(a0)
565; RV64-LP64F-NEXT:    ret
566;
567; RV32-ILP32ZFHMIN-LABEL: callee_half_ret:
568; RV32-ILP32ZFHMIN:       # %bb.0:
569; RV32-ILP32ZFHMIN-NEXT:    lui a0, %hi(.LCPI4_0)
570; RV32-ILP32ZFHMIN-NEXT:    flw fa0, %lo(.LCPI4_0)(a0)
571; RV32-ILP32ZFHMIN-NEXT:    ret
572;
573; RV64-LP64ZFHMIN-LABEL: callee_half_ret:
574; RV64-LP64ZFHMIN:       # %bb.0:
575; RV64-LP64ZFHMIN-NEXT:    lui a0, %hi(.LCPI4_0)
576; RV64-LP64ZFHMIN-NEXT:    flw fa0, %lo(.LCPI4_0)(a0)
577; RV64-LP64ZFHMIN-NEXT:    ret
578  ret half 1.0
579}
580
581define i32 @caller_half_ret() nounwind {
582; RV32I-LABEL: caller_half_ret:
583; RV32I:       # %bb.0:
584; RV32I-NEXT:    addi sp, sp, -16
585; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
586; RV32I-NEXT:    call callee_half_ret@plt
587; RV32I-NEXT:    slli a0, a0, 16
588; RV32I-NEXT:    srli a0, a0, 16
589; RV32I-NEXT:    call __extendhfsf2@plt
590; RV32I-NEXT:    call __fixsfsi@plt
591; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
592; RV32I-NEXT:    addi sp, sp, 16
593; RV32I-NEXT:    ret
594;
595; RV64I-LABEL: caller_half_ret:
596; RV64I:       # %bb.0:
597; RV64I-NEXT:    addi sp, sp, -16
598; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
599; RV64I-NEXT:    call callee_half_ret@plt
600; RV64I-NEXT:    slli a0, a0, 48
601; RV64I-NEXT:    srli a0, a0, 48
602; RV64I-NEXT:    call __extendhfsf2@plt
603; RV64I-NEXT:    call __fixsfdi@plt
604; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
605; RV64I-NEXT:    addi sp, sp, 16
606; RV64I-NEXT:    ret
607;
608; RV32IF-LABEL: caller_half_ret:
609; RV32IF:       # %bb.0:
610; RV32IF-NEXT:    addi sp, sp, -16
611; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
612; RV32IF-NEXT:    call callee_half_ret@plt
613; RV32IF-NEXT:    call __extendhfsf2@plt
614; RV32IF-NEXT:    fmv.w.x ft0, a0
615; RV32IF-NEXT:    fcvt.w.s a0, ft0, rtz
616; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
617; RV32IF-NEXT:    addi sp, sp, 16
618; RV32IF-NEXT:    ret
619;
620; RV64IF-LABEL: caller_half_ret:
621; RV64IF:       # %bb.0:
622; RV64IF-NEXT:    addi sp, sp, -16
623; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
624; RV64IF-NEXT:    call callee_half_ret@plt
625; RV64IF-NEXT:    call __extendhfsf2@plt
626; RV64IF-NEXT:    fmv.w.x ft0, a0
627; RV64IF-NEXT:    fcvt.l.s a0, ft0, rtz
628; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
629; RV64IF-NEXT:    addi sp, sp, 16
630; RV64IF-NEXT:    ret
631;
632; RV32-ILP32F-LABEL: caller_half_ret:
633; RV32-ILP32F:       # %bb.0:
634; RV32-ILP32F-NEXT:    addi sp, sp, -16
635; RV32-ILP32F-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
636; RV32-ILP32F-NEXT:    call callee_half_ret@plt
637; RV32-ILP32F-NEXT:    fmv.x.w a0, fa0
638; RV32-ILP32F-NEXT:    call __extendhfsf2@plt
639; RV32-ILP32F-NEXT:    fcvt.w.s a0, fa0, rtz
640; RV32-ILP32F-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
641; RV32-ILP32F-NEXT:    addi sp, sp, 16
642; RV32-ILP32F-NEXT:    ret
643;
644; RV64-LP64F-LABEL: caller_half_ret:
645; RV64-LP64F:       # %bb.0:
646; RV64-LP64F-NEXT:    addi sp, sp, -16
647; RV64-LP64F-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
648; RV64-LP64F-NEXT:    call callee_half_ret@plt
649; RV64-LP64F-NEXT:    fmv.x.w a0, fa0
650; RV64-LP64F-NEXT:    call __extendhfsf2@plt
651; RV64-LP64F-NEXT:    fcvt.l.s a0, fa0, rtz
652; RV64-LP64F-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
653; RV64-LP64F-NEXT:    addi sp, sp, 16
654; RV64-LP64F-NEXT:    ret
655;
656; RV32-ILP32ZFHMIN-LABEL: caller_half_ret:
657; RV32-ILP32ZFHMIN:       # %bb.0:
658; RV32-ILP32ZFHMIN-NEXT:    addi sp, sp, -16
659; RV32-ILP32ZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
660; RV32-ILP32ZFHMIN-NEXT:    call callee_half_ret@plt
661; RV32-ILP32ZFHMIN-NEXT:    fmv.x.w a0, fa0
662; RV32-ILP32ZFHMIN-NEXT:    call __extendhfsf2@plt
663; RV32-ILP32ZFHMIN-NEXT:    fcvt.w.s a0, fa0, rtz
664; RV32-ILP32ZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
665; RV32-ILP32ZFHMIN-NEXT:    addi sp, sp, 16
666; RV32-ILP32ZFHMIN-NEXT:    ret
667;
668; RV64-LP64ZFHMIN-LABEL: caller_half_ret:
669; RV64-LP64ZFHMIN:       # %bb.0:
670; RV64-LP64ZFHMIN-NEXT:    addi sp, sp, -16
671; RV64-LP64ZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
672; RV64-LP64ZFHMIN-NEXT:    call callee_half_ret@plt
673; RV64-LP64ZFHMIN-NEXT:    fmv.x.w a0, fa0
674; RV64-LP64ZFHMIN-NEXT:    call __extendhfsf2@plt
675; RV64-LP64ZFHMIN-NEXT:    fcvt.l.s a0, fa0, rtz
676; RV64-LP64ZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
677; RV64-LP64ZFHMIN-NEXT:    addi sp, sp, 16
678; RV64-LP64ZFHMIN-NEXT:    ret
679  %1 = call half @callee_half_ret()
680  %2 = fptosi half %1 to i32
681  ret i32 %2
682}
683